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560 lines
15 KiB
560 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Tehuti Networks(R) Network Driver |
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* Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved |
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*/ |
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#ifndef _TEHUTI_H |
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#define _TEHUTI_H |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/ethtool.h> |
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#include <linux/mii.h> |
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#include <linux/crc32.h> |
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#include <linux/uaccess.h> |
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#include <linux/in.h> |
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#include <linux/ip.h> |
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#include <linux/tcp.h> |
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#include <linux/sched.h> |
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#include <linux/tty.h> |
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#include <linux/if_vlan.h> |
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#include <linux/interrupt.h> |
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#include <linux/vmalloc.h> |
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#include <linux/firmware.h> |
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#include <asm/byteorder.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/slab.h> |
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/* Compile Time Switches */ |
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/* start */ |
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#define BDX_TSO |
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#define BDX_LLTX |
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#define BDX_DELAY_WPTR |
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/* #define BDX_MSI */ |
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/* end */ |
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#if !defined CONFIG_PCI_MSI |
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# undef BDX_MSI |
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#endif |
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#define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
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NETIF_MSG_PROBE | \ |
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NETIF_MSG_LINK) |
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/* ioctl ops */ |
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#define BDX_OP_READ 1 |
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#define BDX_OP_WRITE 2 |
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/* RX copy break size */ |
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#define BDX_COPYBREAK 257 |
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#define DRIVER_AUTHOR "Tehuti Networks(R)" |
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#define BDX_DRV_DESC "Tehuti Networks(R) Network Driver" |
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#define BDX_DRV_NAME "tehuti" |
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#define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC" |
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#define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC" |
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#define BDX_DRV_VERSION "7.29.3" |
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#ifdef BDX_MSI |
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# define BDX_MSI_STRING "msi " |
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#else |
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# define BDX_MSI_STRING "" |
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#endif |
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/* netdev tx queue len for Luxor. default value is, btw, 1000 |
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* ifcontig eth1 txqueuelen 3000 - to change it at runtime */ |
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#define BDX_NDEV_TXQ_LEN 3000 |
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/* Max MTU for Jumbo Frame mode, per tehutinetworks.net Features FAQ is 16k */ |
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#define BDX_MAX_MTU (16 * 1024) |
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#define FIFO_SIZE 4096 |
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#define FIFO_EXTRA_SPACE 1024 |
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#if BITS_PER_LONG == 64 |
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# define H32_64(x) (u32) ((u64)(x) >> 32) |
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# define L32_64(x) (u32) ((u64)(x) & 0xffffffff) |
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#elif BITS_PER_LONG == 32 |
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# define H32_64(x) 0 |
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# define L32_64(x) ((u32) (x)) |
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#else /* BITS_PER_LONG == ?? */ |
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# error BITS_PER_LONG is undefined. Must be 64 or 32 |
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#endif /* BITS_PER_LONG */ |
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#ifdef __BIG_ENDIAN |
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# define CPU_CHIP_SWAP32(x) swab32(x) |
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# define CPU_CHIP_SWAP16(x) swab16(x) |
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#else |
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# define CPU_CHIP_SWAP32(x) (x) |
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# define CPU_CHIP_SWAP16(x) (x) |
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#endif |
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#define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) |
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#define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) |
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#ifndef NET_IP_ALIGN |
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# define NET_IP_ALIGN 2 |
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#endif |
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#ifndef NETDEV_TX_OK |
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# define NETDEV_TX_OK 0 |
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#endif |
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#define LUXOR_MAX_PORT 2 |
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#define BDX_MAX_RX_DONE 150 |
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#define BDX_TXF_DESC_SZ 16 |
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#define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) |
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#define BDX_MIN_TX_LEVEL 256 |
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#define BDX_NO_UPD_PACKETS 40 |
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struct pci_nic { |
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int port_num; |
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void __iomem *regs; |
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int irq_type; |
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struct bdx_priv *priv[LUXOR_MAX_PORT]; |
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}; |
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enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX }; |
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#define PCK_TH_MULT 128 |
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#define INT_COAL_MULT 2 |
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#define BITS_MASK(nbits) ((1<<nbits)-1) |
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#define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits)) |
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#define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift) |
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#define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift) |
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#define BITS_SHIFT_CLEAR(x, nbits, nshift) \ |
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((x)&(~BITS_SHIFT_MASK(nbits, nshift))) |
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#define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) |
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#define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15) |
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#define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16) |
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#define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20) |
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#define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \ |
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((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20)) |
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struct fifo { |
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dma_addr_t da; /* physical address of fifo (used by HW) */ |
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char *va; /* virtual address of fifo (used by SW) */ |
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u32 rptr, wptr; /* cached values of RPTR and WPTR registers, |
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they're 32 bits on both 32 and 64 archs */ |
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u16 reg_CFG0, reg_CFG1; |
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u16 reg_RPTR, reg_WPTR; |
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u16 memsz; /* memory size allocated for fifo */ |
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u16 size_mask; |
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u16 pktsz; /* skb packet size to allocate */ |
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u16 rcvno; /* number of buffers that come from this RXF */ |
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}; |
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struct txf_fifo { |
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struct fifo m; /* minimal set of variables used by all fifos */ |
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}; |
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struct txd_fifo { |
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struct fifo m; /* minimal set of variables used by all fifos */ |
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}; |
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struct rxf_fifo { |
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struct fifo m; /* minimal set of variables used by all fifos */ |
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}; |
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struct rxd_fifo { |
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struct fifo m; /* minimal set of variables used by all fifos */ |
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}; |
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struct rx_map { |
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u64 dma; |
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struct sk_buff *skb; |
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}; |
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struct rxdb { |
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int *stack; |
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struct rx_map *elems; |
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int nelem; |
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int top; |
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}; |
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union bdx_dma_addr { |
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dma_addr_t dma; |
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struct sk_buff *skb; |
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}; |
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/* Entry in the db. |
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* if len == 0 addr is dma |
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* if len != 0 addr is skb */ |
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struct tx_map { |
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union bdx_dma_addr addr; |
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int len; |
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}; |
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/* tx database - implemented as circular fifo buffer*/ |
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struct txdb { |
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struct tx_map *start; /* points to the first element */ |
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struct tx_map *end; /* points just AFTER the last element */ |
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struct tx_map *rptr; /* points to the next element to read */ |
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struct tx_map *wptr; /* points to the next element to write */ |
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int size; /* number of elements in the db */ |
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}; |
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/*Internal stats structure*/ |
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struct bdx_stats { |
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u64 InUCast; /* 0x7200 */ |
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u64 InMCast; /* 0x7210 */ |
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u64 InBCast; /* 0x7220 */ |
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u64 InPkts; /* 0x7230 */ |
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u64 InErrors; /* 0x7240 */ |
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u64 InDropped; /* 0x7250 */ |
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u64 FrameTooLong; /* 0x7260 */ |
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u64 FrameSequenceErrors; /* 0x7270 */ |
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u64 InVLAN; /* 0x7280 */ |
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u64 InDroppedDFE; /* 0x7290 */ |
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u64 InDroppedIntFull; /* 0x72A0 */ |
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u64 InFrameAlignErrors; /* 0x72B0 */ |
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/* 0x72C0-0x72E0 RSRV */ |
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u64 OutUCast; /* 0x72F0 */ |
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u64 OutMCast; /* 0x7300 */ |
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u64 OutBCast; /* 0x7310 */ |
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u64 OutPkts; /* 0x7320 */ |
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/* 0x7330-0x7360 RSRV */ |
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u64 OutVLAN; /* 0x7370 */ |
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u64 InUCastOctects; /* 0x7380 */ |
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u64 OutUCastOctects; /* 0x7390 */ |
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/* 0x73A0-0x73B0 RSRV */ |
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u64 InBCastOctects; /* 0x73C0 */ |
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u64 OutBCastOctects; /* 0x73D0 */ |
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u64 InOctects; /* 0x73E0 */ |
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u64 OutOctects; /* 0x73F0 */ |
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}; |
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struct bdx_priv { |
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void __iomem *pBdxRegs; |
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struct net_device *ndev; |
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struct napi_struct napi; |
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/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ |
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struct rxd_fifo rxd_fifo0; |
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struct rxf_fifo rxf_fifo0; |
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struct rxdb *rxdb; /* rx dbs to store skb pointers */ |
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int napi_stop; |
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/* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ |
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struct txd_fifo txd_fifo0; |
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struct txf_fifo txf_fifo0; |
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struct txdb txdb; |
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int tx_level; |
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#ifdef BDX_DELAY_WPTR |
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int tx_update_mark; |
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int tx_noupd; |
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#endif |
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spinlock_t tx_lock; /* NETIF_F_LLTX mode */ |
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/* rarely used */ |
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u8 port; |
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u32 msg_enable; |
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int stats_flag; |
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struct bdx_stats hw_stats; |
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struct pci_dev *pdev; |
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struct pci_nic *nic; |
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u8 txd_size; |
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u8 txf_size; |
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u8 rxd_size; |
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u8 rxf_size; |
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u32 rdintcm; |
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u32 tdintcm; |
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}; |
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/* RX FREE descriptor - 64bit*/ |
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struct rxf_desc { |
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u32 info; /* Buffer Count + Info - described below */ |
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u32 va_lo; /* VAdr[31:0] */ |
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u32 va_hi; /* VAdr[63:32] */ |
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u32 pa_lo; /* PAdr[31:0] */ |
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u32 pa_hi; /* PAdr[63:32] */ |
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u32 len; /* Buffer Length */ |
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}; |
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#define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0) |
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#define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8) |
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#define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15) |
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#define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16) |
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#define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21) |
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#define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27) |
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#define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) |
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#define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) |
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#define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) |
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#define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0) |
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#define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) |
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#define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) |
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struct rxd_desc { |
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u32 rxd_val1; |
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u16 len; |
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u16 rxd_vlan; |
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u32 va_lo; |
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u32 va_hi; |
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}; |
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/* PBL describes each virtual buffer to be */ |
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/* transmitted from the host.*/ |
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struct pbl { |
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u32 pa_lo; |
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u32 pa_hi; |
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u32 len; |
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}; |
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/* First word for TXD descriptor. It means: type = 3 for regular Tx packet, |
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* hw_csum = 7 for ip+udp+tcp hw checksums */ |
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#define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \ |
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((bc) | ((checksum)<<5) | ((vtag)<<8) | \ |
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((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20)) |
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struct txd_desc { |
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u32 txd_val1; |
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u16 mss; |
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u16 length; |
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u32 va_lo; |
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u32 va_hi; |
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struct pbl pbl[]; /* Fragments */ |
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} __packed; |
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/* Register region size */ |
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#define BDX_REGS_SIZE 0x1000 |
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/* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ |
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#define regTXD_CFG1_0 0x4000 |
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#define regRXF_CFG1_0 0x4010 |
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#define regRXD_CFG1_0 0x4020 |
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#define regTXF_CFG1_0 0x4030 |
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#define regTXD_CFG0_0 0x4040 |
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#define regRXF_CFG0_0 0x4050 |
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#define regRXD_CFG0_0 0x4060 |
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#define regTXF_CFG0_0 0x4070 |
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#define regTXD_WPTR_0 0x4080 |
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#define regRXF_WPTR_0 0x4090 |
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#define regRXD_WPTR_0 0x40A0 |
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#define regTXF_WPTR_0 0x40B0 |
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#define regTXD_RPTR_0 0x40C0 |
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#define regRXF_RPTR_0 0x40D0 |
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#define regRXD_RPTR_0 0x40E0 |
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#define regTXF_RPTR_0 0x40F0 |
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#define regTXF_RPTR_3 0x40FC |
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/* hardware versioning */ |
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#define FW_VER 0x5010 |
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#define SROM_VER 0x5020 |
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#define FPGA_VER 0x5030 |
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#define FPGA_SEED 0x5040 |
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/* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ |
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#define regISR regISR0 |
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#define regISR0 0x5100 |
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#define regIMR regIMR0 |
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#define regIMR0 0x5110 |
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#define regRDINTCM0 0x5120 |
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#define regRDINTCM2 0x5128 |
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#define regTDINTCM0 0x5130 |
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#define regISR_MSK0 0x5140 |
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#define regINIT_SEMAPHORE 0x5170 |
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#define regINIT_STATUS 0x5180 |
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#define regMAC_LNK_STAT 0x0200 |
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#define MAC_LINK_STAT 0x4 /* Link state */ |
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#define regGMAC_RXF_A 0x1240 |
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#define regUNC_MAC0_A 0x1250 |
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#define regUNC_MAC1_A 0x1260 |
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#define regUNC_MAC2_A 0x1270 |
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#define regVLAN_0 0x1800 |
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#define regMAX_FRAME_A 0x12C0 |
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#define regRX_MAC_MCST0 0x1A80 |
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#define regRX_MAC_MCST1 0x1A84 |
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#define MAC_MCST_NUM 15 |
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#define regRX_MCST_HASH0 0x1A00 |
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#define MAC_MCST_HASH_NUM 8 |
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#define regVPC 0x2300 |
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#define regVIC 0x2320 |
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#define regVGLB 0x2340 |
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#define regCLKPLL 0x5000 |
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/*for 10G only*/ |
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#define regREVISION 0x6000 |
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#define regSCRATCH 0x6004 |
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#define regCTRLST 0x6008 |
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#define regMAC_ADDR_0 0x600C |
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#define regMAC_ADDR_1 0x6010 |
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#define regFRM_LENGTH 0x6014 |
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#define regPAUSE_QUANT 0x6018 |
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#define regRX_FIFO_SECTION 0x601C |
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#define regTX_FIFO_SECTION 0x6020 |
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#define regRX_FULLNESS 0x6024 |
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#define regTX_FULLNESS 0x6028 |
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#define regHASHTABLE 0x602C |
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#define regMDIO_ST 0x6030 |
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#define regMDIO_CTL 0x6034 |
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#define regMDIO_DATA 0x6038 |
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#define regMDIO_ADDR 0x603C |
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#define regRST_PORT 0x7000 |
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#define regDIS_PORT 0x7010 |
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#define regRST_QU 0x7020 |
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#define regDIS_QU 0x7030 |
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#define regCTRLST_TX_ENA 0x0001 |
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#define regCTRLST_RX_ENA 0x0002 |
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#define regCTRLST_PRM_ENA 0x0010 |
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#define regCTRLST_PAD_ENA 0x0020 |
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#define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA) |
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#define regRX_FLT 0x1400 |
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/* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/ |
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#define TX_RX_CFG1_BASE 0xffffffff /*0-31 */ |
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#define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ |
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#define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */ |
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#define TX_RX_CFG0_SIZE 0x0003 /*1:0 */ |
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/* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ |
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#define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */ |
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/* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ |
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#define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */ |
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#define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped |
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* size is rounded to 16 */ |
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/* regISR 0x0100 */ |
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/* regIMR 0x0110 */ |
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#define IMR_INPROG 0x80000000 /*31 */ |
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#define IR_LNKCHG1 0x10000000 /*28 */ |
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#define IR_LNKCHG0 0x08000000 /*27 */ |
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#define IR_GPIO 0x04000000 /*26 */ |
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#define IR_RFRSH 0x02000000 /*25 */ |
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#define IR_RSVD 0x01000000 /*24 */ |
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#define IR_SWI 0x00800000 /*23 */ |
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#define IR_RX_FREE_3 0x00400000 /*22 */ |
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#define IR_RX_FREE_2 0x00200000 /*21 */ |
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#define IR_RX_FREE_1 0x00100000 /*20 */ |
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#define IR_RX_FREE_0 0x00080000 /*19 */ |
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#define IR_TX_FREE_3 0x00040000 /*18 */ |
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#define IR_TX_FREE_2 0x00020000 /*17 */ |
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#define IR_TX_FREE_1 0x00010000 /*16 */ |
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#define IR_TX_FREE_0 0x00008000 /*15 */ |
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#define IR_RX_DESC_3 0x00004000 /*14 */ |
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#define IR_RX_DESC_2 0x00002000 /*13 */ |
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#define IR_RX_DESC_1 0x00001000 /*12 */ |
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#define IR_RX_DESC_0 0x00000800 /*11 */ |
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#define IR_PSE 0x00000400 /*10 */ |
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#define IR_TMR3 0x00000200 /*9 */ |
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#define IR_TMR2 0x00000100 /*8 */ |
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#define IR_TMR1 0x00000080 /*7 */ |
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#define IR_TMR0 0x00000040 /*6 */ |
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#define IR_VNT 0x00000020 /*5 */ |
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#define IR_RxFL 0x00000010 /*4 */ |
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#define IR_SDPERR 0x00000008 /*3 */ |
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#define IR_TR 0x00000004 /*2 */ |
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#define IR_PCIE_LINK 0x00000002 /*1 */ |
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#define IR_PCIE_TOUT 0x00000001 /*0 */ |
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#define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \ |
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IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT) |
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#define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0) |
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#define IR_ALL 0xfdfffff7 |
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#define IR_LNKCHG0_ofst 27 |
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#define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ |
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#define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ |
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#define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ |
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#define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ |
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#define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ |
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#define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ |
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#define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ |
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#define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ |
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#define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ |
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#define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ |
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#define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */ |
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#define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ |
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#define CLKPLL_PLLLKD 0x0200 /*9 */ |
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#define CLKPLL_RSTEND 0x0100 /*8 */ |
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#define CLKPLL_SFTRST 0x0001 /*0 */ |
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#define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND) |
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/* |
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* PCI-E Device Control Register (Offset 0x88) |
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* Source: Luxor Data Sheet, 7.1.3.3.3 |
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*/ |
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#define PCI_DEV_CTRL_REG 0x88 |
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#define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5) |
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#define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12) |
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/* |
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* PCI-E Link Status Register (Offset 0x92) |
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* Source: Luxor Data Sheet, 7.1.3.3.7 |
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*/ |
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#define PCI_LINK_STATUS_REG 0x92 |
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#define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4) |
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/* Debugging Macros */ |
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#define DBG2(fmt, args...) \ |
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pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args) |
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#define BDX_ASSERT(x) BUG_ON(x) |
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#ifdef DEBUG |
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#define ENTER \ |
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do { \ |
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pr_err("%s:%-5d: ENTER\n", __func__, __LINE__); \ |
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} while (0) |
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#define RET(args...) \ |
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do { \ |
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pr_err("%s:%-5d: RETURN\n", __func__, __LINE__); \ |
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return args; \ |
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} while (0) |
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#define DBG(fmt, args...) \ |
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pr_err("%s:%-5d: " fmt, __func__, __LINE__, ## args) |
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#else |
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#define ENTER do { } while (0) |
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#define RET(args...) return args |
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#define DBG(fmt, args...) \ |
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do { \ |
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if (0) \ |
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pr_err(fmt, ##args); \ |
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} while (0) |
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#endif |
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#endif /* _BDX__H */
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