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682 lines
19 KiB
682 lines
19 KiB
/********************************************************************** |
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* Author: Cavium, Inc. |
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* |
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* Contact: [email protected] |
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* Please include "LiquidIO" in the subject. |
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* |
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* Copyright (c) 2003-2016 Cavium, Inc. |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more details. |
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***********************************************************************/ |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/vmalloc.h> |
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#include "liquidio_common.h" |
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#include "octeon_droq.h" |
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#include "octeon_iq.h" |
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#include "response_manager.h" |
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#include "octeon_device.h" |
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#include "cn23xx_vf_device.h" |
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#include "octeon_main.h" |
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#include "octeon_mailbox.h" |
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|
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u32 cn23xx_vf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us) |
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{ |
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/* This gives the SLI clock per microsec */ |
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u32 oqticks_per_us = (u32)oct->pfvf_hsword.coproc_tics_per_us; |
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|
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/* This gives the clock cycles per millisecond */ |
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oqticks_per_us *= 1000; |
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|
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/* This gives the oq ticks (1024 core clock cycles) per millisecond */ |
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oqticks_per_us /= 1024; |
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|
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/* time_intr is in microseconds. The next 2 steps gives the oq ticks |
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* corressponding to time_intr. |
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*/ |
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oqticks_per_us *= time_intr_in_us; |
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oqticks_per_us /= 1000; |
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return oqticks_per_us; |
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} |
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|
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static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues) |
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{ |
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u32 loop = BUSY_READING_REG_VF_LOOP_COUNT; |
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int ret_val = 0; |
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u32 q_no; |
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u64 d64; |
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for (q_no = 0; q_no < num_queues; q_no++) { |
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/* set RST bit to 1. This bit applies to both IQ and OQ */ |
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d64 = octeon_read_csr64(oct, |
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CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); |
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d64 |= CN23XX_PKT_INPUT_CTL_RST; |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), |
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d64); |
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} |
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|
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/* wait until the RST bit is clear or the RST and QUIET bits are set */ |
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for (q_no = 0; q_no < num_queues; q_no++) { |
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u64 reg_val = octeon_read_csr64(oct, |
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CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); |
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while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && |
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!(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && |
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loop) { |
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WRITE_ONCE(reg_val, octeon_read_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))); |
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loop--; |
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} |
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if (!loop) { |
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dev_err(&oct->pci_dev->dev, |
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"clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", |
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q_no); |
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return -1; |
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} |
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WRITE_ONCE(reg_val, READ_ONCE(reg_val) & |
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~CN23XX_PKT_INPUT_CTL_RST); |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), |
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READ_ONCE(reg_val)); |
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|
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WRITE_ONCE(reg_val, octeon_read_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))); |
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if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { |
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dev_err(&oct->pci_dev->dev, |
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"clearing the reset failed for qno: %u\n", |
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q_no); |
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ret_val = -1; |
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} |
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} |
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return ret_val; |
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} |
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static int cn23xx_vf_setup_global_input_regs(struct octeon_device *oct) |
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{ |
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struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; |
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struct octeon_instr_queue *iq; |
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u64 q_no, intr_threshold; |
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u64 d64; |
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if (cn23xx_vf_reset_io_queues(oct, oct->sriov_info.rings_per_vf)) |
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return -1; |
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for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { |
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void __iomem *inst_cnt_reg; |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_DOORBELL(q_no), |
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0xFFFFFFFF); |
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iq = oct->instr_queue[q_no]; |
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if (iq) |
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inst_cnt_reg = iq->inst_cnt_reg; |
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else |
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inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr + |
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CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no); |
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d64 = octeon_read_csr64(oct, |
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CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)); |
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d64 &= 0xEFFFFFFFFFFFFFFFL; |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), |
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d64); |
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/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for |
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* the Input Queues |
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*/ |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), |
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CN23XX_PKT_INPUT_CTL_MASK); |
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|
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/* set the wmark level to trigger PI_INT */ |
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intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) & |
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CN23XX_PKT_IN_DONE_WMARK_MASK; |
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writeq((readq(inst_cnt_reg) & |
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~(CN23XX_PKT_IN_DONE_WMARK_MASK << |
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CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) | |
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(intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS), |
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inst_cnt_reg); |
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} |
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return 0; |
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} |
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static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct) |
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{ |
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u32 reg_val; |
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u32 q_no; |
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for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { |
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no), |
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0xFFFFFFFF); |
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reg_val = |
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octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); |
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reg_val &= 0xEFFFFFFFFFFFFFFFL; |
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reg_val = |
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octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); |
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/* clear IPTR */ |
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reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR; |
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/* set DPTR */ |
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reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; |
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/* reset BMODE */ |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); |
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap |
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* for Output Queue ScatterList reset ROR_P, NSR_P |
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*/ |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); |
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#ifdef __LITTLE_ENDIAN_BITFIELD |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); |
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#else |
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); |
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#endif |
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap |
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* for Output Queue Data reset ROR, NSR |
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*/ |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); |
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); |
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/* set the ES bit */ |
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); |
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|
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/* write all the selected settings */ |
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), |
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reg_val); |
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} |
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} |
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static int cn23xx_setup_vf_device_regs(struct octeon_device *oct) |
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{ |
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if (cn23xx_vf_setup_global_input_regs(oct)) |
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return -1; |
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cn23xx_vf_setup_global_output_regs(oct); |
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return 0; |
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} |
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static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no) |
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{ |
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struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; |
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u64 pkt_in_done; |
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/* Write the start of the input queue's ring and its size */ |
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no), |
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iq->base_addr_dma); |
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octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count); |
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|
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/* Remember the doorbell & instruction count register addr |
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* for this queue |
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*/ |
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iq->doorbell_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no); |
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iq->inst_cnt_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no); |
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dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", |
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iq_no, iq->doorbell_reg, iq->inst_cnt_reg); |
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/* Store the current instruction counter (used in flush_iq |
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* calculation) |
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*/ |
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pkt_in_done = readq(iq->inst_cnt_reg); |
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if (oct->msix_on) { |
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/* Set CINT_ENB to enable IQ interrupt */ |
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writeq((pkt_in_done | CN23XX_INTR_CINT_ENB), |
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iq->inst_cnt_reg); |
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} |
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iq->reset_instr_cnt = 0; |
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} |
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static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no) |
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{ |
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struct octeon_droq *droq = oct->droq[oq_no]; |
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octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no), |
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droq->desc_ring_dma); |
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count); |
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no), |
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droq->buffer_size); |
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/* Get the mapped address of the pkt_sent and pkts_credit regs */ |
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droq->pkts_sent_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no); |
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droq->pkts_credit_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no); |
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} |
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static void cn23xx_vf_mbox_thread(struct work_struct *work) |
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{ |
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struct cavium_wk *wk = (struct cavium_wk *)work; |
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struct octeon_mbox *mbox = (struct octeon_mbox *)wk->ctxptr; |
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octeon_mbox_process_message(mbox); |
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} |
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static int cn23xx_free_vf_mbox(struct octeon_device *oct) |
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{ |
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cancel_delayed_work_sync(&oct->mbox[0]->mbox_poll_wk.work); |
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vfree(oct->mbox[0]); |
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return 0; |
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} |
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static int cn23xx_setup_vf_mbox(struct octeon_device *oct) |
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{ |
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struct octeon_mbox *mbox = NULL; |
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mbox = vmalloc(sizeof(*mbox)); |
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if (!mbox) |
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return 1; |
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memset(mbox, 0, sizeof(struct octeon_mbox)); |
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spin_lock_init(&mbox->lock); |
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mbox->oct_dev = oct; |
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mbox->q_no = 0; |
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mbox->state = OCTEON_MBOX_STATE_IDLE; |
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/* VF mbox interrupt reg */ |
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mbox->mbox_int_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_PKT_MBOX_INT(0); |
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/* VF reads from SIG0 reg */ |
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mbox->mbox_read_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0); |
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/* VF writes into SIG1 reg */ |
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mbox->mbox_write_reg = |
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(u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1); |
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INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work, |
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cn23xx_vf_mbox_thread); |
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mbox->mbox_poll_wk.ctxptr = mbox; |
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oct->mbox[0] = mbox; |
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writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); |
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return 0; |
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} |
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static int cn23xx_enable_vf_io_queues(struct octeon_device *oct) |
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{ |
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u32 q_no; |
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for (q_no = 0; q_no < oct->num_iqs; q_no++) { |
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u64 reg_val; |
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/* set the corresponding IQ IS_64B bit */ |
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if (oct->io_qmask.iq64B & BIT_ULL(q_no)) { |
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reg_val = octeon_read_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); |
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reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B; |
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octeon_write_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); |
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} |
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|
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/* set the corresponding IQ ENB bit */ |
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if (oct->io_qmask.iq & BIT_ULL(q_no)) { |
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reg_val = octeon_read_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); |
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reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB; |
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octeon_write_csr64( |
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); |
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} |
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} |
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for (q_no = 0; q_no < oct->num_oqs; q_no++) { |
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u32 reg_val; |
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|
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/* set the corresponding OQ ENB bit */ |
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if (oct->io_qmask.oq & BIT_ULL(q_no)) { |
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reg_val = octeon_read_csr( |
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oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); |
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reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB; |
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octeon_write_csr( |
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oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); |
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} |
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} |
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return 0; |
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} |
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static void cn23xx_disable_vf_io_queues(struct octeon_device *oct) |
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{ |
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u32 num_queues = oct->num_iqs; |
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|
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/* per HRM, rings can only be disabled via reset operation, |
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* NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB] |
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*/ |
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if (num_queues < oct->num_oqs) |
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num_queues = oct->num_oqs; |
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cn23xx_vf_reset_io_queues(oct, num_queues); |
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} |
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void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct) |
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{ |
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struct octeon_mbox_cmd mbox_cmd; |
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mbox_cmd.msg.u64 = 0; |
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mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST; |
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mbox_cmd.msg.s.resp_needed = 0; |
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mbox_cmd.msg.s.cmd = OCTEON_VF_FLR_REQUEST; |
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mbox_cmd.msg.s.len = 1; |
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mbox_cmd.q_no = 0; |
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mbox_cmd.recv_len = 0; |
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mbox_cmd.recv_status = 0; |
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mbox_cmd.fn = NULL; |
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mbox_cmd.fn_arg = NULL; |
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|
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octeon_mbox_write(oct, &mbox_cmd); |
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} |
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static void octeon_pfvf_hs_callback(struct octeon_device *oct, |
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struct octeon_mbox_cmd *cmd, |
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void *arg) |
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{ |
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u32 major = 0; |
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|
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memcpy((uint8_t *)&oct->pfvf_hsword, cmd->msg.s.params, |
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CN23XX_MAILBOX_MSGPARAM_SIZE); |
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if (cmd->recv_len > 1) { |
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major = ((struct lio_version *)(cmd->data))->major; |
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major = major << 16; |
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} |
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|
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atomic_set((atomic_t *)arg, major | 1); |
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} |
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|
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int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct) |
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{ |
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struct octeon_mbox_cmd mbox_cmd; |
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u32 q_no, count = 0; |
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atomic_t status; |
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u32 pfmajor; |
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u32 vfmajor; |
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u32 ret; |
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|
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/* Sending VF_ACTIVE indication to the PF driver */ |
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dev_dbg(&oct->pci_dev->dev, "requesting info from pf\n"); |
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|
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mbox_cmd.msg.u64 = 0; |
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mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST; |
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mbox_cmd.msg.s.resp_needed = 1; |
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mbox_cmd.msg.s.cmd = OCTEON_VF_ACTIVE; |
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mbox_cmd.msg.s.len = 2; |
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mbox_cmd.data[0] = 0; |
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((struct lio_version *)&mbox_cmd.data[0])->major = |
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LIQUIDIO_BASE_MAJOR_VERSION; |
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((struct lio_version *)&mbox_cmd.data[0])->minor = |
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LIQUIDIO_BASE_MINOR_VERSION; |
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((struct lio_version *)&mbox_cmd.data[0])->micro = |
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LIQUIDIO_BASE_MICRO_VERSION; |
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mbox_cmd.q_no = 0; |
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mbox_cmd.recv_len = 0; |
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mbox_cmd.recv_status = 0; |
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mbox_cmd.fn = (octeon_mbox_callback_t)octeon_pfvf_hs_callback; |
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mbox_cmd.fn_arg = &status; |
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|
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octeon_mbox_write(oct, &mbox_cmd); |
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|
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atomic_set(&status, 0); |
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|
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do { |
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schedule_timeout_uninterruptible(1); |
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} while ((!atomic_read(&status)) && (count++ < 100000)); |
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|
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ret = atomic_read(&status); |
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if (!ret) { |
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dev_err(&oct->pci_dev->dev, "octeon_pfvf_handshake timeout\n"); |
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return 1; |
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} |
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|
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for (q_no = 0 ; q_no < oct->num_iqs ; q_no++) |
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oct->instr_queue[q_no]->txpciq.s.pkind = oct->pfvf_hsword.pkind; |
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|
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vfmajor = LIQUIDIO_BASE_MAJOR_VERSION; |
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pfmajor = ret >> 16; |
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if (pfmajor != vfmajor) { |
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dev_err(&oct->pci_dev->dev, |
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"VF Liquidio driver (major version %d) is not compatible with Liquidio PF driver (major version %d)\n", |
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vfmajor, pfmajor); |
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return 1; |
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} |
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|
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dev_dbg(&oct->pci_dev->dev, |
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"VF Liquidio driver (major version %d), Liquidio PF driver (major version %d)\n", |
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vfmajor, pfmajor); |
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|
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dev_dbg(&oct->pci_dev->dev, "got data from pf pkind is %d\n", |
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oct->pfvf_hsword.pkind); |
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|
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return 0; |
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} |
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|
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static void cn23xx_handle_vf_mbox_intr(struct octeon_ioq_vector *ioq_vector) |
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{ |
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struct octeon_device *oct = ioq_vector->oct_dev; |
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u64 mbox_int_val; |
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|
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if (!ioq_vector->droq_index) { |
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/* read and clear by writing 1 */ |
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mbox_int_val = readq(oct->mbox[0]->mbox_int_reg); |
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writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg); |
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if (octeon_mbox_read(oct->mbox[0])) |
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schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work, |
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msecs_to_jiffies(0)); |
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} |
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} |
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|
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static u64 cn23xx_vf_msix_interrupt_handler(void *dev) |
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{ |
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struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev; |
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struct octeon_device *oct = ioq_vector->oct_dev; |
|
struct octeon_droq *droq = oct->droq[ioq_vector->droq_index]; |
|
u64 pkts_sent; |
|
u64 ret = 0; |
|
|
|
dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct); |
|
pkts_sent = readq(droq->pkts_sent_reg); |
|
|
|
/* If our device has interrupted, then proceed. Also check |
|
* for all f's if interrupt was triggered on an error |
|
* and the PCI read fails. |
|
*/ |
|
if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL)) |
|
return ret; |
|
|
|
/* Write count reg in sli_pkt_cnts to clear these int. */ |
|
if ((pkts_sent & CN23XX_INTR_PO_INT) || |
|
(pkts_sent & CN23XX_INTR_PI_INT)) { |
|
if (pkts_sent & CN23XX_INTR_PO_INT) |
|
ret |= MSIX_PO_INT; |
|
} |
|
|
|
if (pkts_sent & CN23XX_INTR_PI_INT) |
|
/* We will clear the count when we update the read_index. */ |
|
ret |= MSIX_PI_INT; |
|
|
|
if (pkts_sent & CN23XX_INTR_MBOX_INT) { |
|
cn23xx_handle_vf_mbox_intr(ioq_vector); |
|
ret |= MSIX_MBOX_INT; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static u32 cn23xx_update_read_index(struct octeon_instr_queue *iq) |
|
{ |
|
u32 pkt_in_done = readl(iq->inst_cnt_reg); |
|
u32 last_done; |
|
u32 new_idx; |
|
|
|
last_done = pkt_in_done - iq->pkt_in_done; |
|
iq->pkt_in_done = pkt_in_done; |
|
|
|
/* Modulo of the new index with the IQ size will give us |
|
* the new index. The iq->reset_instr_cnt is always zero for |
|
* cn23xx, so no extra adjustments are needed. |
|
*/ |
|
new_idx = (iq->octeon_read_index + |
|
(u32)(last_done & CN23XX_PKT_IN_DONE_CNT_MASK)) % |
|
iq->max_count; |
|
|
|
return new_idx; |
|
} |
|
|
|
static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) |
|
{ |
|
struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; |
|
u32 q_no, time_threshold; |
|
|
|
if (intr_flag & OCTEON_OUTPUT_INTR) { |
|
for (q_no = 0; q_no < oct->num_oqs; q_no++) { |
|
/* Set up interrupt packet and time thresholds |
|
* for all the OQs |
|
*/ |
|
time_threshold = cn23xx_vf_get_oq_ticks( |
|
oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); |
|
|
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), |
|
(CFG_GET_OQ_INTR_PKT(cn23xx->conf) | |
|
((u64)time_threshold << 32))); |
|
} |
|
} |
|
|
|
if (intr_flag & OCTEON_INPUT_INTR) { |
|
for (q_no = 0; q_no < oct->num_oqs; q_no++) { |
|
/* Set CINT_ENB to enable IQ interrupt */ |
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), |
|
((octeon_read_csr64( |
|
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & |
|
~CN23XX_PKT_IN_DONE_CNT_MASK) | |
|
CN23XX_INTR_CINT_ENB)); |
|
} |
|
} |
|
|
|
/* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */ |
|
if (intr_flag & OCTEON_MBOX_INTR) { |
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), |
|
(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) | |
|
CN23XX_INTR_MBOX_ENB)); |
|
} |
|
} |
|
|
|
static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) |
|
{ |
|
u32 q_no; |
|
|
|
if (intr_flag & OCTEON_OUTPUT_INTR) { |
|
for (q_no = 0; q_no < oct->num_oqs; q_no++) { |
|
/* Write all 1's in INT_LEVEL reg to disable PO_INT */ |
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), |
|
0x3fffffffffffff); |
|
} |
|
} |
|
if (intr_flag & OCTEON_INPUT_INTR) { |
|
for (q_no = 0; q_no < oct->num_oqs; q_no++) { |
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), |
|
(octeon_read_csr64( |
|
oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & |
|
~(CN23XX_INTR_CINT_ENB | |
|
CN23XX_PKT_IN_DONE_CNT_MASK))); |
|
} |
|
} |
|
|
|
if (intr_flag & OCTEON_MBOX_INTR) { |
|
octeon_write_csr64( |
|
oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), |
|
(octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) & |
|
~CN23XX_INTR_MBOX_ENB)); |
|
} |
|
} |
|
|
|
int cn23xx_setup_octeon_vf_device(struct octeon_device *oct) |
|
{ |
|
struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; |
|
u32 rings_per_vf; |
|
u64 reg_val; |
|
|
|
if (octeon_map_pci_barx(oct, 0, 0)) |
|
return 1; |
|
|
|
/* INPUT_CONTROL[RPVF] gives the VF IOq count */ |
|
reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0)); |
|
|
|
oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) & |
|
CN23XX_PKT_INPUT_CTL_PF_NUM_MASK; |
|
oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) & |
|
CN23XX_PKT_INPUT_CTL_VF_NUM_MASK; |
|
|
|
reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS; |
|
|
|
rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK; |
|
|
|
cn23xx->conf = oct_get_config_info(oct, LIO_23XX); |
|
if (!cn23xx->conf) { |
|
dev_err(&oct->pci_dev->dev, "%s No Config found for CN23XX\n", |
|
__func__); |
|
octeon_unmap_pci_barx(oct, 0); |
|
return 1; |
|
} |
|
|
|
if (oct->sriov_info.rings_per_vf > rings_per_vf) { |
|
dev_warn(&oct->pci_dev->dev, |
|
"num_queues:%d greater than PF configured rings_per_vf:%d. Reducing to %d.\n", |
|
oct->sriov_info.rings_per_vf, rings_per_vf, |
|
rings_per_vf); |
|
oct->sriov_info.rings_per_vf = rings_per_vf; |
|
} else { |
|
if (rings_per_vf > num_present_cpus()) { |
|
dev_warn(&oct->pci_dev->dev, |
|
"PF configured rings_per_vf:%d greater than num_cpu:%d. Using rings_per_vf:%d equal to num cpus\n", |
|
rings_per_vf, |
|
num_present_cpus(), |
|
num_present_cpus()); |
|
oct->sriov_info.rings_per_vf = |
|
num_present_cpus(); |
|
} else { |
|
oct->sriov_info.rings_per_vf = rings_per_vf; |
|
} |
|
} |
|
|
|
oct->fn_list.setup_iq_regs = cn23xx_setup_vf_iq_regs; |
|
oct->fn_list.setup_oq_regs = cn23xx_setup_vf_oq_regs; |
|
oct->fn_list.setup_mbox = cn23xx_setup_vf_mbox; |
|
oct->fn_list.free_mbox = cn23xx_free_vf_mbox; |
|
|
|
oct->fn_list.msix_interrupt_handler = cn23xx_vf_msix_interrupt_handler; |
|
|
|
oct->fn_list.setup_device_regs = cn23xx_setup_vf_device_regs; |
|
oct->fn_list.update_iq_read_idx = cn23xx_update_read_index; |
|
|
|
oct->fn_list.enable_interrupt = cn23xx_enable_vf_interrupt; |
|
oct->fn_list.disable_interrupt = cn23xx_disable_vf_interrupt; |
|
|
|
oct->fn_list.enable_io_queues = cn23xx_enable_vf_io_queues; |
|
oct->fn_list.disable_io_queues = cn23xx_disable_vf_io_queues; |
|
|
|
return 0; |
|
}
|
|
|