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508 lines
15 KiB
508 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* atl2.h -- atl2 driver definitions |
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* |
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* Copyright(c) 2007 Atheros Corporation. All rights reserved. |
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* Copyright(c) 2006 xiong huang <[email protected]> |
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* Copyright(c) 2007 Chris Snook <[email protected]> |
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* |
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* Derived from Intel e1000 driver |
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
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*/ |
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#ifndef _ATL2_H_ |
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#define _ATL2_H_ |
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#include <linux/atomic.h> |
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#include <linux/netdevice.h> |
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#ifndef _ATL2_HW_H_ |
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#define _ATL2_HW_H_ |
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#ifndef _ATL2_OSDEP_H_ |
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#define _ATL2_OSDEP_H_ |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/if_ether.h> |
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#include "atlx.h" |
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#ifdef ETHTOOL_OPS_COMPAT |
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int ethtool_ioctl(struct ifreq *ifr); |
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#endif |
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#define PCI_COMMAND_REGISTER PCI_COMMAND |
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#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE |
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#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \ |
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((a)->hw_addr + (reg)))) |
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#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr)) |
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#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) |
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#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \ |
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((a)->hw_addr + (reg)))) |
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#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) |
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#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \ |
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((a)->hw_addr + (reg)))) |
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#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) |
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#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ |
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(iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) |
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#define ATL2_READ_REG_ARRAY(a, reg, offset) \ |
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(ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) |
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#endif /* _ATL2_OSDEP_H_ */ |
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struct atl2_adapter; |
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struct atl2_hw; |
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/* function prototype */ |
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static s32 atl2_reset_hw(struct atl2_hw *hw); |
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static s32 atl2_read_mac_addr(struct atl2_hw *hw); |
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static s32 atl2_init_hw(struct atl2_hw *hw); |
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static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, |
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u16 *duplex); |
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static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr); |
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static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value); |
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static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data); |
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static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data); |
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static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); |
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static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); |
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static void atl2_set_mac_addr(struct atl2_hw *hw); |
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static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue); |
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static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value); |
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static s32 atl2_phy_init(struct atl2_hw *hw); |
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static int atl2_check_eeprom_exist(struct atl2_hw *hw); |
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static void atl2_force_ps(struct atl2_hw *hw); |
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/* register definition */ |
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/* Block IDLE Status Register */ |
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#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */ |
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#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */ |
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#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */ |
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#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */ |
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/* MDIO Control Register */ |
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#define MDIO_WAIT_TIMES 10 |
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/* MAC Control Register */ |
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#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */ |
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#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */ |
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#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28 |
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#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */ |
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/* Internal SRAM Partition Register */ |
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#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM |
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* default: 2byte*1024 */ |
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#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM |
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* default: 2byte*1024 */ |
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/* Descriptor Control register */ |
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#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit |
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* Data Mem low 32-bit(dword align) */ |
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#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by |
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* double word , max 256KB) */ |
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#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit |
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* Status Memory low 32-bit(dword word |
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* align) */ |
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#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047 |
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* bytes. */ |
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#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit |
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* Status Memory low 32-bit(unit 8 |
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* bytes) */ |
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#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer |
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* number (unit 1536bytes, max |
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* 1536*2047) */ |
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/* DMAR Control Register */ |
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#define REG_DMAR 0x1580 |
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#define DMAR_EN 0x1 /* 1: Enable DMAR */ |
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/* TX Cur-Through (early tx threshold) Control Register */ |
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#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet |
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* threshold(unit word) */ |
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/* DMAW Control Register */ |
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#define REG_DMAW 0x15A0 |
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#define DMAW_EN 0x1 |
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/* Flow control register */ |
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#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow |
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* threshold configuration register */ |
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#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow |
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* threshold configuration register */ |
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/* Mailbox Register */ |
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#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */ |
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#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */ |
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/* Interrupt Status Register */ |
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#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */ |
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#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set |
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* when SW_MAN_INT_EN is set in Table 51 |
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* Selene Master Control Register |
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* (Offset 0x1400). */ |
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#define ISR_RXF_OV 4 /* RXF overflow interrupt */ |
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#define ISR_TXF_UR 8 /* TXF underrun interrupt */ |
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#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full |
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* interrupt */ |
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#define ISR_RXS_OV 0x20 /* Internal receive status buffer full |
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* interrupt */ |
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#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */ |
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#define ISR_HOST_TXD_UR 0x80 |
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#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */ |
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#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should |
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* do Reset */ |
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#define ISR_DMAW_TO_RST 0x400 |
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#define ISR_PHY 0x800 /* phy interrupt */ |
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#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written |
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* to host */ |
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#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written |
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* to host. */ |
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#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one |
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* packet */ |
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#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\ |
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ISR_TS_UPDATE | ISR_TX_EARLY) |
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#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\ |
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ISR_RS_UPDATE) |
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#define IMR_NORMAL_MASK (\ |
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/*ISR_LINK_CHG |*/\ |
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ISR_MANUAL |\ |
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ISR_DMAR_TO_RST |\ |
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ISR_DMAW_TO_RST |\ |
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ISR_PHY |\ |
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ISR_PHY_LINKDOWN |\ |
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ISR_TS_UPDATE |\ |
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ISR_RS_UPDATE) |
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/* Receive MAC Statistics Registers */ |
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#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */ |
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#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX |
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* FIFO overflow */ |
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#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX |
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* Status Buffer Overflow */ |
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#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to |
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* address filtering */ |
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/* MII definitions */ |
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/* PHY Common Register */ |
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#define MII_SMARTSPEED 0x14 |
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#define MII_DBG_ADDR 0x1D |
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#define MII_DBG_DATA 0x1E |
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/* PCI Command Register Bit Definitions */ |
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#define PCI_REG_COMMAND 0x04 |
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#define CMD_IO_SPACE 0x0001 |
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#define CMD_MEMORY_SPACE 0x0002 |
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#define CMD_BUS_MASTER 0x0004 |
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#define MEDIA_TYPE_100M_FULL 1 |
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#define MEDIA_TYPE_100M_HALF 2 |
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#define MEDIA_TYPE_10M_FULL 3 |
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#define MEDIA_TYPE_10M_HALF 4 |
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#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */ |
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/* The size (in bytes) of a ethernet packet */ |
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#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */ |
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#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */ |
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#define MAX_JUMBO_FRAME_SIZE 0x2000 |
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struct tx_pkt_header { |
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unsigned pkt_size:11; |
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unsigned:4; /* reserved */ |
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unsigned ins_vlan:1; /* txmac should insert vlan */ |
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unsigned short vlan; /* vlan tag */ |
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}; |
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/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
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#define TX_PKT_HEADER_SIZE_MASK 0x7FF |
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#define TX_PKT_HEADER_SIZE_SHIFT 0 |
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#define TX_PKT_HEADER_INS_VLAN_MASK 0x1 |
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#define TX_PKT_HEADER_INS_VLAN_SHIFT 15 |
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#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF |
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#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16 |
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struct tx_pkt_status { |
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unsigned pkt_size:11; |
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unsigned:5; /* reserved */ |
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unsigned ok:1; /* current packet transmitted without error */ |
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unsigned bcast:1; /* broadcast packet */ |
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unsigned mcast:1; /* multicast packet */ |
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unsigned pause:1; /* transmiited a pause frame */ |
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unsigned ctrl:1; |
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unsigned defer:1; /* current packet is xmitted with defer */ |
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unsigned exc_defer:1; |
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unsigned single_col:1; |
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unsigned multi_col:1; |
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unsigned late_col:1; |
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unsigned abort_col:1; |
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unsigned underrun:1; /* current packet is aborted |
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* due to txram underrun */ |
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unsigned:3; /* reserved */ |
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unsigned update:1; /* always 1'b1 in tx_status_buf */ |
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}; |
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/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
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#define TX_PKT_STATUS_SIZE_MASK 0x7FF |
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#define TX_PKT_STATUS_SIZE_SHIFT 0 |
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#define TX_PKT_STATUS_OK_MASK 0x1 |
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#define TX_PKT_STATUS_OK_SHIFT 16 |
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#define TX_PKT_STATUS_BCAST_MASK 0x1 |
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#define TX_PKT_STATUS_BCAST_SHIFT 17 |
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#define TX_PKT_STATUS_MCAST_MASK 0x1 |
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#define TX_PKT_STATUS_MCAST_SHIFT 18 |
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#define TX_PKT_STATUS_PAUSE_MASK 0x1 |
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#define TX_PKT_STATUS_PAUSE_SHIFT 19 |
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#define TX_PKT_STATUS_CTRL_MASK 0x1 |
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#define TX_PKT_STATUS_CTRL_SHIFT 20 |
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#define TX_PKT_STATUS_DEFER_MASK 0x1 |
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#define TX_PKT_STATUS_DEFER_SHIFT 21 |
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#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1 |
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#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22 |
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#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1 |
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#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23 |
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#define TX_PKT_STATUS_MULTI_COL_MASK 0x1 |
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#define TX_PKT_STATUS_MULTI_COL_SHIFT 24 |
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#define TX_PKT_STATUS_LATE_COL_MASK 0x1 |
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#define TX_PKT_STATUS_LATE_COL_SHIFT 25 |
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#define TX_PKT_STATUS_ABORT_COL_MASK 0x1 |
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#define TX_PKT_STATUS_ABORT_COL_SHIFT 26 |
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#define TX_PKT_STATUS_UNDERRUN_MASK 0x1 |
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#define TX_PKT_STATUS_UNDERRUN_SHIFT 27 |
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#define TX_PKT_STATUS_UPDATE_MASK 0x1 |
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#define TX_PKT_STATUS_UPDATE_SHIFT 31 |
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struct rx_pkt_status { |
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unsigned pkt_size:11; /* packet size, max 2047 bytes */ |
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unsigned:5; /* reserved */ |
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unsigned ok:1; /* current packet received ok without error */ |
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unsigned bcast:1; /* current packet is broadcast */ |
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unsigned mcast:1; /* current packet is multicast */ |
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unsigned pause:1; |
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unsigned ctrl:1; |
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unsigned crc:1; /* received a packet with crc error */ |
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unsigned code:1; /* received a packet with code error */ |
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unsigned runt:1; /* received a packet less than 64 bytes |
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* with good crc */ |
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unsigned frag:1; /* received a packet less than 64 bytes |
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* with bad crc */ |
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unsigned trunc:1; /* current frame truncated due to rxram full */ |
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unsigned align:1; /* this packet is alignment error */ |
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unsigned vlan:1; /* this packet has vlan */ |
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unsigned:3; /* reserved */ |
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unsigned update:1; |
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unsigned short vtag; /* vlan tag */ |
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unsigned:16; |
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}; |
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/* FIXME: replace above bitfields with MASK/SHIFT defines below */ |
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#define RX_PKT_STATUS_SIZE_MASK 0x7FF |
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#define RX_PKT_STATUS_SIZE_SHIFT 0 |
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#define RX_PKT_STATUS_OK_MASK 0x1 |
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#define RX_PKT_STATUS_OK_SHIFT 16 |
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#define RX_PKT_STATUS_BCAST_MASK 0x1 |
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#define RX_PKT_STATUS_BCAST_SHIFT 17 |
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#define RX_PKT_STATUS_MCAST_MASK 0x1 |
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#define RX_PKT_STATUS_MCAST_SHIFT 18 |
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#define RX_PKT_STATUS_PAUSE_MASK 0x1 |
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#define RX_PKT_STATUS_PAUSE_SHIFT 19 |
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#define RX_PKT_STATUS_CTRL_MASK 0x1 |
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#define RX_PKT_STATUS_CTRL_SHIFT 20 |
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#define RX_PKT_STATUS_CRC_MASK 0x1 |
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#define RX_PKT_STATUS_CRC_SHIFT 21 |
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#define RX_PKT_STATUS_CODE_MASK 0x1 |
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#define RX_PKT_STATUS_CODE_SHIFT 22 |
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#define RX_PKT_STATUS_RUNT_MASK 0x1 |
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#define RX_PKT_STATUS_RUNT_SHIFT 23 |
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#define RX_PKT_STATUS_FRAG_MASK 0x1 |
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#define RX_PKT_STATUS_FRAG_SHIFT 24 |
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#define RX_PKT_STATUS_TRUNK_MASK 0x1 |
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#define RX_PKT_STATUS_TRUNK_SHIFT 25 |
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#define RX_PKT_STATUS_ALIGN_MASK 0x1 |
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#define RX_PKT_STATUS_ALIGN_SHIFT 26 |
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#define RX_PKT_STATUS_VLAN_MASK 0x1 |
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#define RX_PKT_STATUS_VLAN_SHIFT 27 |
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#define RX_PKT_STATUS_UPDATE_MASK 0x1 |
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#define RX_PKT_STATUS_UPDATE_SHIFT 31 |
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#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF |
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#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32 |
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struct rx_desc { |
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struct rx_pkt_status status; |
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unsigned char packet[1536-sizeof(struct rx_pkt_status)]; |
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}; |
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enum atl2_speed_duplex { |
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atl2_10_half = 0, |
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atl2_10_full = 1, |
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atl2_100_half = 2, |
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atl2_100_full = 3 |
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}; |
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struct atl2_spi_flash_dev { |
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const char *manu_name; /* manufacturer id */ |
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/* op-code */ |
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u8 cmdWRSR; |
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u8 cmdREAD; |
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u8 cmdPROGRAM; |
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u8 cmdWREN; |
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u8 cmdWRDI; |
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u8 cmdRDSR; |
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u8 cmdRDID; |
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u8 cmdSECTOR_ERASE; |
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u8 cmdCHIP_ERASE; |
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}; |
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/* Structure containing variables used by the shared code (atl2_hw.c) */ |
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struct atl2_hw { |
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u8 __iomem *hw_addr; |
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void *back; |
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u8 preamble_len; |
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u8 max_retry; /* Retransmission maximum, afterwards the |
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* packet will be discarded. */ |
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u8 jam_ipg; /* IPG to start JAM for collision based flow |
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* control in half-duplex mode. In unit of |
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* 8-bit time. */ |
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u8 ipgt; /* Desired back to back inter-packet gap. The |
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* default is 96-bit time. */ |
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u8 min_ifg; /* Minimum number of IFG to enforce in between |
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* RX frames. Frame gap below such IFP is |
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* dropped. */ |
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u8 ipgr1; /* 64bit Carrier-Sense window */ |
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u8 ipgr2; /* 96-bit IPG window */ |
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u8 retry_buf; /* When half-duplex mode, should hold some |
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* bytes for mac retry . (8*4bytes unit) */ |
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u16 fc_rxd_hi; |
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u16 fc_rxd_lo; |
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u16 lcol; /* Collision Window */ |
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u16 max_frame_size; |
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u16 MediaType; |
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u16 autoneg_advertised; |
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u16 pci_cmd_word; |
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u16 mii_autoneg_adv_reg; |
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u32 mem_rang; |
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u32 txcw; |
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u32 mc_filter_type; |
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u32 num_mc_addrs; |
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u32 collision_delta; |
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u32 tx_packet_delta; |
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u16 phy_spd_default; |
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u16 device_id; |
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u16 vendor_id; |
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u16 subsystem_id; |
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u16 subsystem_vendor_id; |
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u8 revision_id; |
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/* spi flash */ |
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u8 flash_vendor; |
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u8 dma_fairness; |
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u8 mac_addr[ETH_ALEN]; |
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u8 perm_mac_addr[ETH_ALEN]; |
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/* FIXME */ |
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/* bool phy_preamble_sup; */ |
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bool phy_configured; |
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}; |
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#endif /* _ATL2_HW_H_ */ |
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struct atl2_ring_header { |
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/* pointer to the descriptor ring memory */ |
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void *desc; |
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/* physical address of the descriptor ring */ |
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dma_addr_t dma; |
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/* length of descriptor ring in bytes */ |
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unsigned int size; |
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}; |
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/* board specific private data structure */ |
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struct atl2_adapter { |
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/* OS defined structs */ |
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struct net_device *netdev; |
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struct pci_dev *pdev; |
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u32 wol; |
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u16 link_speed; |
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u16 link_duplex; |
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spinlock_t stats_lock; |
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struct work_struct reset_task; |
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struct work_struct link_chg_task; |
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struct timer_list watchdog_timer; |
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struct timer_list phy_config_timer; |
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unsigned long cfg_phy; |
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bool mac_disabled; |
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/* All Descriptor memory */ |
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dma_addr_t ring_dma; |
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void *ring_vir_addr; |
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int ring_size; |
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struct tx_pkt_header *txd_ring; |
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dma_addr_t txd_dma; |
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struct tx_pkt_status *txs_ring; |
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dma_addr_t txs_dma; |
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struct rx_desc *rxd_ring; |
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dma_addr_t rxd_dma; |
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u32 txd_ring_size; /* bytes per unit */ |
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u32 txs_ring_size; /* dwords per unit */ |
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u32 rxd_ring_size; /* 1536 bytes per unit */ |
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/* read /write ptr: */ |
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/* host */ |
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u32 txd_write_ptr; |
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u32 txs_next_clear; |
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u32 rxd_read_ptr; |
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/* nic */ |
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atomic_t txd_read_ptr; |
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atomic_t txs_write_ptr; |
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u32 rxd_write_ptr; |
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/* Interrupt Moderator timer ( 2us resolution) */ |
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u16 imt; |
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/* Interrupt Clear timer (2us resolution) */ |
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u16 ict; |
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unsigned long flags; |
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/* structs defined in atl2_hw.h */ |
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u32 bd_number; /* board number */ |
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bool pci_using_64; |
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bool have_msi; |
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struct atl2_hw hw; |
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u32 usr_cmd; |
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/* FIXME */ |
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/* u32 regs_buff[ATL2_REGS_LEN]; */ |
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u32 pci_state[16]; |
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u32 *config_space; |
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}; |
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enum atl2_state_t { |
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__ATL2_TESTING, |
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__ATL2_RESETTING, |
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__ATL2_DOWN |
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}; |
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#endif /* _ATL2_H_ */
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