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173 lines
5.0 KiB
173 lines
5.0 KiB
/* |
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* Amiga Linux/68k A2065 Ethernet Driver |
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* |
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* (C) Copyright 1995 by Geert Uytterhoeven <[email protected]> |
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* |
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* --------------------------------------------------------------------------- |
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* |
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* This program is based on |
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* |
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* ariadne.?: Amiga Linux/68k Ariadne Ethernet Driver |
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* (C) Copyright 1995 by Geert Uytterhoeven, |
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* Peter De Schrijver |
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* |
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* lance.c: An AMD LANCE ethernet driver for linux. |
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* Written 1993-94 by Donald Becker. |
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* |
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* Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller |
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* Advanced Micro Devices |
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* Publication #16907, Rev. B, Amendment/0, May 1994 |
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* |
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* --------------------------------------------------------------------------- |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of the Linux |
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* distribution for more details. |
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* |
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* --------------------------------------------------------------------------- |
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* |
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* The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains: |
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* |
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* - an Am7990 Local Area Network Controller for Ethernet (LANCE) with |
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* both 10BASE-2 (thin coax) and AUI (DB-15) connectors |
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*/ |
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/* |
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* Am7990 Local Area Network Controller for Ethernet (LANCE) |
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*/ |
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struct lance_regs { |
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unsigned short rdp; /* Register Data Port */ |
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unsigned short rap; /* Register Address Port */ |
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}; |
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/* |
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* Am7990 Control and Status Registers |
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*/ |
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#define LE_CSR0 0x0000 /* LANCE Controller Status */ |
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#define LE_CSR1 0x0001 /* IADR[15:0] */ |
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#define LE_CSR2 0x0002 /* IADR[23:16] */ |
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#define LE_CSR3 0x0003 /* Misc */ |
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/* |
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* Bit definitions for CSR0 (LANCE Controller Status) |
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*/ |
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#define LE_C0_ERR 0x8000 /* Error */ |
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#define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */ |
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#define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */ |
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#define LE_C0_MISS 0x1000 /* Missed Frame */ |
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#define LE_C0_MERR 0x0800 /* Memory Error */ |
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#define LE_C0_RINT 0x0400 /* Receive Interrupt */ |
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#define LE_C0_TINT 0x0200 /* Transmit Interrupt */ |
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#define LE_C0_IDON 0x0100 /* Initialization Done */ |
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#define LE_C0_INTR 0x0080 /* Interrupt Flag */ |
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#define LE_C0_INEA 0x0040 /* Interrupt Enable */ |
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#define LE_C0_RXON 0x0020 /* Receive On */ |
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#define LE_C0_TXON 0x0010 /* Transmit On */ |
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#define LE_C0_TDMD 0x0008 /* Transmit Demand */ |
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#define LE_C0_STOP 0x0004 /* Stop */ |
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#define LE_C0_STRT 0x0002 /* Start */ |
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#define LE_C0_INIT 0x0001 /* Initialize */ |
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/* |
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* Bit definitions for CSR3 |
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*/ |
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#define LE_C3_BSWP 0x0004 /* Byte Swap |
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(on for big endian byte order) */ |
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#define LE_C3_ACON 0x0002 /* ALE Control |
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(on for active low ALE) */ |
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#define LE_C3_BCON 0x0001 /* Byte Control */ |
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/* |
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* Mode Flags |
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*/ |
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#define LE_MO_PROM 0x8000 /* Promiscuous Mode */ |
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#define LE_MO_INTL 0x0040 /* Internal Loopback */ |
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#define LE_MO_DRTY 0x0020 /* Disable Retry */ |
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#define LE_MO_FCOLL 0x0010 /* Force Collision */ |
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#define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */ |
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#define LE_MO_LOOP 0x0004 /* Loopback Enable */ |
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#define LE_MO_DTX 0x0002 /* Disable Transmitter */ |
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#define LE_MO_DRX 0x0001 /* Disable Receiver */ |
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struct lance_rx_desc { |
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unsigned short rmd0; /* low address of packet */ |
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unsigned char rmd1_bits; /* descriptor bits */ |
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unsigned char rmd1_hadr; /* high address of packet */ |
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short length; /* This length is 2s complement (negative)! |
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* Buffer length |
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*/ |
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unsigned short mblength; /* Aactual number of bytes received */ |
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}; |
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struct lance_tx_desc { |
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unsigned short tmd0; /* low address of packet */ |
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unsigned char tmd1_bits; /* descriptor bits */ |
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unsigned char tmd1_hadr; /* high address of packet */ |
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short length; /* Length is 2s complement (negative)! */ |
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unsigned short misc; |
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}; |
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/* |
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* Receive Flags |
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*/ |
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#define LE_R1_OWN 0x80 /* LANCE owns the descriptor */ |
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#define LE_R1_ERR 0x40 /* Error */ |
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#define LE_R1_FRA 0x20 /* Framing Error */ |
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#define LE_R1_OFL 0x10 /* Overflow Error */ |
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#define LE_R1_CRC 0x08 /* CRC Error */ |
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#define LE_R1_BUF 0x04 /* Buffer Error */ |
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#define LE_R1_SOP 0x02 /* Start of Packet */ |
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#define LE_R1_EOP 0x01 /* End of Packet */ |
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#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ |
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/* |
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* Transmit Flags |
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*/ |
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#define LE_T1_OWN 0x80 /* LANCE owns the descriptor */ |
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#define LE_T1_ERR 0x40 /* Error */ |
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#define LE_T1_RES 0x20 /* Reserved, |
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LANCE writes this with a zero */ |
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#define LE_T1_EMORE 0x10 /* More than one retry needed */ |
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#define LE_T1_EONE 0x08 /* One retry needed */ |
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#define LE_T1_EDEF 0x04 /* Deferred */ |
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#define LE_T1_SOP 0x02 /* Start of Packet */ |
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#define LE_T1_EOP 0x01 /* End of Packet */ |
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#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ |
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/* |
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* Error Flags |
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*/ |
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#define LE_T3_BUF 0x8000 /* Buffer Error */ |
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#define LE_T3_UFL 0x4000 /* Underflow Error */ |
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#define LE_T3_LCOL 0x1000 /* Late Collision */ |
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#define LE_T3_CLOS 0x0800 /* Loss of Carrier */ |
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#define LE_T3_RTY 0x0400 /* Retry Error */ |
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#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */ |
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/* |
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* A2065 Expansion Board Structure |
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*/ |
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#define A2065_LANCE 0x4000 |
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#define A2065_RAM 0x8000 |
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#define A2065_RAM_SIZE 0x8000 |
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