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449 lines
12 KiB
449 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2014 IBM Corp. |
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*/ |
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|
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#include <linux/interrupt.h> |
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#include <linux/workqueue.h> |
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#include <linux/sched.h> |
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#include <linux/wait.h> |
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#include <linux/slab.h> |
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#include <linux/pid.h> |
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#include <asm/cputable.h> |
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#include <misc/cxl-base.h> |
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#include "cxl.h" |
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#include "trace.h" |
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static int afu_irq_range_start(void) |
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{ |
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if (cpu_has_feature(CPU_FTR_HVMODE)) |
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return 1; |
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return 0; |
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} |
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static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) |
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{ |
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ctx->dsisr = dsisr; |
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ctx->dar = dar; |
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schedule_work(&ctx->fault_work); |
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return IRQ_HANDLED; |
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} |
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irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info) |
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{ |
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u64 dsisr, dar; |
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dsisr = irq_info->dsisr; |
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dar = irq_info->dar; |
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trace_cxl_psl9_irq(ctx, irq, dsisr, dar); |
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pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); |
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if (dsisr & CXL_PSL9_DSISR_An_TF) { |
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pr_devel("CXL interrupt: Scheduling translation fault handling for later (pe: %i)\n", ctx->pe); |
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return schedule_cxl_fault(ctx, dsisr, dar); |
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} |
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if (dsisr & CXL_PSL9_DSISR_An_PE) |
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return cxl_ops->handle_psl_slice_error(ctx, dsisr, |
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irq_info->errstat); |
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if (dsisr & CXL_PSL9_DSISR_An_AE) { |
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pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err); |
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if (ctx->pending_afu_err) { |
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/* |
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* This shouldn't happen - the PSL treats these errors |
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* as fatal and will have reset the AFU, so there's not |
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* much point buffering multiple AFU errors. |
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* OTOH if we DO ever see a storm of these come in it's |
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* probably best that we log them somewhere: |
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*/ |
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dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error undelivered to pe %i: 0x%016llx\n", |
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ctx->pe, irq_info->afu_err); |
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} else { |
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spin_lock(&ctx->lock); |
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ctx->afu_err = irq_info->afu_err; |
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ctx->pending_afu_err = 1; |
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spin_unlock(&ctx->lock); |
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wake_up_all(&ctx->wq); |
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} |
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cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); |
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return IRQ_HANDLED; |
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} |
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if (dsisr & CXL_PSL9_DSISR_An_OC) |
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pr_devel("CXL interrupt: OS Context Warning\n"); |
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WARN(1, "Unhandled CXL PSL IRQ\n"); |
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return IRQ_HANDLED; |
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} |
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irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info) |
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{ |
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u64 dsisr, dar; |
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dsisr = irq_info->dsisr; |
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dar = irq_info->dar; |
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trace_cxl_psl_irq(ctx, irq, dsisr, dar); |
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pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); |
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if (dsisr & CXL_PSL_DSISR_An_DS) { |
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/* |
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* We don't inherently need to sleep to handle this, but we do |
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* need to get a ref to the task's mm, which we can't do from |
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* irq context without the potential for a deadlock since it |
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* takes the task_lock. An alternate option would be to keep a |
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* reference to the task's mm the entire time it has cxl open, |
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* but to do that we need to solve the issue where we hold a |
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* ref to the mm, but the mm can hold a ref to the fd after an |
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* mmap preventing anything from being cleaned up. |
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*/ |
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pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe); |
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return schedule_cxl_fault(ctx, dsisr, dar); |
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} |
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if (dsisr & CXL_PSL_DSISR_An_M) |
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pr_devel("CXL interrupt: PTE not found\n"); |
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if (dsisr & CXL_PSL_DSISR_An_P) |
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pr_devel("CXL interrupt: Storage protection violation\n"); |
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if (dsisr & CXL_PSL_DSISR_An_A) |
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pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n"); |
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if (dsisr & CXL_PSL_DSISR_An_S) |
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pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n"); |
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if (dsisr & CXL_PSL_DSISR_An_K) |
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pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n"); |
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if (dsisr & CXL_PSL_DSISR_An_DM) { |
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/* |
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* In some cases we might be able to handle the fault |
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* immediately if hash_page would succeed, but we still need |
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* the task's mm, which as above we can't get without a lock |
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*/ |
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pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe); |
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return schedule_cxl_fault(ctx, dsisr, dar); |
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} |
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if (dsisr & CXL_PSL_DSISR_An_ST) |
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WARN(1, "CXL interrupt: Segment Table PTE not found\n"); |
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if (dsisr & CXL_PSL_DSISR_An_UR) |
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pr_devel("CXL interrupt: AURP PTE not found\n"); |
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if (dsisr & CXL_PSL_DSISR_An_PE) |
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return cxl_ops->handle_psl_slice_error(ctx, dsisr, |
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irq_info->errstat); |
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if (dsisr & CXL_PSL_DSISR_An_AE) { |
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pr_devel("CXL interrupt: AFU Error 0x%016llx\n", irq_info->afu_err); |
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if (ctx->pending_afu_err) { |
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/* |
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* This shouldn't happen - the PSL treats these errors |
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* as fatal and will have reset the AFU, so there's not |
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* much point buffering multiple AFU errors. |
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* OTOH if we DO ever see a storm of these come in it's |
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* probably best that we log them somewhere: |
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*/ |
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dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error " |
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"undelivered to pe %i: 0x%016llx\n", |
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ctx->pe, irq_info->afu_err); |
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} else { |
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spin_lock(&ctx->lock); |
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ctx->afu_err = irq_info->afu_err; |
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ctx->pending_afu_err = true; |
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spin_unlock(&ctx->lock); |
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wake_up_all(&ctx->wq); |
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} |
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cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_A, 0); |
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return IRQ_HANDLED; |
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} |
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if (dsisr & CXL_PSL_DSISR_An_OC) |
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pr_devel("CXL interrupt: OS Context Warning\n"); |
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WARN(1, "Unhandled CXL PSL IRQ\n"); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t cxl_irq_afu(int irq, void *data) |
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{ |
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struct cxl_context *ctx = data; |
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irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); |
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int irq_off, afu_irq = 0; |
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__u16 range; |
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int r; |
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/* |
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* Look for the interrupt number. |
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* On bare-metal, we know range 0 only contains the PSL |
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* interrupt so we could start counting at range 1 and initialize |
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* afu_irq at 1. |
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* In a guest, range 0 also contains AFU interrupts, so it must |
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* be counted for. Therefore we initialize afu_irq at 0 to take into |
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* account the PSL interrupt. |
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* |
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* For code-readability, it just seems easier to go over all |
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* the ranges on bare-metal and guest. The end result is the same. |
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*/ |
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for (r = 0; r < CXL_IRQ_RANGES; r++) { |
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irq_off = hwirq - ctx->irqs.offset[r]; |
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range = ctx->irqs.range[r]; |
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if (irq_off >= 0 && irq_off < range) { |
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afu_irq += irq_off; |
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break; |
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} |
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afu_irq += range; |
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} |
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if (unlikely(r >= CXL_IRQ_RANGES)) { |
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WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n", |
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ctx->pe, irq, hwirq); |
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return IRQ_HANDLED; |
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} |
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trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq); |
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pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n", |
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afu_irq, ctx->pe, irq, hwirq); |
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if (unlikely(!ctx->irq_bitmap)) { |
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WARN(1, "Received AFU IRQ for context with no IRQ bitmap\n"); |
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return IRQ_HANDLED; |
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} |
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spin_lock(&ctx->lock); |
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set_bit(afu_irq - 1, ctx->irq_bitmap); |
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ctx->pending_irq = true; |
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spin_unlock(&ctx->lock); |
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wake_up_all(&ctx->wq); |
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return IRQ_HANDLED; |
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} |
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unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, |
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irq_handler_t handler, void *cookie, const char *name) |
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{ |
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unsigned int virq; |
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int result; |
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/* IRQ Domain? */ |
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virq = irq_create_mapping(NULL, hwirq); |
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if (!virq) { |
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dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n"); |
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return 0; |
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} |
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if (cxl_ops->setup_irq) |
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cxl_ops->setup_irq(adapter, hwirq, virq); |
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pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq); |
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result = request_irq(virq, handler, 0, name, cookie); |
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if (result) { |
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dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result); |
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return 0; |
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} |
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return virq; |
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} |
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void cxl_unmap_irq(unsigned int virq, void *cookie) |
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{ |
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free_irq(virq, cookie); |
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} |
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int cxl_register_one_irq(struct cxl *adapter, |
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irq_handler_t handler, |
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void *cookie, |
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irq_hw_number_t *dest_hwirq, |
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unsigned int *dest_virq, |
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const char *name) |
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{ |
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int hwirq, virq; |
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if ((hwirq = cxl_ops->alloc_one_irq(adapter)) < 0) |
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return hwirq; |
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if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name))) |
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goto err; |
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*dest_hwirq = hwirq; |
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*dest_virq = virq; |
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return 0; |
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err: |
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cxl_ops->release_one_irq(adapter, hwirq); |
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return -ENOMEM; |
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} |
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void afu_irq_name_free(struct cxl_context *ctx) |
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{ |
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struct cxl_irq_name *irq_name, *tmp; |
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list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) { |
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kfree(irq_name->name); |
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list_del(&irq_name->list); |
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kfree(irq_name); |
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} |
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} |
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int afu_allocate_irqs(struct cxl_context *ctx, u32 count) |
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{ |
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int rc, r, i, j = 1; |
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struct cxl_irq_name *irq_name; |
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int alloc_count; |
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/* |
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* In native mode, range 0 is reserved for the multiplexed |
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* PSL interrupt. It has been allocated when the AFU was initialized. |
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* |
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* In a guest, the PSL interrupt is not mutliplexed, but per-context, |
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* and is the first interrupt from range 0. It still needs to be |
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* allocated, so bump the count by one. |
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*/ |
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if (cpu_has_feature(CPU_FTR_HVMODE)) |
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alloc_count = count; |
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else |
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alloc_count = count + 1; |
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if ((rc = cxl_ops->alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, |
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alloc_count))) |
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return rc; |
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if (cpu_has_feature(CPU_FTR_HVMODE)) { |
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/* Multiplexed PSL Interrupt */ |
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ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; |
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ctx->irqs.range[0] = 1; |
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} |
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ctx->irq_count = count; |
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ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count), |
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sizeof(*ctx->irq_bitmap), GFP_KERNEL); |
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if (!ctx->irq_bitmap) |
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goto out; |
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/* |
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* Allocate names first. If any fail, bail out before allocating |
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* actual hardware IRQs. |
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*/ |
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for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) { |
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for (i = 0; i < ctx->irqs.range[r]; i++) { |
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irq_name = kmalloc(sizeof(struct cxl_irq_name), |
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GFP_KERNEL); |
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if (!irq_name) |
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goto out; |
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irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i", |
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dev_name(&ctx->afu->dev), |
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ctx->pe, j); |
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if (!irq_name->name) { |
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kfree(irq_name); |
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goto out; |
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} |
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/* Add to tail so next look get the correct order */ |
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list_add_tail(&irq_name->list, &ctx->irq_names); |
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j++; |
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} |
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} |
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return 0; |
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out: |
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cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); |
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afu_irq_name_free(ctx); |
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return -ENOMEM; |
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} |
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static void afu_register_hwirqs(struct cxl_context *ctx) |
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{ |
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irq_hw_number_t hwirq; |
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struct cxl_irq_name *irq_name; |
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int r, i; |
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irqreturn_t (*handler)(int irq, void *data); |
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/* We've allocated all memory now, so let's do the irq allocations */ |
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irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list); |
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for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) { |
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hwirq = ctx->irqs.offset[r]; |
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for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) { |
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if (r == 0 && i == 0) |
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/* |
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* The very first interrupt of range 0 is |
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* always the PSL interrupt, but we only |
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* need to connect a handler for guests, |
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* because there's one PSL interrupt per |
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* context. |
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* On bare-metal, the PSL interrupt is |
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* multiplexed and was setup when the AFU |
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* was configured. |
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*/ |
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handler = cxl_ops->psl_interrupt; |
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else |
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handler = cxl_irq_afu; |
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cxl_map_irq(ctx->afu->adapter, hwirq, handler, ctx, |
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irq_name->name); |
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irq_name = list_next_entry(irq_name, list); |
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} |
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} |
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} |
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int afu_register_irqs(struct cxl_context *ctx, u32 count) |
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{ |
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int rc; |
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rc = afu_allocate_irqs(ctx, count); |
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if (rc) |
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return rc; |
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afu_register_hwirqs(ctx); |
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return 0; |
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} |
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void afu_release_irqs(struct cxl_context *ctx, void *cookie) |
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{ |
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irq_hw_number_t hwirq; |
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unsigned int virq; |
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int r, i; |
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for (r = afu_irq_range_start(); r < CXL_IRQ_RANGES; r++) { |
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hwirq = ctx->irqs.offset[r]; |
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for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) { |
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virq = irq_find_mapping(NULL, hwirq); |
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if (virq) |
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cxl_unmap_irq(virq, cookie); |
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} |
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} |
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afu_irq_name_free(ctx); |
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cxl_ops->release_irq_ranges(&ctx->irqs, ctx->afu->adapter); |
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ctx->irq_count = 0; |
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} |
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void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr) |
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{ |
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dev_crit(&afu->dev, |
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"PSL Slice error received. Check AFU for root cause.\n"); |
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dev_crit(&afu->dev, "PSL_SERR_An: 0x%016llx\n", serr); |
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if (serr & CXL_PSL_SERR_An_afuto) |
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dev_crit(&afu->dev, "AFU MMIO Timeout\n"); |
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if (serr & CXL_PSL_SERR_An_afudis) |
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dev_crit(&afu->dev, |
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"MMIO targeted Accelerator that was not enabled\n"); |
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if (serr & CXL_PSL_SERR_An_afuov) |
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dev_crit(&afu->dev, "AFU CTAG Overflow\n"); |
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if (serr & CXL_PSL_SERR_An_badsrc) |
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dev_crit(&afu->dev, "Bad Interrupt Source\n"); |
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if (serr & CXL_PSL_SERR_An_badctx) |
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dev_crit(&afu->dev, "Bad Context Handle\n"); |
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if (serr & CXL_PSL_SERR_An_llcmdis) |
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dev_crit(&afu->dev, "LLCMD to Disabled AFU\n"); |
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if (serr & CXL_PSL_SERR_An_llcmdto) |
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dev_crit(&afu->dev, "LLCMD Timeout to AFU\n"); |
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if (serr & CXL_PSL_SERR_An_afupar) |
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dev_crit(&afu->dev, "AFU MMIO Parity Error\n"); |
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if (serr & CXL_PSL_SERR_An_afudup) |
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dev_crit(&afu->dev, "AFU MMIO Duplicate CTAG Error\n"); |
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if (serr & CXL_PSL_SERR_An_AE) |
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dev_crit(&afu->dev, |
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"AFU asserted JDONE with JERROR in AFU Directed Mode\n"); |
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}
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