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639 lines
16 KiB
639 lines
16 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2013 Texas Instruments Inc. |
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* |
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* David Griego, <[email protected]> |
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* Dale Farnsworth, <[email protected]> |
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* Archit Taneja, <[email protected]> |
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*/ |
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|
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#ifndef _TI_VPDMA_PRIV_H_ |
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#define _TI_VPDMA_PRIV_H_ |
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|
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/* |
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* VPDMA Register offsets |
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*/ |
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|
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/* Top level */ |
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#define VPDMA_PID 0x00 |
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#define VPDMA_LIST_ADDR 0x04 |
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#define VPDMA_LIST_ATTR 0x08 |
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#define VPDMA_LIST_STAT_SYNC 0x0c |
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#define VPDMA_BG_RGB 0x18 |
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#define VPDMA_BG_YUV 0x1c |
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#define VPDMA_SETUP 0x30 |
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#define VPDMA_MAX_SIZE1 0x34 |
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#define VPDMA_MAX_SIZE2 0x38 |
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#define VPDMA_MAX_SIZE3 0x3c |
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#define VPDMA_MAX_SIZE_WIDTH_MASK 0xffff |
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#define VPDMA_MAX_SIZE_WIDTH_SHFT 16 |
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#define VPDMA_MAX_SIZE_HEIGHT_MASK 0xffff |
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#define VPDMA_MAX_SIZE_HEIGHT_SHFT 0 |
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|
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/* Interrupts */ |
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#define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8) |
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#define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4) |
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#define VPDMA_INT_CLIENT0_STAT 0x78 |
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#define VPDMA_INT_CLIENT0_MASK 0x7c |
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#define VPDMA_INT_CLIENT1_STAT 0x80 |
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#define VPDMA_INT_CLIENT1_MASK 0x84 |
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#define VPDMA_INT_LIST0_STAT 0x88 |
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#define VPDMA_INT_LIST0_MASK 0x8c |
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#define VPDMA_INTX_OFFSET 0x50 |
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|
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#define VPDMA_PERFMON(i) (0x200 + i * 4) |
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|
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/* VIP/VPE client registers */ |
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#define VPDMA_DEI_CHROMA1_CSTAT 0x0300 |
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#define VPDMA_DEI_LUMA1_CSTAT 0x0304 |
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#define VPDMA_DEI_LUMA2_CSTAT 0x0308 |
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#define VPDMA_DEI_CHROMA2_CSTAT 0x030c |
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#define VPDMA_DEI_LUMA3_CSTAT 0x0310 |
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#define VPDMA_DEI_CHROMA3_CSTAT 0x0314 |
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#define VPDMA_DEI_MV_IN_CSTAT 0x0330 |
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#define VPDMA_DEI_MV_OUT_CSTAT 0x033c |
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#define VPDMA_VIP_LO_Y_CSTAT 0x0388 |
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#define VPDMA_VIP_LO_UV_CSTAT 0x038c |
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#define VPDMA_VIP_UP_Y_CSTAT 0x0390 |
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#define VPDMA_VIP_UP_UV_CSTAT 0x0394 |
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#define VPDMA_VPI_CTL_CSTAT 0x03d0 |
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/* Reg field info for VPDMA_CLIENT_CSTAT registers */ |
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#define VPDMA_CSTAT_LINE_MODE_MASK 0x03 |
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#define VPDMA_CSTAT_LINE_MODE_SHIFT 8 |
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#define VPDMA_CSTAT_FRAME_START_MASK 0xf |
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#define VPDMA_CSTAT_FRAME_START_SHIFT 10 |
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#define VPDMA_LIST_NUM_MASK 0x07 |
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#define VPDMA_LIST_NUM_SHFT 24 |
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#define VPDMA_LIST_STOP_SHFT 20 |
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#define VPDMA_LIST_RDY_MASK 0x01 |
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#define VPDMA_LIST_RDY_SHFT 19 |
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#define VPDMA_LIST_TYPE_MASK 0x03 |
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#define VPDMA_LIST_TYPE_SHFT 16 |
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#define VPDMA_LIST_SIZE_MASK 0xffff |
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/* |
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* The YUV data type definition below are taken from |
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* both the TRM and i839 Errata information. |
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* Use the correct data type considering byte |
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* reordering of components. |
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* |
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* Also since the single use of "C" in the 422 case |
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* to mean "Cr" (i.e. V component). It was decided |
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* to explicitly label them CR to remove any confusion. |
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* Bear in mind that the type label refer to the memory |
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* packed order (LSB - MSB). |
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*/ |
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#define DATA_TYPE_Y444 0x0 |
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#define DATA_TYPE_Y422 0x1 |
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#define DATA_TYPE_Y420 0x2 |
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#define DATA_TYPE_C444 0x4 |
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#define DATA_TYPE_C422 0x5 |
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#define DATA_TYPE_C420 0x6 |
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#define DATA_TYPE_CB420 0x16 |
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#define DATA_TYPE_YC444 0x8 |
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#define DATA_TYPE_YCB422 0x7 |
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#define DATA_TYPE_YCR422 0x17 |
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#define DATA_TYPE_CBY422 0x27 |
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#define DATA_TYPE_CRY422 0x37 |
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|
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/* |
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* The RGB data type definition below are defined |
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* to follow Errata i819. |
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* The initial values were taken from: |
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* VPDMA_data_type_mapping_v0.2vayu_c.pdf |
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* But some of the ARGB definition appeared to be wrong |
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* in the document also. As they would yield RGBA instead. |
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* They have been corrected based on experimentation. |
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*/ |
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#define DATA_TYPE_RGB16_565 0x10 |
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#define DATA_TYPE_ARGB_1555 0x13 |
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#define DATA_TYPE_ARGB_4444 0x14 |
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#define DATA_TYPE_RGBA_5551 0x11 |
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#define DATA_TYPE_RGBA_4444 0x12 |
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#define DATA_TYPE_ARGB24_6666 0x18 |
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#define DATA_TYPE_RGB24_888 0x16 |
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#define DATA_TYPE_ARGB32_8888 0x17 |
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#define DATA_TYPE_RGBA24_6666 0x15 |
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#define DATA_TYPE_RGBA32_8888 0x19 |
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#define DATA_TYPE_BGR16_565 0x0 |
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#define DATA_TYPE_ABGR_1555 0x3 |
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#define DATA_TYPE_ABGR_4444 0x4 |
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#define DATA_TYPE_BGRA_5551 0x1 |
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#define DATA_TYPE_BGRA_4444 0x2 |
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#define DATA_TYPE_ABGR24_6666 0x8 |
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#define DATA_TYPE_BGR24_888 0x6 |
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#define DATA_TYPE_ABGR32_8888 0x7 |
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#define DATA_TYPE_BGRA24_6666 0x5 |
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#define DATA_TYPE_BGRA32_8888 0x9 |
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#define DATA_TYPE_MV 0x3 |
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/* VPDMA channel numbers, some are common between VIP/VPE and appear twice */ |
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#define VPE_CHAN_NUM_LUMA1_IN 0 |
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#define VPE_CHAN_NUM_CHROMA1_IN 1 |
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#define VPE_CHAN_NUM_LUMA2_IN 2 |
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#define VPE_CHAN_NUM_CHROMA2_IN 3 |
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#define VPE_CHAN_NUM_LUMA3_IN 4 |
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#define VPE_CHAN_NUM_CHROMA3_IN 5 |
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#define VPE_CHAN_NUM_MV_IN 12 |
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#define VPE_CHAN_NUM_MV_OUT 15 |
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#define VIP1_CHAN_NUM_MULT_PORT_A_SRC0 38 |
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#define VIP1_CHAN_NUM_MULT_ANC_A_SRC0 70 |
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#define VPE_CHAN_NUM_LUMA_OUT 102 |
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#define VPE_CHAN_NUM_CHROMA_OUT 103 |
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#define VIP1_CHAN_NUM_PORT_A_LUMA 102 |
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#define VIP1_CHAN_NUM_PORT_A_CHROMA 103 |
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#define VPE_CHAN_NUM_RGB_OUT 106 |
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#define VIP1_CHAN_NUM_PORT_A_RGB 106 |
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#define VIP1_CHAN_NUM_PORT_B_RGB 107 |
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/* |
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* a VPDMA address data block payload for a configuration descriptor needs to |
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* have each sub block length as a multiple of 16 bytes. Therefore, the overall |
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* size of the payload also needs to be a multiple of 16 bytes. The sub block |
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* lengths should be ensured to be aligned by the VPDMA user. |
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*/ |
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#define VPDMA_ADB_SIZE_ALIGN 0x0f |
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|
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/* |
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* data transfer descriptor |
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*/ |
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struct vpdma_dtd { |
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u32 type_ctl_stride; |
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union { |
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u32 xfer_length_height; |
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u32 w1; |
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}; |
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u32 start_addr; |
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u32 pkt_ctl; |
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union { |
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u32 frame_width_height; /* inbound */ |
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u32 desc_write_addr; /* outbound */ |
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}; |
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union { |
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u32 start_h_v; /* inbound */ |
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u32 max_width_height; /* outbound */ |
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}; |
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u32 client_attr0; |
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u32 client_attr1; |
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}; |
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/* Data Transfer Descriptor specifics */ |
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#define DTD_NO_NOTIFY 0 |
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#define DTD_NOTIFY 1 |
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#define DTD_PKT_TYPE 0xa |
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#define DTD_DIR_IN 0 |
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#define DTD_DIR_OUT 1 |
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/* type_ctl_stride */ |
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#define DTD_DATA_TYPE_MASK 0x3f |
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#define DTD_DATA_TYPE_SHFT 26 |
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#define DTD_NOTIFY_MASK 0x01 |
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#define DTD_NOTIFY_SHFT 25 |
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#define DTD_FIELD_MASK 0x01 |
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#define DTD_FIELD_SHFT 24 |
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#define DTD_1D_MASK 0x01 |
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#define DTD_1D_SHFT 23 |
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#define DTD_EVEN_LINE_SKIP_MASK 0x01 |
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#define DTD_EVEN_LINE_SKIP_SHFT 20 |
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#define DTD_ODD_LINE_SKIP_MASK 0x01 |
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#define DTD_ODD_LINE_SKIP_SHFT 16 |
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#define DTD_LINE_STRIDE_MASK 0xffff |
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#define DTD_LINE_STRIDE_SHFT 0 |
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/* xfer_length_height */ |
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#define DTD_LINE_LENGTH_MASK 0xffff |
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#define DTD_LINE_LENGTH_SHFT 16 |
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#define DTD_XFER_HEIGHT_MASK 0xffff |
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#define DTD_XFER_HEIGHT_SHFT 0 |
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/* pkt_ctl */ |
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#define DTD_PKT_TYPE_MASK 0x1f |
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#define DTD_PKT_TYPE_SHFT 27 |
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#define DTD_MODE_MASK 0x01 |
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#define DTD_MODE_SHFT 26 |
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#define DTD_DIR_MASK 0x01 |
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#define DTD_DIR_SHFT 25 |
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#define DTD_CHAN_MASK 0x01ff |
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#define DTD_CHAN_SHFT 16 |
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#define DTD_PRI_MASK 0x0f |
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#define DTD_PRI_SHFT 9 |
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#define DTD_NEXT_CHAN_MASK 0x01ff |
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#define DTD_NEXT_CHAN_SHFT 0 |
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/* frame_width_height */ |
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#define DTD_FRAME_WIDTH_MASK 0xffff |
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#define DTD_FRAME_WIDTH_SHFT 16 |
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#define DTD_FRAME_HEIGHT_MASK 0xffff |
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#define DTD_FRAME_HEIGHT_SHFT 0 |
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/* start_h_v */ |
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#define DTD_H_START_MASK 0xffff |
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#define DTD_H_START_SHFT 16 |
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#define DTD_V_START_MASK 0xffff |
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#define DTD_V_START_SHFT 0 |
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#define DTD_DESC_START_MASK 0xffffffe0 |
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#define DTD_DESC_START_SHIFT 5 |
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#define DTD_WRITE_DESC_MASK 0x01 |
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#define DTD_WRITE_DESC_SHIFT 2 |
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#define DTD_DROP_DATA_MASK 0x01 |
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#define DTD_DROP_DATA_SHIFT 1 |
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#define DTD_USE_DESC_MASK 0x01 |
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#define DTD_USE_DESC_SHIFT 0 |
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/* max_width_height */ |
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#define DTD_MAX_WIDTH_MASK 0x07 |
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#define DTD_MAX_WIDTH_SHFT 4 |
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#define DTD_MAX_HEIGHT_MASK 0x07 |
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#define DTD_MAX_HEIGHT_SHFT 0 |
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static inline u32 dtd_type_ctl_stride(int type, bool notify, int field, |
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bool one_d, bool even_line_skip, bool odd_line_skip, |
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int line_stride) |
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{ |
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return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) | |
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(field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) | |
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(even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) | |
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(odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) | |
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line_stride; |
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} |
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static inline u32 dtd_xfer_length_height(int line_length, int xfer_height) |
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{ |
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return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height; |
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} |
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static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri, |
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int next_chan) |
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{ |
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return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) | |
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(dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) | |
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(pri << DTD_PRI_SHFT) | next_chan; |
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} |
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static inline u32 dtd_frame_width_height(int width, int height) |
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{ |
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return (width << DTD_FRAME_WIDTH_SHFT) | height; |
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} |
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static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc, |
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bool drop_data, bool use_desc) |
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{ |
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return (addr & DTD_DESC_START_MASK) | |
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(write_desc << DTD_WRITE_DESC_SHIFT) | |
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(drop_data << DTD_DROP_DATA_SHIFT) | |
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use_desc; |
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} |
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static inline u32 dtd_start_h_v(int h_start, int v_start) |
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{ |
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return (h_start << DTD_H_START_SHFT) | v_start; |
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} |
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static inline u32 dtd_max_width_height(int max_width, int max_height) |
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{ |
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return (max_width << DTD_MAX_WIDTH_SHFT) | max_height; |
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} |
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static inline int dtd_get_data_type(struct vpdma_dtd *dtd) |
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{ |
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return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT; |
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} |
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static inline bool dtd_get_notify(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK; |
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} |
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static inline int dtd_get_field(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK; |
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} |
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static inline bool dtd_get_1d(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK; |
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} |
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static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT) |
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& DTD_EVEN_LINE_SKIP_MASK; |
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} |
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static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT) |
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& DTD_ODD_LINE_SKIP_MASK; |
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} |
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static inline int dtd_get_line_stride(struct vpdma_dtd *dtd) |
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{ |
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return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK; |
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} |
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static inline int dtd_get_line_length(struct vpdma_dtd *dtd) |
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{ |
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return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT; |
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} |
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static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd) |
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{ |
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return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK; |
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} |
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static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd) |
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{ |
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return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT; |
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} |
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static inline bool dtd_get_mode(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK; |
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} |
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static inline bool dtd_get_dir(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK; |
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} |
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static inline int dtd_get_chan(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK; |
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} |
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static inline int dtd_get_priority(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK; |
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} |
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static inline int dtd_get_next_chan(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK; |
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} |
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static inline int dtd_get_frame_width(struct vpdma_dtd *dtd) |
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{ |
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return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT; |
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} |
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static inline int dtd_get_frame_height(struct vpdma_dtd *dtd) |
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{ |
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return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK; |
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} |
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static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd) |
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{ |
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return dtd->desc_write_addr & DTD_DESC_START_MASK; |
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} |
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static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) & |
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DTD_WRITE_DESC_MASK; |
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} |
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static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) & |
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DTD_DROP_DATA_MASK; |
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} |
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static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd) |
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{ |
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return dtd->desc_write_addr & DTD_USE_DESC_MASK; |
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} |
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static inline int dtd_get_h_start(struct vpdma_dtd *dtd) |
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{ |
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return dtd->start_h_v >> DTD_H_START_SHFT; |
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} |
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static inline int dtd_get_v_start(struct vpdma_dtd *dtd) |
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{ |
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return dtd->start_h_v & DTD_V_START_MASK; |
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} |
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static inline int dtd_get_max_width(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) & |
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DTD_MAX_WIDTH_MASK; |
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} |
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static inline int dtd_get_max_height(struct vpdma_dtd *dtd) |
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{ |
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return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) & |
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DTD_MAX_HEIGHT_MASK; |
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} |
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|
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/* |
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* configuration descriptor |
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*/ |
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struct vpdma_cfd { |
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union { |
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u32 dest_addr_offset; |
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u32 w0; |
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}; |
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union { |
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u32 block_len; /* in words */ |
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u32 w1; |
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}; |
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u32 payload_addr; |
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u32 ctl_payload_len; /* in words */ |
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}; |
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|
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/* Configuration descriptor specifics */ |
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|
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#define CFD_PKT_TYPE 0xb |
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#define CFD_DIRECT 1 |
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#define CFD_INDIRECT 0 |
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#define CFD_CLS_ADB 0 |
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#define CFD_CLS_BLOCK 1 |
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|
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/* block_len */ |
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#define CFD__BLOCK_LEN_MASK 0xffff |
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#define CFD__BLOCK_LEN_SHFT 0 |
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|
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/* ctl_payload_len */ |
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#define CFD_PKT_TYPE_MASK 0x1f |
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#define CFD_PKT_TYPE_SHFT 27 |
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#define CFD_DIRECT_MASK 0x01 |
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#define CFD_DIRECT_SHFT 26 |
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#define CFD_CLASS_MASK 0x03 |
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#define CFD_CLASS_SHFT 24 |
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#define CFD_DEST_MASK 0xff |
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#define CFD_DEST_SHFT 16 |
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#define CFD_PAYLOAD_LEN_MASK 0xffff |
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#define CFD_PAYLOAD_LEN_SHFT 0 |
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|
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static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest, |
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int payload_len) |
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{ |
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return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) | |
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(direct << CFD_DIRECT_SHFT) | |
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(cls << CFD_CLASS_SHFT) | |
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(dest << CFD_DEST_SHFT) | |
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payload_len; |
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} |
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static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd) |
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{ |
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return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT; |
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} |
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static inline bool cfd_get_direct(struct vpdma_cfd *cfd) |
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{ |
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return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK; |
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} |
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static inline bool cfd_get_class(struct vpdma_cfd *cfd) |
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{ |
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return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK; |
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} |
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|
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static inline int cfd_get_dest(struct vpdma_cfd *cfd) |
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{ |
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return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK; |
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} |
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static inline int cfd_get_payload_len(struct vpdma_cfd *cfd) |
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{ |
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return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK; |
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} |
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|
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/* |
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* control descriptor |
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*/ |
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struct vpdma_ctd { |
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union { |
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u32 timer_value; |
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u32 list_addr; |
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u32 w0; |
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}; |
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union { |
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u32 pixel_line_count; |
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u32 list_size; |
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u32 w1; |
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}; |
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union { |
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u32 event; |
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u32 fid_ctl; |
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u32 w2; |
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}; |
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u32 type_source_ctl; |
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}; |
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|
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/* control descriptor types */ |
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#define CTD_TYPE_SYNC_ON_CLIENT 0 |
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#define CTD_TYPE_SYNC_ON_LIST 1 |
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#define CTD_TYPE_SYNC_ON_EXT 2 |
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#define CTD_TYPE_SYNC_ON_LM_TIMER 3 |
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#define CTD_TYPE_SYNC_ON_CHANNEL 4 |
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#define CTD_TYPE_CHNG_CLIENT_IRQ 5 |
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#define CTD_TYPE_SEND_IRQ 6 |
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#define CTD_TYPE_RELOAD_LIST 7 |
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#define CTD_TYPE_ABORT_CHANNEL 8 |
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|
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#define CTD_PKT_TYPE 0xc |
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|
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/* timer_value */ |
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#define CTD_TIMER_VALUE_MASK 0xffff |
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#define CTD_TIMER_VALUE_SHFT 0 |
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|
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/* pixel_line_count */ |
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#define CTD_PIXEL_COUNT_MASK 0xffff |
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#define CTD_PIXEL_COUNT_SHFT 16 |
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#define CTD_LINE_COUNT_MASK 0xffff |
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#define CTD_LINE_COUNT_SHFT 0 |
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|
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/* list_size */ |
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#define CTD_LIST_SIZE_MASK 0xffff |
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#define CTD_LIST_SIZE_SHFT 0 |
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|
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/* event */ |
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#define CTD_EVENT_MASK 0x0f |
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#define CTD_EVENT_SHFT 0 |
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|
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/* fid_ctl */ |
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#define CTD_FID2_MASK 0x03 |
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#define CTD_FID2_SHFT 4 |
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#define CTD_FID1_MASK 0x03 |
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#define CTD_FID1_SHFT 2 |
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#define CTD_FID0_MASK 0x03 |
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#define CTD_FID0_SHFT 0 |
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|
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/* type_source_ctl */ |
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#define CTD_PKT_TYPE_MASK 0x1f |
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#define CTD_PKT_TYPE_SHFT 27 |
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#define CTD_SOURCE_MASK 0xff |
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#define CTD_SOURCE_SHFT 16 |
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#define CTD_CONTROL_MASK 0x0f |
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#define CTD_CONTROL_SHFT 0 |
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|
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static inline u32 ctd_pixel_line_count(int pixel_count, int line_count) |
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{ |
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return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count; |
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} |
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|
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static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2) |
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{ |
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return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0; |
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} |
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|
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static inline u32 ctd_type_source_ctl(int source, int control) |
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{ |
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return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) | |
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(source << CTD_SOURCE_SHFT) | control; |
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} |
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|
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static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd) |
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{ |
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return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT; |
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} |
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|
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static inline int ctd_get_line_count(struct vpdma_ctd *ctd) |
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{ |
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return ctd->pixel_line_count & CTD_LINE_COUNT_MASK; |
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} |
|
|
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static inline int ctd_get_event(struct vpdma_ctd *ctd) |
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{ |
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return ctd->event & CTD_EVENT_MASK; |
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} |
|
|
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static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd) |
|
{ |
|
return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK; |
|
} |
|
|
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static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd) |
|
{ |
|
return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK; |
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} |
|
|
|
static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd) |
|
{ |
|
return ctd->fid_ctl & CTD_FID2_MASK; |
|
} |
|
|
|
static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd) |
|
{ |
|
return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT; |
|
} |
|
|
|
static inline int ctd_get_source(struct vpdma_ctd *ctd) |
|
{ |
|
return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK; |
|
} |
|
|
|
static inline int ctd_get_ctl(struct vpdma_ctd *ctd) |
|
{ |
|
return ctd->type_source_ctl & CTD_CONTROL_MASK; |
|
} |
|
|
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#endif
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