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346 lines
9.2 KiB
346 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Register interface file for EXYNOS FIMC-LITE (camera interface) driver |
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* |
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* Copyright (C) 2012 Samsung Electronics Co., Ltd. |
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* Author: Sylwester Nawrocki <[email protected]> |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <media/drv-intf/exynos-fimc.h> |
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#include "fimc-lite-reg.h" |
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#include "fimc-lite.h" |
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#include "fimc-core.h" |
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#define FLITE_RESET_TIMEOUT 50 /* in ms */ |
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void flite_hw_reset(struct fimc_lite *dev) |
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{ |
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unsigned long end = jiffies + msecs_to_jiffies(FLITE_RESET_TIMEOUT); |
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u32 cfg; |
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cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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while (time_is_after_jiffies(end)) { |
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cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) |
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break; |
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usleep_range(1000, 5000); |
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} |
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cfg |= FLITE_REG_CIGCTRL_SWRST; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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} |
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void flite_hw_clear_pending_irq(struct fimc_lite *dev) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); |
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cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; |
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writel(cfg, dev->regs + FLITE_REG_CISTATUS); |
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} |
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u32 flite_hw_get_interrupt_source(struct fimc_lite *dev) |
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{ |
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u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); |
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return intsrc & FLITE_REG_CISTATUS_IRQ_MASK; |
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} |
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void flite_hw_clear_last_capture_end(struct fimc_lite *dev) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); |
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cfg &= ~FLITE_REG_CISTATUS2_LASTCAPEND; |
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writel(cfg, dev->regs + FLITE_REG_CISTATUS2); |
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} |
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void flite_hw_set_interrupt_mask(struct fimc_lite *dev) |
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{ |
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u32 cfg, intsrc; |
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/* Select interrupts to be enabled for each output mode */ |
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if (atomic_read(&dev->out_path) == FIMC_IO_DMA) { |
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intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN | |
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FLITE_REG_CIGCTRL_IRQ_LASTEN | |
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FLITE_REG_CIGCTRL_IRQ_STARTEN | |
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FLITE_REG_CIGCTRL_IRQ_ENDEN; |
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} else { |
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/* An output to the FIMC-IS */ |
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intsrc = FLITE_REG_CIGCTRL_IRQ_OVFEN | |
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FLITE_REG_CIGCTRL_IRQ_LASTEN; |
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} |
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cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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cfg |= FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK; |
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cfg &= ~intsrc; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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} |
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void flite_hw_capture_start(struct fimc_lite *dev) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); |
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cfg |= FLITE_REG_CIIMGCPT_IMGCPTEN; |
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writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); |
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} |
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void flite_hw_capture_stop(struct fimc_lite *dev) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); |
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cfg &= ~FLITE_REG_CIIMGCPT_IMGCPTEN; |
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writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); |
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} |
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/* |
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* Test pattern (color bars) enable/disable. External sensor |
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* pixel clock must be active for the test pattern to work. |
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*/ |
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void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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if (on) |
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cfg |= FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR; |
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else |
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cfg &= ~FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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} |
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static const u32 src_pixfmt_map[8][3] = { |
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{ MEDIA_BUS_FMT_YUYV8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR, |
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FLITE_REG_CIGCTRL_YUV422_1P }, |
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{ MEDIA_BUS_FMT_YVYU8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB, |
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FLITE_REG_CIGCTRL_YUV422_1P }, |
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{ MEDIA_BUS_FMT_UYVY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY, |
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FLITE_REG_CIGCTRL_YUV422_1P }, |
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{ MEDIA_BUS_FMT_VYUY8_2X8, FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY, |
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FLITE_REG_CIGCTRL_YUV422_1P }, |
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{ MEDIA_BUS_FMT_SGRBG8_1X8, 0, FLITE_REG_CIGCTRL_RAW8 }, |
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{ MEDIA_BUS_FMT_SGRBG10_1X10, 0, FLITE_REG_CIGCTRL_RAW10 }, |
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{ MEDIA_BUS_FMT_SGRBG12_1X12, 0, FLITE_REG_CIGCTRL_RAW12 }, |
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{ MEDIA_BUS_FMT_JPEG_1X8, 0, FLITE_REG_CIGCTRL_USER(1) }, |
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}; |
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/* Set camera input pixel format and resolution */ |
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void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f) |
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{ |
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u32 pixelcode = f->fmt->mbus_code; |
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int i = ARRAY_SIZE(src_pixfmt_map); |
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u32 cfg; |
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while (--i) { |
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if (src_pixfmt_map[i][0] == pixelcode) |
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break; |
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} |
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if (i == 0 && src_pixfmt_map[i][0] != pixelcode) { |
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v4l2_err(&dev->ve.vdev, |
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"Unsupported pixel code, falling back to %#08x\n", |
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src_pixfmt_map[i][0]); |
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} |
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cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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cfg &= ~FLITE_REG_CIGCTRL_FMT_MASK; |
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cfg |= src_pixfmt_map[i][2]; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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cfg = readl(dev->regs + FLITE_REG_CISRCSIZE); |
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cfg &= ~(FLITE_REG_CISRCSIZE_ORDER422_MASK | |
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FLITE_REG_CISRCSIZE_SIZE_CAM_MASK); |
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cfg |= (f->f_width << 16) | f->f_height; |
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cfg |= src_pixfmt_map[i][1]; |
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writel(cfg, dev->regs + FLITE_REG_CISRCSIZE); |
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} |
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/* Set the camera host input window offsets (cropping) */ |
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void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f) |
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{ |
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u32 hoff2, voff2; |
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u32 cfg; |
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cfg = readl(dev->regs + FLITE_REG_CIWDOFST); |
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cfg &= ~FLITE_REG_CIWDOFST_OFST_MASK; |
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cfg |= (f->rect.left << 16) | f->rect.top; |
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cfg |= FLITE_REG_CIWDOFST_WINOFSEN; |
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writel(cfg, dev->regs + FLITE_REG_CIWDOFST); |
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hoff2 = f->f_width - f->rect.width - f->rect.left; |
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voff2 = f->f_height - f->rect.height - f->rect.top; |
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cfg = (hoff2 << 16) | voff2; |
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writel(cfg, dev->regs + FLITE_REG_CIWDOFST2); |
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} |
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/* Select camera port (A, B) */ |
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static void flite_hw_set_camera_port(struct fimc_lite *dev, int id) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL); |
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if (id == 0) |
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cfg &= ~FLITE_REG_CIGENERAL_CAM_B; |
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else |
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cfg |= FLITE_REG_CIGENERAL_CAM_B; |
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writel(cfg, dev->regs + FLITE_REG_CIGENERAL); |
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} |
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/* Select serial or parallel bus, camera port (A,B) and set signals polarity */ |
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void flite_hw_set_camera_bus(struct fimc_lite *dev, |
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struct fimc_source_info *si) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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unsigned int flags = si->flags; |
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if (si->sensor_bus_type != FIMC_BUS_TYPE_MIPI_CSI2) { |
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cfg &= ~(FLITE_REG_CIGCTRL_SELCAM_MIPI | |
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FLITE_REG_CIGCTRL_INVPOLPCLK | |
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FLITE_REG_CIGCTRL_INVPOLVSYNC | |
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FLITE_REG_CIGCTRL_INVPOLHREF); |
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if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
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cfg |= FLITE_REG_CIGCTRL_INVPOLPCLK; |
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if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
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cfg |= FLITE_REG_CIGCTRL_INVPOLVSYNC; |
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if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
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cfg |= FLITE_REG_CIGCTRL_INVPOLHREF; |
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} else { |
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cfg |= FLITE_REG_CIGCTRL_SELCAM_MIPI; |
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} |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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flite_hw_set_camera_port(dev, si->mux_id); |
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} |
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static void flite_hw_set_pack12(struct fimc_lite *dev, int on) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); |
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cfg &= ~FLITE_REG_CIODMAFMT_PACK12; |
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if (on) |
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cfg |= FLITE_REG_CIODMAFMT_PACK12; |
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writel(cfg, dev->regs + FLITE_REG_CIODMAFMT); |
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} |
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static void flite_hw_set_out_order(struct fimc_lite *dev, struct flite_frame *f) |
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{ |
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static const u32 pixcode[4][2] = { |
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{ MEDIA_BUS_FMT_YUYV8_2X8, FLITE_REG_CIODMAFMT_YCBYCR }, |
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{ MEDIA_BUS_FMT_YVYU8_2X8, FLITE_REG_CIODMAFMT_YCRYCB }, |
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{ MEDIA_BUS_FMT_UYVY8_2X8, FLITE_REG_CIODMAFMT_CBYCRY }, |
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{ MEDIA_BUS_FMT_VYUY8_2X8, FLITE_REG_CIODMAFMT_CRYCBY }, |
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}; |
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u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT); |
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int i = ARRAY_SIZE(pixcode); |
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while (--i) |
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if (pixcode[i][0] == f->fmt->mbus_code) |
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break; |
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cfg &= ~FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK; |
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writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT); |
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} |
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void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f) |
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{ |
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u32 cfg; |
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/* Maximum output pixel size */ |
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cfg = readl(dev->regs + FLITE_REG_CIOCAN); |
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cfg &= ~FLITE_REG_CIOCAN_MASK; |
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cfg |= (f->f_height << 16) | f->f_width; |
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writel(cfg, dev->regs + FLITE_REG_CIOCAN); |
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/* DMA offsets */ |
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cfg = readl(dev->regs + FLITE_REG_CIOOFF); |
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cfg &= ~FLITE_REG_CIOOFF_MASK; |
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cfg |= (f->rect.top << 16) | f->rect.left; |
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writel(cfg, dev->regs + FLITE_REG_CIOOFF); |
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} |
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void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf) |
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{ |
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unsigned int index; |
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u32 cfg; |
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if (dev->dd->max_dma_bufs == 1) |
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index = 0; |
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else |
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index = buf->index; |
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if (index == 0) |
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writel(buf->addr, dev->regs + FLITE_REG_CIOSA); |
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else |
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writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1)); |
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cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ); |
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cfg |= BIT(index); |
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writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); |
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} |
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void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index) |
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{ |
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u32 cfg; |
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if (dev->dd->max_dma_bufs == 1) |
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index = 0; |
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cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ); |
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cfg &= ~BIT(index); |
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writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); |
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} |
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/* Enable/disable output DMA, set output pixel size and offsets (composition) */ |
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void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f, |
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bool enable) |
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{ |
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u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); |
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if (!enable) { |
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cfg |= FLITE_REG_CIGCTRL_ODMA_DISABLE; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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return; |
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} |
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cfg &= ~FLITE_REG_CIGCTRL_ODMA_DISABLE; |
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writel(cfg, dev->regs + FLITE_REG_CIGCTRL); |
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flite_hw_set_out_order(dev, f); |
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flite_hw_set_dma_window(dev, f); |
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flite_hw_set_pack12(dev, 0); |
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} |
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void flite_hw_dump_regs(struct fimc_lite *dev, const char *label) |
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{ |
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struct { |
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u32 offset; |
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const char * const name; |
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} registers[] = { |
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{ 0x00, "CISRCSIZE" }, |
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{ 0x04, "CIGCTRL" }, |
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{ 0x08, "CIIMGCPT" }, |
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{ 0x0c, "CICPTSEQ" }, |
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{ 0x10, "CIWDOFST" }, |
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{ 0x14, "CIWDOFST2" }, |
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{ 0x18, "CIODMAFMT" }, |
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{ 0x20, "CIOCAN" }, |
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{ 0x24, "CIOOFF" }, |
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{ 0x30, "CIOSA" }, |
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{ 0x40, "CISTATUS" }, |
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{ 0x44, "CISTATUS2" }, |
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{ 0xf0, "CITHOLD" }, |
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{ 0xfc, "CIGENERAL" }, |
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}; |
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u32 i; |
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v4l2_info(&dev->subdev, "--- %s ---\n", label); |
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for (i = 0; i < ARRAY_SIZE(registers); i++) { |
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u32 cfg = readl(dev->regs + registers[i].offset); |
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v4l2_info(&dev->subdev, "%9s: 0x%08x\n", |
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registers[i].name, cfg); |
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} |
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}
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