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197 lines
4.8 KiB
197 lines
4.8 KiB
/* |
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* Copyright (C) 2016 Marvell |
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* |
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* Yehuda Yitschak <[email protected]> |
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* Thomas Petazzoni <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/of_irq.h> |
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#include <linux/platform_device.h> |
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#define PIC_CAUSE 0x0 |
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#define PIC_MASK 0x4 |
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#define PIC_MAX_IRQS 32 |
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#define PIC_MAX_IRQ_MASK ((1UL << PIC_MAX_IRQS) - 1) |
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struct mvebu_pic { |
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void __iomem *base; |
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u32 parent_irq; |
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struct irq_domain *domain; |
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struct irq_chip irq_chip; |
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}; |
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static void mvebu_pic_reset(struct mvebu_pic *pic) |
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{ |
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/* ACK and mask all interrupts */ |
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writel(0, pic->base + PIC_MASK); |
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writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); |
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} |
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static void mvebu_pic_eoi_irq(struct irq_data *d) |
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{ |
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struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); |
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writel(1 << d->hwirq, pic->base + PIC_CAUSE); |
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} |
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static void mvebu_pic_mask_irq(struct irq_data *d) |
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{ |
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struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); |
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u32 reg; |
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reg = readl(pic->base + PIC_MASK); |
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reg |= (1 << d->hwirq); |
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writel(reg, pic->base + PIC_MASK); |
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} |
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static void mvebu_pic_unmask_irq(struct irq_data *d) |
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{ |
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struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); |
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u32 reg; |
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reg = readl(pic->base + PIC_MASK); |
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reg &= ~(1 << d->hwirq); |
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writel(reg, pic->base + PIC_MASK); |
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} |
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static int mvebu_pic_irq_map(struct irq_domain *domain, unsigned int virq, |
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irq_hw_number_t hwirq) |
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{ |
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struct mvebu_pic *pic = domain->host_data; |
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irq_set_percpu_devid(virq); |
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irq_set_chip_data(virq, pic); |
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irq_set_chip_and_handler(virq, &pic->irq_chip, |
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handle_percpu_devid_irq); |
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irq_set_status_flags(virq, IRQ_LEVEL); |
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irq_set_probe(virq); |
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return 0; |
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} |
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static const struct irq_domain_ops mvebu_pic_domain_ops = { |
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.map = mvebu_pic_irq_map, |
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.xlate = irq_domain_xlate_onecell, |
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}; |
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static void mvebu_pic_handle_cascade_irq(struct irq_desc *desc) |
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{ |
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struct mvebu_pic *pic = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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unsigned long irqmap, irqn; |
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unsigned int cascade_irq; |
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irqmap = readl_relaxed(pic->base + PIC_CAUSE); |
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chained_irq_enter(chip, desc); |
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for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { |
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cascade_irq = irq_find_mapping(pic->domain, irqn); |
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generic_handle_irq(cascade_irq); |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static void mvebu_pic_enable_percpu_irq(void *data) |
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{ |
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struct mvebu_pic *pic = data; |
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mvebu_pic_reset(pic); |
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enable_percpu_irq(pic->parent_irq, IRQ_TYPE_NONE); |
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} |
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static void mvebu_pic_disable_percpu_irq(void *data) |
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{ |
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struct mvebu_pic *pic = data; |
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disable_percpu_irq(pic->parent_irq); |
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} |
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static int mvebu_pic_probe(struct platform_device *pdev) |
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{ |
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struct device_node *node = pdev->dev.of_node; |
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struct mvebu_pic *pic; |
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struct irq_chip *irq_chip; |
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struct resource *res; |
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pic = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pic), GFP_KERNEL); |
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if (!pic) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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pic->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(pic->base)) |
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return PTR_ERR(pic->base); |
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irq_chip = &pic->irq_chip; |
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irq_chip->name = dev_name(&pdev->dev); |
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irq_chip->irq_mask = mvebu_pic_mask_irq; |
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irq_chip->irq_unmask = mvebu_pic_unmask_irq; |
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irq_chip->irq_eoi = mvebu_pic_eoi_irq; |
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pic->parent_irq = irq_of_parse_and_map(node, 0); |
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if (pic->parent_irq <= 0) { |
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dev_err(&pdev->dev, "Failed to parse parent interrupt\n"); |
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return -EINVAL; |
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} |
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pic->domain = irq_domain_add_linear(node, PIC_MAX_IRQS, |
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&mvebu_pic_domain_ops, pic); |
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if (!pic->domain) { |
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dev_err(&pdev->dev, "Failed to allocate irq domain\n"); |
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return -ENOMEM; |
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} |
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irq_set_chained_handler(pic->parent_irq, mvebu_pic_handle_cascade_irq); |
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irq_set_handler_data(pic->parent_irq, pic); |
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on_each_cpu(mvebu_pic_enable_percpu_irq, pic, 1); |
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platform_set_drvdata(pdev, pic); |
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return 0; |
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} |
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static int mvebu_pic_remove(struct platform_device *pdev) |
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{ |
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struct mvebu_pic *pic = platform_get_drvdata(pdev); |
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on_each_cpu(mvebu_pic_disable_percpu_irq, pic, 1); |
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irq_domain_remove(pic->domain); |
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return 0; |
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} |
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static const struct of_device_id mvebu_pic_of_match[] = { |
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{ .compatible = "marvell,armada-8k-pic", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mvebu_pic_of_match); |
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static struct platform_driver mvebu_pic_driver = { |
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.probe = mvebu_pic_probe, |
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.remove = mvebu_pic_remove, |
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.driver = { |
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.name = "mvebu-pic", |
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.of_match_table = mvebu_pic_of_match, |
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}, |
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}; |
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module_platform_driver(mvebu_pic_driver); |
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MODULE_AUTHOR("Yehuda Yitschak <[email protected]>"); |
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MODULE_AUTHOR("Thomas Petazzoni <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:mvebu_pic"); |
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