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1254 lines
33 KiB
1254 lines
33 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* CPU-agnostic ARM page table allocator. |
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* |
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* Copyright (C) 2014 ARM Limited |
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* |
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* Author: Will Deacon <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt |
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|
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#include <linux/atomic.h> |
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#include <linux/bitops.h> |
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#include <linux/io-pgtable.h> |
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#include <linux/kernel.h> |
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#include <linux/sizes.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <linux/dma-mapping.h> |
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|
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#include <asm/barrier.h> |
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#include "io-pgtable-arm.h" |
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|
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#define ARM_LPAE_MAX_ADDR_BITS 52 |
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#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16 |
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#define ARM_LPAE_MAX_LEVELS 4 |
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|
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/* Struct accessors */ |
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#define io_pgtable_to_data(x) \ |
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container_of((x), struct arm_lpae_io_pgtable, iop) |
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|
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#define io_pgtable_ops_to_data(x) \ |
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io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) |
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|
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/* |
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* Calculate the right shift amount to get to the portion describing level l |
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* in a virtual address mapped by the pagetable in d. |
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*/ |
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#define ARM_LPAE_LVL_SHIFT(l,d) \ |
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(((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level) + \ |
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ilog2(sizeof(arm_lpae_iopte))) |
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|
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#define ARM_LPAE_GRANULE(d) \ |
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(sizeof(arm_lpae_iopte) << (d)->bits_per_level) |
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#define ARM_LPAE_PGD_SIZE(d) \ |
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(sizeof(arm_lpae_iopte) << (d)->pgd_bits) |
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|
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/* |
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* Calculate the index at level l used to map virtual address a using the |
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* pagetable in d. |
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*/ |
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#define ARM_LPAE_PGD_IDX(l,d) \ |
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((l) == (d)->start_level ? (d)->pgd_bits - (d)->bits_per_level : 0) |
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|
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#define ARM_LPAE_LVL_IDX(a,l,d) \ |
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(((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \ |
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((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1)) |
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|
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/* Calculate the block/page mapping size at level l for pagetable in d. */ |
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#define ARM_LPAE_BLOCK_SIZE(l,d) (1ULL << ARM_LPAE_LVL_SHIFT(l,d)) |
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|
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/* Page table bits */ |
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#define ARM_LPAE_PTE_TYPE_SHIFT 0 |
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#define ARM_LPAE_PTE_TYPE_MASK 0x3 |
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|
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#define ARM_LPAE_PTE_TYPE_BLOCK 1 |
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#define ARM_LPAE_PTE_TYPE_TABLE 3 |
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#define ARM_LPAE_PTE_TYPE_PAGE 3 |
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|
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#define ARM_LPAE_PTE_ADDR_MASK GENMASK_ULL(47,12) |
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|
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#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) |
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#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) |
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#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) |
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#define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) |
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#define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8) |
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#define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8) |
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#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5) |
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#define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0) |
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|
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#define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2) |
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/* Ignore the contiguous bit for block splitting */ |
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#define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52) |
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#define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \ |
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ARM_LPAE_PTE_ATTR_HI_MASK) |
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/* Software bit for solving coherency races */ |
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#define ARM_LPAE_PTE_SW_SYNC (((arm_lpae_iopte)1) << 55) |
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|
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/* Stage-1 PTE */ |
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#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6) |
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#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6) |
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#define ARM_LPAE_PTE_ATTRINDX_SHIFT 2 |
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#define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11) |
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|
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/* Stage-2 PTE */ |
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#define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6) |
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#define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6) |
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#define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6) |
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#define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2) |
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#define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2) |
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#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2) |
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|
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/* Register bits */ |
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#define ARM_LPAE_VTCR_SL0_MASK 0x3 |
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|
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#define ARM_LPAE_TCR_T0SZ_SHIFT 0 |
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|
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#define ARM_LPAE_VTCR_PS_SHIFT 16 |
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#define ARM_LPAE_VTCR_PS_MASK 0x7 |
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|
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#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3) |
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#define ARM_LPAE_MAIR_ATTR_MASK 0xff |
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#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04 |
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#define ARM_LPAE_MAIR_ATTR_NC 0x44 |
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#define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4 |
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#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff |
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#define ARM_LPAE_MAIR_ATTR_IDX_NC 0 |
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#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1 |
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#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2 |
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#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3 |
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|
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#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0) |
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#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2) |
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#define ARM_MALI_LPAE_TTBR_SHARE_OUTER BIT(4) |
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|
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#define ARM_MALI_LPAE_MEMATTR_IMP_DEF 0x88ULL |
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#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL |
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|
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/* IOPTE accessors */ |
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#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d)) |
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|
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#define iopte_type(pte) \ |
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(((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK) |
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#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK) |
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struct arm_lpae_io_pgtable { |
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struct io_pgtable iop; |
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|
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int pgd_bits; |
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int start_level; |
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int bits_per_level; |
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|
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void *pgd; |
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}; |
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typedef u64 arm_lpae_iopte; |
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static inline bool iopte_leaf(arm_lpae_iopte pte, int lvl, |
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enum io_pgtable_fmt fmt) |
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{ |
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if (lvl == (ARM_LPAE_MAX_LEVELS - 1) && fmt != ARM_MALI_LPAE) |
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return iopte_type(pte) == ARM_LPAE_PTE_TYPE_PAGE; |
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|
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return iopte_type(pte) == ARM_LPAE_PTE_TYPE_BLOCK; |
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} |
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static arm_lpae_iopte paddr_to_iopte(phys_addr_t paddr, |
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struct arm_lpae_io_pgtable *data) |
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{ |
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arm_lpae_iopte pte = paddr; |
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|
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/* Of the bits which overlap, either 51:48 or 15:12 are always RES0 */ |
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return (pte | (pte >> (48 - 12))) & ARM_LPAE_PTE_ADDR_MASK; |
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} |
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static phys_addr_t iopte_to_paddr(arm_lpae_iopte pte, |
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struct arm_lpae_io_pgtable *data) |
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{ |
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u64 paddr = pte & ARM_LPAE_PTE_ADDR_MASK; |
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|
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if (ARM_LPAE_GRANULE(data) < SZ_64K) |
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return paddr; |
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|
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/* Rotate the packed high-order bits back to the top */ |
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return (paddr | (paddr << (48 - 12))) & (ARM_LPAE_PTE_ADDR_MASK << 4); |
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} |
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static bool selftest_running = false; |
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static dma_addr_t __arm_lpae_dma_addr(void *pages) |
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{ |
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return (dma_addr_t)virt_to_phys(pages); |
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} |
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static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, |
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struct io_pgtable_cfg *cfg) |
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{ |
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struct device *dev = cfg->iommu_dev; |
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int order = get_order(size); |
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struct page *p; |
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dma_addr_t dma; |
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void *pages; |
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VM_BUG_ON((gfp & __GFP_HIGHMEM)); |
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p = alloc_pages_node(dev ? dev_to_node(dev) : NUMA_NO_NODE, |
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gfp | __GFP_ZERO, order); |
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if (!p) |
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return NULL; |
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pages = page_address(p); |
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if (!cfg->coherent_walk) { |
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dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE); |
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if (dma_mapping_error(dev, dma)) |
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goto out_free; |
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/* |
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* We depend on the IOMMU being able to work with any physical |
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* address directly, so if the DMA layer suggests otherwise by |
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* translating or truncating them, that bodes very badly... |
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*/ |
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if (dma != virt_to_phys(pages)) |
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goto out_unmap; |
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} |
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return pages; |
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out_unmap: |
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dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"); |
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dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); |
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out_free: |
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__free_pages(p, order); |
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return NULL; |
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} |
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static void __arm_lpae_free_pages(void *pages, size_t size, |
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struct io_pgtable_cfg *cfg) |
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{ |
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if (!cfg->coherent_walk) |
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dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), |
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size, DMA_TO_DEVICE); |
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free_pages((unsigned long)pages, get_order(size)); |
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} |
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static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, |
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struct io_pgtable_cfg *cfg) |
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{ |
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dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep), |
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sizeof(*ptep), DMA_TO_DEVICE); |
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} |
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static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte, |
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struct io_pgtable_cfg *cfg) |
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{ |
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*ptep = pte; |
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if (!cfg->coherent_walk) |
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__arm_lpae_sync_pte(ptep, cfg); |
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} |
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static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, |
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struct iommu_iotlb_gather *gather, |
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unsigned long iova, size_t size, int lvl, |
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arm_lpae_iopte *ptep); |
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static void __arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, |
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phys_addr_t paddr, arm_lpae_iopte prot, |
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int lvl, arm_lpae_iopte *ptep) |
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{ |
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arm_lpae_iopte pte = prot; |
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if (data->iop.fmt != ARM_MALI_LPAE && lvl == ARM_LPAE_MAX_LEVELS - 1) |
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pte |= ARM_LPAE_PTE_TYPE_PAGE; |
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else |
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pte |= ARM_LPAE_PTE_TYPE_BLOCK; |
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pte |= paddr_to_iopte(paddr, data); |
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__arm_lpae_set_pte(ptep, pte, &data->iop.cfg); |
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} |
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static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, |
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unsigned long iova, phys_addr_t paddr, |
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arm_lpae_iopte prot, int lvl, |
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arm_lpae_iopte *ptep) |
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{ |
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arm_lpae_iopte pte = *ptep; |
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if (iopte_leaf(pte, lvl, data->iop.fmt)) { |
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/* We require an unmap first */ |
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WARN_ON(!selftest_running); |
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return -EEXIST; |
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} else if (iopte_type(pte) == ARM_LPAE_PTE_TYPE_TABLE) { |
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/* |
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* We need to unmap and free the old table before |
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* overwriting it with a block entry. |
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*/ |
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arm_lpae_iopte *tblp; |
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size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data); |
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tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data); |
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if (__arm_lpae_unmap(data, NULL, iova, sz, lvl, tblp) != sz) { |
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WARN_ON(1); |
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return -EINVAL; |
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} |
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} |
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__arm_lpae_init_pte(data, paddr, prot, lvl, ptep); |
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return 0; |
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} |
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static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table, |
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arm_lpae_iopte *ptep, |
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arm_lpae_iopte curr, |
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struct io_pgtable_cfg *cfg) |
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{ |
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arm_lpae_iopte old, new; |
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new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE; |
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) |
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new |= ARM_LPAE_PTE_NSTABLE; |
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|
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/* |
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* Ensure the table itself is visible before its PTE can be. |
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* Whilst we could get away with cmpxchg64_release below, this |
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* doesn't have any ordering semantics when !CONFIG_SMP. |
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*/ |
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dma_wmb(); |
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old = cmpxchg64_relaxed(ptep, curr, new); |
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if (cfg->coherent_walk || (old & ARM_LPAE_PTE_SW_SYNC)) |
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return old; |
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|
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/* Even if it's not ours, there's no point waiting; just kick it */ |
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__arm_lpae_sync_pte(ptep, cfg); |
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if (old == curr) |
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WRITE_ONCE(*ptep, new | ARM_LPAE_PTE_SW_SYNC); |
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return old; |
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} |
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static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, |
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phys_addr_t paddr, size_t size, arm_lpae_iopte prot, |
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int lvl, arm_lpae_iopte *ptep, gfp_t gfp) |
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{ |
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arm_lpae_iopte *cptep, pte; |
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size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data); |
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size_t tblsz = ARM_LPAE_GRANULE(data); |
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struct io_pgtable_cfg *cfg = &data->iop.cfg; |
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/* Find our entry at the current level */ |
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ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
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|
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/* If we can install a leaf entry at this level, then do so */ |
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if (size == block_size) |
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return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep); |
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|
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/* We can't allocate tables at the final level */ |
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if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)) |
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return -EINVAL; |
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|
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/* Grab a pointer to the next level */ |
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pte = READ_ONCE(*ptep); |
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if (!pte) { |
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cptep = __arm_lpae_alloc_pages(tblsz, gfp, cfg); |
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if (!cptep) |
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return -ENOMEM; |
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|
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pte = arm_lpae_install_table(cptep, ptep, 0, cfg); |
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if (pte) |
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__arm_lpae_free_pages(cptep, tblsz, cfg); |
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} else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) { |
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__arm_lpae_sync_pte(ptep, cfg); |
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} |
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|
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if (pte && !iopte_leaf(pte, lvl, data->iop.fmt)) { |
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cptep = iopte_deref(pte, data); |
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} else if (pte) { |
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/* We require an unmap first */ |
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WARN_ON(!selftest_running); |
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return -EEXIST; |
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} |
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|
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/* Rinse, repeat */ |
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return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep, gfp); |
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} |
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static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, |
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int prot) |
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{ |
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arm_lpae_iopte pte; |
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|
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if (data->iop.fmt == ARM_64_LPAE_S1 || |
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data->iop.fmt == ARM_32_LPAE_S1) { |
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pte = ARM_LPAE_PTE_nG; |
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if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
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pte |= ARM_LPAE_PTE_AP_RDONLY; |
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if (!(prot & IOMMU_PRIV)) |
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pte |= ARM_LPAE_PTE_AP_UNPRIV; |
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} else { |
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pte = ARM_LPAE_PTE_HAP_FAULT; |
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if (prot & IOMMU_READ) |
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pte |= ARM_LPAE_PTE_HAP_READ; |
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if (prot & IOMMU_WRITE) |
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pte |= ARM_LPAE_PTE_HAP_WRITE; |
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} |
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|
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/* |
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* Note that this logic is structured to accommodate Mali LPAE |
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* having stage-1-like attributes but stage-2-like permissions. |
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*/ |
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if (data->iop.fmt == ARM_64_LPAE_S2 || |
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data->iop.fmt == ARM_32_LPAE_S2) { |
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if (prot & IOMMU_MMIO) |
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pte |= ARM_LPAE_PTE_MEMATTR_DEV; |
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else if (prot & IOMMU_CACHE) |
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pte |= ARM_LPAE_PTE_MEMATTR_OIWB; |
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else |
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pte |= ARM_LPAE_PTE_MEMATTR_NC; |
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} else { |
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if (prot & IOMMU_MMIO) |
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV |
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT); |
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else if (prot & IOMMU_CACHE) |
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pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE |
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<< ARM_LPAE_PTE_ATTRINDX_SHIFT); |
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} |
|
|
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/* |
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* Also Mali has its own notions of shareability wherein its Inner |
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* domain covers the cores within the GPU, and its Outer domain is |
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* "outside the GPU" (i.e. either the Inner or System domain in CPU |
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* terms, depending on coherency). |
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*/ |
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if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE) |
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pte |= ARM_LPAE_PTE_SH_IS; |
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else |
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pte |= ARM_LPAE_PTE_SH_OS; |
|
|
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if (prot & IOMMU_NOEXEC) |
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pte |= ARM_LPAE_PTE_XN; |
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|
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if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_NS) |
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pte |= ARM_LPAE_PTE_NS; |
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|
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if (data->iop.fmt != ARM_MALI_LPAE) |
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pte |= ARM_LPAE_PTE_AF; |
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|
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return pte; |
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} |
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|
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static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova, |
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phys_addr_t paddr, size_t size, int iommu_prot, gfp_t gfp) |
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{ |
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struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); |
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struct io_pgtable_cfg *cfg = &data->iop.cfg; |
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arm_lpae_iopte *ptep = data->pgd; |
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int ret, lvl = data->start_level; |
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arm_lpae_iopte prot; |
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long iaext = (s64)iova >> cfg->ias; |
|
|
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if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) |
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return -EINVAL; |
|
|
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) |
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iaext = ~iaext; |
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if (WARN_ON(iaext || paddr >> cfg->oas)) |
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return -ERANGE; |
|
|
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/* If no access, then nothing to do */ |
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if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) |
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return 0; |
|
|
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prot = arm_lpae_prot_to_pte(data, iommu_prot); |
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ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep, gfp); |
|
/* |
|
* Synchronise all PTE updates for the new mapping before there's |
|
* a chance for anything to kick off a table walk for the new iova. |
|
*/ |
|
wmb(); |
|
|
|
return ret; |
|
} |
|
|
|
static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl, |
|
arm_lpae_iopte *ptep) |
|
{ |
|
arm_lpae_iopte *start, *end; |
|
unsigned long table_size; |
|
|
|
if (lvl == data->start_level) |
|
table_size = ARM_LPAE_PGD_SIZE(data); |
|
else |
|
table_size = ARM_LPAE_GRANULE(data); |
|
|
|
start = ptep; |
|
|
|
/* Only leaf entries at the last level */ |
|
if (lvl == ARM_LPAE_MAX_LEVELS - 1) |
|
end = ptep; |
|
else |
|
end = (void *)ptep + table_size; |
|
|
|
while (ptep != end) { |
|
arm_lpae_iopte pte = *ptep++; |
|
|
|
if (!pte || iopte_leaf(pte, lvl, data->iop.fmt)) |
|
continue; |
|
|
|
__arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data)); |
|
} |
|
|
|
__arm_lpae_free_pages(start, table_size, &data->iop.cfg); |
|
} |
|
|
|
static void arm_lpae_free_pgtable(struct io_pgtable *iop) |
|
{ |
|
struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop); |
|
|
|
__arm_lpae_free_pgtable(data, data->start_level, data->pgd); |
|
kfree(data); |
|
} |
|
|
|
static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, |
|
struct iommu_iotlb_gather *gather, |
|
unsigned long iova, size_t size, |
|
arm_lpae_iopte blk_pte, int lvl, |
|
arm_lpae_iopte *ptep) |
|
{ |
|
struct io_pgtable_cfg *cfg = &data->iop.cfg; |
|
arm_lpae_iopte pte, *tablep; |
|
phys_addr_t blk_paddr; |
|
size_t tablesz = ARM_LPAE_GRANULE(data); |
|
size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data); |
|
int i, unmap_idx = -1; |
|
|
|
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) |
|
return 0; |
|
|
|
tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg); |
|
if (!tablep) |
|
return 0; /* Bytes unmapped */ |
|
|
|
if (size == split_sz) |
|
unmap_idx = ARM_LPAE_LVL_IDX(iova, lvl, data); |
|
|
|
blk_paddr = iopte_to_paddr(blk_pte, data); |
|
pte = iopte_prot(blk_pte); |
|
|
|
for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) { |
|
/* Unmap! */ |
|
if (i == unmap_idx) |
|
continue; |
|
|
|
__arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]); |
|
} |
|
|
|
pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg); |
|
if (pte != blk_pte) { |
|
__arm_lpae_free_pages(tablep, tablesz, cfg); |
|
/* |
|
* We may race against someone unmapping another part of this |
|
* block, but anything else is invalid. We can't misinterpret |
|
* a page entry here since we're never at the last level. |
|
*/ |
|
if (iopte_type(pte) != ARM_LPAE_PTE_TYPE_TABLE) |
|
return 0; |
|
|
|
tablep = iopte_deref(pte, data); |
|
} else if (unmap_idx >= 0) { |
|
io_pgtable_tlb_add_page(&data->iop, gather, iova, size); |
|
return size; |
|
} |
|
|
|
return __arm_lpae_unmap(data, gather, iova, size, lvl, tablep); |
|
} |
|
|
|
static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, |
|
struct iommu_iotlb_gather *gather, |
|
unsigned long iova, size_t size, int lvl, |
|
arm_lpae_iopte *ptep) |
|
{ |
|
arm_lpae_iopte pte; |
|
struct io_pgtable *iop = &data->iop; |
|
|
|
/* Something went horribly wrong and we ran out of page table */ |
|
if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) |
|
return 0; |
|
|
|
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
|
pte = READ_ONCE(*ptep); |
|
if (WARN_ON(!pte)) |
|
return 0; |
|
|
|
/* If the size matches this level, we're in the right place */ |
|
if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { |
|
__arm_lpae_set_pte(ptep, 0, &iop->cfg); |
|
|
|
if (!iopte_leaf(pte, lvl, iop->fmt)) { |
|
/* Also flush any partial walks */ |
|
io_pgtable_tlb_flush_walk(iop, iova, size, |
|
ARM_LPAE_GRANULE(data)); |
|
ptep = iopte_deref(pte, data); |
|
__arm_lpae_free_pgtable(data, lvl + 1, ptep); |
|
} else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) { |
|
/* |
|
* Order the PTE update against queueing the IOVA, to |
|
* guarantee that a flush callback from a different CPU |
|
* has observed it before the TLBIALL can be issued. |
|
*/ |
|
smp_wmb(); |
|
} else { |
|
io_pgtable_tlb_add_page(iop, gather, iova, size); |
|
} |
|
|
|
return size; |
|
} else if (iopte_leaf(pte, lvl, iop->fmt)) { |
|
/* |
|
* Insert a table at the next level to map the old region, |
|
* minus the part we want to unmap |
|
*/ |
|
return arm_lpae_split_blk_unmap(data, gather, iova, size, pte, |
|
lvl + 1, ptep); |
|
} |
|
|
|
/* Keep on walkin' */ |
|
ptep = iopte_deref(pte, data); |
|
return __arm_lpae_unmap(data, gather, iova, size, lvl + 1, ptep); |
|
} |
|
|
|
static size_t arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova, |
|
size_t size, struct iommu_iotlb_gather *gather) |
|
{ |
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); |
|
struct io_pgtable_cfg *cfg = &data->iop.cfg; |
|
arm_lpae_iopte *ptep = data->pgd; |
|
long iaext = (s64)iova >> cfg->ias; |
|
|
|
if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) |
|
return 0; |
|
|
|
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) |
|
iaext = ~iaext; |
|
if (WARN_ON(iaext)) |
|
return 0; |
|
|
|
return __arm_lpae_unmap(data, gather, iova, size, data->start_level, ptep); |
|
} |
|
|
|
static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, |
|
unsigned long iova) |
|
{ |
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); |
|
arm_lpae_iopte pte, *ptep = data->pgd; |
|
int lvl = data->start_level; |
|
|
|
do { |
|
/* Valid IOPTE pointer? */ |
|
if (!ptep) |
|
return 0; |
|
|
|
/* Grab the IOPTE we're interested in */ |
|
ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); |
|
pte = READ_ONCE(*ptep); |
|
|
|
/* Valid entry? */ |
|
if (!pte) |
|
return 0; |
|
|
|
/* Leaf entry? */ |
|
if (iopte_leaf(pte, lvl, data->iop.fmt)) |
|
goto found_translation; |
|
|
|
/* Take it to the next level */ |
|
ptep = iopte_deref(pte, data); |
|
} while (++lvl < ARM_LPAE_MAX_LEVELS); |
|
|
|
/* Ran out of page tables to walk */ |
|
return 0; |
|
|
|
found_translation: |
|
iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1); |
|
return iopte_to_paddr(pte, data) | iova; |
|
} |
|
|
|
static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) |
|
{ |
|
unsigned long granule, page_sizes; |
|
unsigned int max_addr_bits = 48; |
|
|
|
/* |
|
* We need to restrict the supported page sizes to match the |
|
* translation regime for a particular granule. Aim to match |
|
* the CPU page size if possible, otherwise prefer smaller sizes. |
|
* While we're at it, restrict the block sizes to match the |
|
* chosen granule. |
|
*/ |
|
if (cfg->pgsize_bitmap & PAGE_SIZE) |
|
granule = PAGE_SIZE; |
|
else if (cfg->pgsize_bitmap & ~PAGE_MASK) |
|
granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK); |
|
else if (cfg->pgsize_bitmap & PAGE_MASK) |
|
granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK); |
|
else |
|
granule = 0; |
|
|
|
switch (granule) { |
|
case SZ_4K: |
|
page_sizes = (SZ_4K | SZ_2M | SZ_1G); |
|
break; |
|
case SZ_16K: |
|
page_sizes = (SZ_16K | SZ_32M); |
|
break; |
|
case SZ_64K: |
|
max_addr_bits = 52; |
|
page_sizes = (SZ_64K | SZ_512M); |
|
if (cfg->oas > 48) |
|
page_sizes |= 1ULL << 42; /* 4TB */ |
|
break; |
|
default: |
|
page_sizes = 0; |
|
} |
|
|
|
cfg->pgsize_bitmap &= page_sizes; |
|
cfg->ias = min(cfg->ias, max_addr_bits); |
|
cfg->oas = min(cfg->oas, max_addr_bits); |
|
} |
|
|
|
static struct arm_lpae_io_pgtable * |
|
arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) |
|
{ |
|
struct arm_lpae_io_pgtable *data; |
|
int levels, va_bits, pg_shift; |
|
|
|
arm_lpae_restrict_pgsizes(cfg); |
|
|
|
if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K))) |
|
return NULL; |
|
|
|
if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS) |
|
return NULL; |
|
|
|
if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS) |
|
return NULL; |
|
|
|
data = kmalloc(sizeof(*data), GFP_KERNEL); |
|
if (!data) |
|
return NULL; |
|
|
|
pg_shift = __ffs(cfg->pgsize_bitmap); |
|
data->bits_per_level = pg_shift - ilog2(sizeof(arm_lpae_iopte)); |
|
|
|
va_bits = cfg->ias - pg_shift; |
|
levels = DIV_ROUND_UP(va_bits, data->bits_per_level); |
|
data->start_level = ARM_LPAE_MAX_LEVELS - levels; |
|
|
|
/* Calculate the actual size of our pgd (without concatenation) */ |
|
data->pgd_bits = va_bits - (data->bits_per_level * (levels - 1)); |
|
|
|
data->iop.ops = (struct io_pgtable_ops) { |
|
.map = arm_lpae_map, |
|
.unmap = arm_lpae_unmap, |
|
.iova_to_phys = arm_lpae_iova_to_phys, |
|
}; |
|
|
|
return data; |
|
} |
|
|
|
static struct io_pgtable * |
|
arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) |
|
{ |
|
u64 reg; |
|
struct arm_lpae_io_pgtable *data; |
|
typeof(&cfg->arm_lpae_s1_cfg.tcr) tcr = &cfg->arm_lpae_s1_cfg.tcr; |
|
bool tg1; |
|
|
|
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | |
|
IO_PGTABLE_QUIRK_NON_STRICT | |
|
IO_PGTABLE_QUIRK_ARM_TTBR1 | |
|
IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)) |
|
return NULL; |
|
|
|
data = arm_lpae_alloc_pgtable(cfg); |
|
if (!data) |
|
return NULL; |
|
|
|
/* TCR */ |
|
if (cfg->coherent_walk) { |
|
tcr->sh = ARM_LPAE_TCR_SH_IS; |
|
tcr->irgn = ARM_LPAE_TCR_RGN_WBWA; |
|
tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; |
|
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA) |
|
goto out_free_data; |
|
} else { |
|
tcr->sh = ARM_LPAE_TCR_SH_OS; |
|
tcr->irgn = ARM_LPAE_TCR_RGN_NC; |
|
if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)) |
|
tcr->orgn = ARM_LPAE_TCR_RGN_NC; |
|
else |
|
tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; |
|
} |
|
|
|
tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1; |
|
switch (ARM_LPAE_GRANULE(data)) { |
|
case SZ_4K: |
|
tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_4K : ARM_LPAE_TCR_TG0_4K; |
|
break; |
|
case SZ_16K: |
|
tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_16K : ARM_LPAE_TCR_TG0_16K; |
|
break; |
|
case SZ_64K: |
|
tcr->tg = tg1 ? ARM_LPAE_TCR_TG1_64K : ARM_LPAE_TCR_TG0_64K; |
|
break; |
|
} |
|
|
|
switch (cfg->oas) { |
|
case 32: |
|
tcr->ips = ARM_LPAE_TCR_PS_32_BIT; |
|
break; |
|
case 36: |
|
tcr->ips = ARM_LPAE_TCR_PS_36_BIT; |
|
break; |
|
case 40: |
|
tcr->ips = ARM_LPAE_TCR_PS_40_BIT; |
|
break; |
|
case 42: |
|
tcr->ips = ARM_LPAE_TCR_PS_42_BIT; |
|
break; |
|
case 44: |
|
tcr->ips = ARM_LPAE_TCR_PS_44_BIT; |
|
break; |
|
case 48: |
|
tcr->ips = ARM_LPAE_TCR_PS_48_BIT; |
|
break; |
|
case 52: |
|
tcr->ips = ARM_LPAE_TCR_PS_52_BIT; |
|
break; |
|
default: |
|
goto out_free_data; |
|
} |
|
|
|
tcr->tsz = 64ULL - cfg->ias; |
|
|
|
/* MAIRs */ |
|
reg = (ARM_LPAE_MAIR_ATTR_NC |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) | |
|
(ARM_LPAE_MAIR_ATTR_WBRWA |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) | |
|
(ARM_LPAE_MAIR_ATTR_DEVICE |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) | |
|
(ARM_LPAE_MAIR_ATTR_INC_OWBRWA |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)); |
|
|
|
cfg->arm_lpae_s1_cfg.mair = reg; |
|
|
|
/* Looking good; allocate a pgd */ |
|
data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), |
|
GFP_KERNEL, cfg); |
|
if (!data->pgd) |
|
goto out_free_data; |
|
|
|
/* Ensure the empty pgd is visible before any actual TTBR write */ |
|
wmb(); |
|
|
|
/* TTBR */ |
|
cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); |
|
return &data->iop; |
|
|
|
out_free_data: |
|
kfree(data); |
|
return NULL; |
|
} |
|
|
|
static struct io_pgtable * |
|
arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) |
|
{ |
|
u64 sl; |
|
struct arm_lpae_io_pgtable *data; |
|
typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr; |
|
|
|
/* The NS quirk doesn't apply at stage 2 */ |
|
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT)) |
|
return NULL; |
|
|
|
data = arm_lpae_alloc_pgtable(cfg); |
|
if (!data) |
|
return NULL; |
|
|
|
/* |
|
* Concatenate PGDs at level 1 if possible in order to reduce |
|
* the depth of the stage-2 walk. |
|
*/ |
|
if (data->start_level == 0) { |
|
unsigned long pgd_pages; |
|
|
|
pgd_pages = ARM_LPAE_PGD_SIZE(data) / sizeof(arm_lpae_iopte); |
|
if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) { |
|
data->pgd_bits += data->bits_per_level; |
|
data->start_level++; |
|
} |
|
} |
|
|
|
/* VTCR */ |
|
if (cfg->coherent_walk) { |
|
vtcr->sh = ARM_LPAE_TCR_SH_IS; |
|
vtcr->irgn = ARM_LPAE_TCR_RGN_WBWA; |
|
vtcr->orgn = ARM_LPAE_TCR_RGN_WBWA; |
|
} else { |
|
vtcr->sh = ARM_LPAE_TCR_SH_OS; |
|
vtcr->irgn = ARM_LPAE_TCR_RGN_NC; |
|
vtcr->orgn = ARM_LPAE_TCR_RGN_NC; |
|
} |
|
|
|
sl = data->start_level; |
|
|
|
switch (ARM_LPAE_GRANULE(data)) { |
|
case SZ_4K: |
|
vtcr->tg = ARM_LPAE_TCR_TG0_4K; |
|
sl++; /* SL0 format is different for 4K granule size */ |
|
break; |
|
case SZ_16K: |
|
vtcr->tg = ARM_LPAE_TCR_TG0_16K; |
|
break; |
|
case SZ_64K: |
|
vtcr->tg = ARM_LPAE_TCR_TG0_64K; |
|
break; |
|
} |
|
|
|
switch (cfg->oas) { |
|
case 32: |
|
vtcr->ps = ARM_LPAE_TCR_PS_32_BIT; |
|
break; |
|
case 36: |
|
vtcr->ps = ARM_LPAE_TCR_PS_36_BIT; |
|
break; |
|
case 40: |
|
vtcr->ps = ARM_LPAE_TCR_PS_40_BIT; |
|
break; |
|
case 42: |
|
vtcr->ps = ARM_LPAE_TCR_PS_42_BIT; |
|
break; |
|
case 44: |
|
vtcr->ps = ARM_LPAE_TCR_PS_44_BIT; |
|
break; |
|
case 48: |
|
vtcr->ps = ARM_LPAE_TCR_PS_48_BIT; |
|
break; |
|
case 52: |
|
vtcr->ps = ARM_LPAE_TCR_PS_52_BIT; |
|
break; |
|
default: |
|
goto out_free_data; |
|
} |
|
|
|
vtcr->tsz = 64ULL - cfg->ias; |
|
vtcr->sl = ~sl & ARM_LPAE_VTCR_SL0_MASK; |
|
|
|
/* Allocate pgd pages */ |
|
data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), |
|
GFP_KERNEL, cfg); |
|
if (!data->pgd) |
|
goto out_free_data; |
|
|
|
/* Ensure the empty pgd is visible before any actual TTBR write */ |
|
wmb(); |
|
|
|
/* VTTBR */ |
|
cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd); |
|
return &data->iop; |
|
|
|
out_free_data: |
|
kfree(data); |
|
return NULL; |
|
} |
|
|
|
static struct io_pgtable * |
|
arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) |
|
{ |
|
if (cfg->ias > 32 || cfg->oas > 40) |
|
return NULL; |
|
|
|
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); |
|
return arm_64_lpae_alloc_pgtable_s1(cfg, cookie); |
|
} |
|
|
|
static struct io_pgtable * |
|
arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) |
|
{ |
|
if (cfg->ias > 40 || cfg->oas > 40) |
|
return NULL; |
|
|
|
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); |
|
return arm_64_lpae_alloc_pgtable_s2(cfg, cookie); |
|
} |
|
|
|
static struct io_pgtable * |
|
arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) |
|
{ |
|
struct arm_lpae_io_pgtable *data; |
|
|
|
/* No quirks for Mali (hopefully) */ |
|
if (cfg->quirks) |
|
return NULL; |
|
|
|
if (cfg->ias > 48 || cfg->oas > 40) |
|
return NULL; |
|
|
|
cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G); |
|
|
|
data = arm_lpae_alloc_pgtable(cfg); |
|
if (!data) |
|
return NULL; |
|
|
|
/* Mali seems to need a full 4-level table regardless of IAS */ |
|
if (data->start_level > 0) { |
|
data->start_level = 0; |
|
data->pgd_bits = 0; |
|
} |
|
/* |
|
* MEMATTR: Mali has no actual notion of a non-cacheable type, so the |
|
* best we can do is mimic the out-of-tree driver and hope that the |
|
* "implementation-defined caching policy" is good enough. Similarly, |
|
* we'll use it for the sake of a valid attribute for our 'device' |
|
* index, although callers should never request that in practice. |
|
*/ |
|
cfg->arm_mali_lpae_cfg.memattr = |
|
(ARM_MALI_LPAE_MEMATTR_IMP_DEF |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) | |
|
(ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) | |
|
(ARM_MALI_LPAE_MEMATTR_IMP_DEF |
|
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)); |
|
|
|
data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), GFP_KERNEL, |
|
cfg); |
|
if (!data->pgd) |
|
goto out_free_data; |
|
|
|
/* Ensure the empty pgd is visible before TRANSTAB can be written */ |
|
wmb(); |
|
|
|
cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) | |
|
ARM_MALI_LPAE_TTBR_READ_INNER | |
|
ARM_MALI_LPAE_TTBR_ADRMODE_TABLE; |
|
if (cfg->coherent_walk) |
|
cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER; |
|
|
|
return &data->iop; |
|
|
|
out_free_data: |
|
kfree(data); |
|
return NULL; |
|
} |
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = { |
|
.alloc = arm_64_lpae_alloc_pgtable_s1, |
|
.free = arm_lpae_free_pgtable, |
|
}; |
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = { |
|
.alloc = arm_64_lpae_alloc_pgtable_s2, |
|
.free = arm_lpae_free_pgtable, |
|
}; |
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = { |
|
.alloc = arm_32_lpae_alloc_pgtable_s1, |
|
.free = arm_lpae_free_pgtable, |
|
}; |
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = { |
|
.alloc = arm_32_lpae_alloc_pgtable_s2, |
|
.free = arm_lpae_free_pgtable, |
|
}; |
|
|
|
struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns = { |
|
.alloc = arm_mali_lpae_alloc_pgtable, |
|
.free = arm_lpae_free_pgtable, |
|
}; |
|
|
|
#ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST |
|
|
|
static struct io_pgtable_cfg *cfg_cookie __initdata; |
|
|
|
static void __init dummy_tlb_flush_all(void *cookie) |
|
{ |
|
WARN_ON(cookie != cfg_cookie); |
|
} |
|
|
|
static void __init dummy_tlb_flush(unsigned long iova, size_t size, |
|
size_t granule, void *cookie) |
|
{ |
|
WARN_ON(cookie != cfg_cookie); |
|
WARN_ON(!(size & cfg_cookie->pgsize_bitmap)); |
|
} |
|
|
|
static void __init dummy_tlb_add_page(struct iommu_iotlb_gather *gather, |
|
unsigned long iova, size_t granule, |
|
void *cookie) |
|
{ |
|
dummy_tlb_flush(iova, granule, granule, cookie); |
|
} |
|
|
|
static const struct iommu_flush_ops dummy_tlb_ops __initconst = { |
|
.tlb_flush_all = dummy_tlb_flush_all, |
|
.tlb_flush_walk = dummy_tlb_flush, |
|
.tlb_add_page = dummy_tlb_add_page, |
|
}; |
|
|
|
static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops) |
|
{ |
|
struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); |
|
struct io_pgtable_cfg *cfg = &data->iop.cfg; |
|
|
|
pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n", |
|
cfg->pgsize_bitmap, cfg->ias); |
|
pr_err("data: %d levels, 0x%zx pgd_size, %u pg_shift, %u bits_per_level, pgd @ %p\n", |
|
ARM_LPAE_MAX_LEVELS - data->start_level, ARM_LPAE_PGD_SIZE(data), |
|
ilog2(ARM_LPAE_GRANULE(data)), data->bits_per_level, data->pgd); |
|
} |
|
|
|
#define __FAIL(ops, i) ({ \ |
|
WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \ |
|
arm_lpae_dump_ops(ops); \ |
|
selftest_running = false; \ |
|
-EFAULT; \ |
|
}) |
|
|
|
static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg) |
|
{ |
|
static const enum io_pgtable_fmt fmts[] __initconst = { |
|
ARM_64_LPAE_S1, |
|
ARM_64_LPAE_S2, |
|
}; |
|
|
|
int i, j; |
|
unsigned long iova; |
|
size_t size; |
|
struct io_pgtable_ops *ops; |
|
|
|
selftest_running = true; |
|
|
|
for (i = 0; i < ARRAY_SIZE(fmts); ++i) { |
|
cfg_cookie = cfg; |
|
ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg); |
|
if (!ops) { |
|
pr_err("selftest: failed to allocate io pgtable ops\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
/* |
|
* Initial sanity checks. |
|
* Empty page tables shouldn't provide any translations. |
|
*/ |
|
if (ops->iova_to_phys(ops, 42)) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, SZ_1G + 42)) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, SZ_2G + 42)) |
|
return __FAIL(ops, i); |
|
|
|
/* |
|
* Distinct mappings of different granule sizes. |
|
*/ |
|
iova = 0; |
|
for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) { |
|
size = 1UL << j; |
|
|
|
if (ops->map(ops, iova, iova, size, IOMMU_READ | |
|
IOMMU_WRITE | |
|
IOMMU_NOEXEC | |
|
IOMMU_CACHE, GFP_KERNEL)) |
|
return __FAIL(ops, i); |
|
|
|
/* Overlapping mappings */ |
|
if (!ops->map(ops, iova, iova + size, size, |
|
IOMMU_READ | IOMMU_NOEXEC, GFP_KERNEL)) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) |
|
return __FAIL(ops, i); |
|
|
|
iova += SZ_1G; |
|
} |
|
|
|
/* Partial unmap */ |
|
size = 1UL << __ffs(cfg->pgsize_bitmap); |
|
if (ops->unmap(ops, SZ_1G + size, size, NULL) != size) |
|
return __FAIL(ops, i); |
|
|
|
/* Remap of partial unmap */ |
|
if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ, GFP_KERNEL)) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42)) |
|
return __FAIL(ops, i); |
|
|
|
/* Full unmap */ |
|
iova = 0; |
|
for_each_set_bit(j, &cfg->pgsize_bitmap, BITS_PER_LONG) { |
|
size = 1UL << j; |
|
|
|
if (ops->unmap(ops, iova, size, NULL) != size) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, iova + 42)) |
|
return __FAIL(ops, i); |
|
|
|
/* Remap full block */ |
|
if (ops->map(ops, iova, iova, size, IOMMU_WRITE, GFP_KERNEL)) |
|
return __FAIL(ops, i); |
|
|
|
if (ops->iova_to_phys(ops, iova + 42) != (iova + 42)) |
|
return __FAIL(ops, i); |
|
|
|
iova += SZ_1G; |
|
} |
|
|
|
free_io_pgtable_ops(ops); |
|
} |
|
|
|
selftest_running = false; |
|
return 0; |
|
} |
|
|
|
static int __init arm_lpae_do_selftests(void) |
|
{ |
|
static const unsigned long pgsize[] __initconst = { |
|
SZ_4K | SZ_2M | SZ_1G, |
|
SZ_16K | SZ_32M, |
|
SZ_64K | SZ_512M, |
|
}; |
|
|
|
static const unsigned int ias[] __initconst = { |
|
32, 36, 40, 42, 44, 48, |
|
}; |
|
|
|
int i, j, pass = 0, fail = 0; |
|
struct io_pgtable_cfg cfg = { |
|
.tlb = &dummy_tlb_ops, |
|
.oas = 48, |
|
.coherent_walk = true, |
|
}; |
|
|
|
for (i = 0; i < ARRAY_SIZE(pgsize); ++i) { |
|
for (j = 0; j < ARRAY_SIZE(ias); ++j) { |
|
cfg.pgsize_bitmap = pgsize[i]; |
|
cfg.ias = ias[j]; |
|
pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n", |
|
pgsize[i], ias[j]); |
|
if (arm_lpae_run_tests(&cfg)) |
|
fail++; |
|
else |
|
pass++; |
|
} |
|
} |
|
|
|
pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail); |
|
return fail ? -EFAULT : 0; |
|
} |
|
subsys_initcall(arm_lpae_do_selftests); |
|
#endif
|
|
|