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611 lines
18 KiB
611 lines
18 KiB
/******************************************************************************* |
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* |
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* Copyright (c) 2015-2016 Intel Corporation. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenFabrics.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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* |
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*******************************************************************************/ |
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#include "i40iw_status.h" |
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#include "i40iw_osdep.h" |
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#include "i40iw_register.h" |
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#include "i40iw_hmc.h" |
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#include "i40iw_d.h" |
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#include "i40iw_type.h" |
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#include "i40iw_p.h" |
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#include <linux/pci.h> |
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#include <linux/genalloc.h> |
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#include <linux/vmalloc.h> |
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#include "i40iw_pble.h" |
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#include "i40iw.h" |
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struct i40iw_device; |
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static enum i40iw_status_code add_pble_pool(struct i40iw_sc_dev *dev, |
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struct i40iw_hmc_pble_rsrc *pble_rsrc); |
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static void i40iw_free_vmalloc_mem(struct i40iw_hw *hw, struct i40iw_chunk *chunk); |
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/** |
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* i40iw_destroy_pble_pool - destroy pool during module unload |
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* @dev: i40iw_sc_dev struct |
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* @pble_rsrc: pble resources |
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*/ |
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void i40iw_destroy_pble_pool(struct i40iw_sc_dev *dev, struct i40iw_hmc_pble_rsrc *pble_rsrc) |
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{ |
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struct list_head *clist; |
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struct list_head *tlist; |
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struct i40iw_chunk *chunk; |
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struct i40iw_pble_pool *pinfo = &pble_rsrc->pinfo; |
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if (pinfo->pool) { |
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list_for_each_safe(clist, tlist, &pinfo->clist) { |
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chunk = list_entry(clist, struct i40iw_chunk, list); |
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if (chunk->type == I40IW_VMALLOC) |
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i40iw_free_vmalloc_mem(dev->hw, chunk); |
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kfree(chunk); |
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} |
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gen_pool_destroy(pinfo->pool); |
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} |
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} |
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/** |
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* i40iw_hmc_init_pble - Initialize pble resources during module load |
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* @dev: i40iw_sc_dev struct |
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* @pble_rsrc: pble resources |
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*/ |
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enum i40iw_status_code i40iw_hmc_init_pble(struct i40iw_sc_dev *dev, |
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struct i40iw_hmc_pble_rsrc *pble_rsrc) |
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{ |
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struct i40iw_hmc_info *hmc_info; |
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u32 fpm_idx = 0; |
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hmc_info = dev->hmc_info; |
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pble_rsrc->fpm_base_addr = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].base; |
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/* Now start the pble' on 4k boundary */ |
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if (pble_rsrc->fpm_base_addr & 0xfff) |
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fpm_idx = (PAGE_SIZE - (pble_rsrc->fpm_base_addr & 0xfff)) >> 3; |
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pble_rsrc->unallocated_pble = |
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hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt - fpm_idx; |
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pble_rsrc->next_fpm_addr = pble_rsrc->fpm_base_addr + (fpm_idx << 3); |
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pble_rsrc->pinfo.pool_shift = POOL_SHIFT; |
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pble_rsrc->pinfo.pool = gen_pool_create(pble_rsrc->pinfo.pool_shift, -1); |
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INIT_LIST_HEAD(&pble_rsrc->pinfo.clist); |
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if (!pble_rsrc->pinfo.pool) |
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goto error; |
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if (add_pble_pool(dev, pble_rsrc)) |
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goto error; |
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return 0; |
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error:i40iw_destroy_pble_pool(dev, pble_rsrc); |
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return I40IW_ERR_NO_MEMORY; |
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} |
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/** |
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* get_sd_pd_idx - Returns sd index, pd index and rel_pd_idx from fpm address |
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* @pble_rsrc: structure containing fpm address |
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* @idx: where to return indexes |
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*/ |
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static inline void get_sd_pd_idx(struct i40iw_hmc_pble_rsrc *pble_rsrc, |
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struct sd_pd_idx *idx) |
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{ |
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idx->sd_idx = (u32)(pble_rsrc->next_fpm_addr) / I40IW_HMC_DIRECT_BP_SIZE; |
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idx->pd_idx = (u32)(pble_rsrc->next_fpm_addr) / I40IW_HMC_PAGED_BP_SIZE; |
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idx->rel_pd_idx = (idx->pd_idx % I40IW_HMC_PD_CNT_IN_SD); |
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} |
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/** |
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* add_sd_direct - add sd direct for pble |
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* @dev: hardware control device structure |
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* @pble_rsrc: pble resource ptr |
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* @info: page info for sd |
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*/ |
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static enum i40iw_status_code add_sd_direct(struct i40iw_sc_dev *dev, |
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struct i40iw_hmc_pble_rsrc *pble_rsrc, |
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struct i40iw_add_page_info *info) |
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{ |
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enum i40iw_status_code ret_code = 0; |
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struct sd_pd_idx *idx = &info->idx; |
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struct i40iw_chunk *chunk = info->chunk; |
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struct i40iw_hmc_info *hmc_info = info->hmc_info; |
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struct i40iw_hmc_sd_entry *sd_entry = info->sd_entry; |
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u32 offset = 0; |
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if (!sd_entry->valid) { |
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if (dev->is_pf) { |
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ret_code = i40iw_add_sd_table_entry(dev->hw, hmc_info, |
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info->idx.sd_idx, |
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I40IW_SD_TYPE_DIRECT, |
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I40IW_HMC_DIRECT_BP_SIZE); |
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if (ret_code) |
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return ret_code; |
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chunk->type = I40IW_DMA_COHERENT; |
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} |
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} |
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offset = idx->rel_pd_idx << I40IW_HMC_PAGED_BP_SHIFT; |
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chunk->size = info->pages << I40IW_HMC_PAGED_BP_SHIFT; |
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chunk->vaddr = ((u8 *)sd_entry->u.bp.addr.va + offset); |
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chunk->fpm_addr = pble_rsrc->next_fpm_addr; |
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i40iw_debug(dev, I40IW_DEBUG_PBLE, "chunk_size[%d] = 0x%x vaddr=%p fpm_addr = %llx\n", |
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chunk->size, chunk->size, chunk->vaddr, chunk->fpm_addr); |
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return 0; |
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} |
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/** |
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* i40iw_free_vmalloc_mem - free vmalloc during close |
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* @hw: hw struct |
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* @chunk: chunk information for vmalloc |
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*/ |
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static void i40iw_free_vmalloc_mem(struct i40iw_hw *hw, struct i40iw_chunk *chunk) |
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{ |
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struct pci_dev *pcidev = hw->pcidev; |
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int i; |
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if (!chunk->pg_cnt) |
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goto done; |
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for (i = 0; i < chunk->pg_cnt; i++) |
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dma_unmap_page(&pcidev->dev, chunk->dmaaddrs[i], PAGE_SIZE, DMA_BIDIRECTIONAL); |
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done: |
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kfree(chunk->dmaaddrs); |
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chunk->dmaaddrs = NULL; |
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vfree(chunk->vaddr); |
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chunk->vaddr = NULL; |
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chunk->type = 0; |
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} |
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/** |
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* i40iw_get_vmalloc_mem - get 2M page for sd |
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* @hw: hardware address |
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* @chunk: chunk to adf |
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* @pg_cnt: #of 4 K pages |
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*/ |
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static enum i40iw_status_code i40iw_get_vmalloc_mem(struct i40iw_hw *hw, |
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struct i40iw_chunk *chunk, |
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int pg_cnt) |
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{ |
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struct pci_dev *pcidev = hw->pcidev; |
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struct page *page; |
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u8 *addr; |
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u32 size; |
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int i; |
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chunk->dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL); |
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if (!chunk->dmaaddrs) |
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return I40IW_ERR_NO_MEMORY; |
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size = PAGE_SIZE * pg_cnt; |
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chunk->vaddr = vmalloc(size); |
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if (!chunk->vaddr) { |
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kfree(chunk->dmaaddrs); |
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chunk->dmaaddrs = NULL; |
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return I40IW_ERR_NO_MEMORY; |
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} |
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chunk->size = size; |
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addr = (u8 *)chunk->vaddr; |
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for (i = 0; i < pg_cnt; i++) { |
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page = vmalloc_to_page((void *)addr); |
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if (!page) |
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break; |
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chunk->dmaaddrs[i] = dma_map_page(&pcidev->dev, page, 0, |
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PAGE_SIZE, DMA_BIDIRECTIONAL); |
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if (dma_mapping_error(&pcidev->dev, chunk->dmaaddrs[i])) |
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break; |
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addr += PAGE_SIZE; |
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} |
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chunk->pg_cnt = i; |
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chunk->type = I40IW_VMALLOC; |
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if (i == pg_cnt) |
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return 0; |
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i40iw_free_vmalloc_mem(hw, chunk); |
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return I40IW_ERR_NO_MEMORY; |
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} |
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/** |
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* fpm_to_idx - given fpm address, get pble index |
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* @pble_rsrc: pble resource management |
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* @addr: fpm address for index |
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*/ |
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static inline u32 fpm_to_idx(struct i40iw_hmc_pble_rsrc *pble_rsrc, u64 addr) |
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{ |
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return (addr - (pble_rsrc->fpm_base_addr)) >> 3; |
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} |
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/** |
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* add_bp_pages - add backing pages for sd |
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* @dev: hardware control device structure |
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* @pble_rsrc: pble resource management |
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* @info: page info for sd |
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*/ |
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static enum i40iw_status_code add_bp_pages(struct i40iw_sc_dev *dev, |
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struct i40iw_hmc_pble_rsrc *pble_rsrc, |
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struct i40iw_add_page_info *info) |
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{ |
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u8 *addr; |
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struct i40iw_dma_mem mem; |
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struct i40iw_hmc_pd_entry *pd_entry; |
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struct i40iw_hmc_sd_entry *sd_entry = info->sd_entry; |
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struct i40iw_hmc_info *hmc_info = info->hmc_info; |
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struct i40iw_chunk *chunk = info->chunk; |
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struct i40iw_manage_vf_pble_info vf_pble_info; |
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enum i40iw_status_code status = 0; |
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u32 rel_pd_idx = info->idx.rel_pd_idx; |
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u32 pd_idx = info->idx.pd_idx; |
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u32 i; |
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status = i40iw_get_vmalloc_mem(dev->hw, chunk, info->pages); |
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if (status) |
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return I40IW_ERR_NO_MEMORY; |
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status = i40iw_add_sd_table_entry(dev->hw, hmc_info, |
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info->idx.sd_idx, I40IW_SD_TYPE_PAGED, |
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I40IW_HMC_DIRECT_BP_SIZE); |
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if (status) |
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goto error; |
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if (!dev->is_pf) { |
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status = i40iw_vchnl_vf_add_hmc_objs(dev, I40IW_HMC_IW_PBLE, |
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fpm_to_idx(pble_rsrc, |
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pble_rsrc->next_fpm_addr), |
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(info->pages << PBLE_512_SHIFT)); |
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if (status) { |
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i40iw_pr_err("allocate PBLEs in the PF. Error %i\n", status); |
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goto error; |
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} |
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} |
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addr = chunk->vaddr; |
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for (i = 0; i < info->pages; i++) { |
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mem.pa = chunk->dmaaddrs[i]; |
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mem.size = PAGE_SIZE; |
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mem.va = (void *)(addr); |
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pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx++]; |
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if (!pd_entry->valid) { |
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status = i40iw_add_pd_table_entry(dev->hw, hmc_info, pd_idx++, &mem); |
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if (status) |
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goto error; |
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addr += PAGE_SIZE; |
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} else { |
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i40iw_pr_err("pd entry is valid expecting to be invalid\n"); |
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} |
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} |
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if (!dev->is_pf) { |
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vf_pble_info.first_pd_index = info->idx.rel_pd_idx; |
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vf_pble_info.inv_pd_ent = false; |
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vf_pble_info.pd_entry_cnt = PBLE_PER_PAGE; |
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vf_pble_info.pd_pl_pba = sd_entry->u.pd_table.pd_page_addr.pa; |
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vf_pble_info.sd_index = info->idx.sd_idx; |
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status = i40iw_hw_manage_vf_pble_bp(dev->back_dev, |
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&vf_pble_info, true); |
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if (status) { |
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i40iw_pr_err("CQP manage VF PBLE BP failed. %i\n", status); |
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goto error; |
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} |
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} |
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chunk->fpm_addr = pble_rsrc->next_fpm_addr; |
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return 0; |
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error: |
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i40iw_free_vmalloc_mem(dev->hw, chunk); |
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return status; |
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} |
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/** |
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* add_pble_pool - add a sd entry for pble resoure |
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* @dev: hardware control device structure |
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* @pble_rsrc: pble resource management |
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*/ |
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static enum i40iw_status_code add_pble_pool(struct i40iw_sc_dev *dev, |
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struct i40iw_hmc_pble_rsrc *pble_rsrc) |
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{ |
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struct i40iw_hmc_sd_entry *sd_entry; |
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struct i40iw_hmc_info *hmc_info; |
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struct i40iw_chunk *chunk; |
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struct i40iw_add_page_info info; |
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struct sd_pd_idx *idx = &info.idx; |
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enum i40iw_status_code ret_code = 0; |
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enum i40iw_sd_entry_type sd_entry_type; |
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u64 sd_reg_val = 0; |
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u32 pages; |
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if (pble_rsrc->unallocated_pble < PBLE_PER_PAGE) |
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return I40IW_ERR_NO_MEMORY; |
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if (pble_rsrc->next_fpm_addr & 0xfff) { |
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i40iw_pr_err("next fpm_addr %llx\n", pble_rsrc->next_fpm_addr); |
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return I40IW_ERR_INVALID_PAGE_DESC_INDEX; |
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} |
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chunk = kzalloc(sizeof(*chunk), GFP_KERNEL); |
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if (!chunk) |
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return I40IW_ERR_NO_MEMORY; |
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hmc_info = dev->hmc_info; |
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chunk->fpm_addr = pble_rsrc->next_fpm_addr; |
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get_sd_pd_idx(pble_rsrc, idx); |
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sd_entry = &hmc_info->sd_table.sd_entry[idx->sd_idx]; |
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pages = (idx->rel_pd_idx) ? (I40IW_HMC_PD_CNT_IN_SD - |
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idx->rel_pd_idx) : I40IW_HMC_PD_CNT_IN_SD; |
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pages = min(pages, pble_rsrc->unallocated_pble >> PBLE_512_SHIFT); |
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info.chunk = chunk; |
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info.hmc_info = hmc_info; |
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info.pages = pages; |
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info.sd_entry = sd_entry; |
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if (!sd_entry->valid) { |
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sd_entry_type = (!idx->rel_pd_idx && |
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(pages == I40IW_HMC_PD_CNT_IN_SD) && |
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dev->is_pf) ? I40IW_SD_TYPE_DIRECT : I40IW_SD_TYPE_PAGED; |
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} else { |
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sd_entry_type = sd_entry->entry_type; |
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} |
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i40iw_debug(dev, I40IW_DEBUG_PBLE, |
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"pages = %d, unallocated_pble[%u] current_fpm_addr = %llx\n", |
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pages, pble_rsrc->unallocated_pble, pble_rsrc->next_fpm_addr); |
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i40iw_debug(dev, I40IW_DEBUG_PBLE, "sd_entry_type = %d sd_entry valid = %d\n", |
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sd_entry_type, sd_entry->valid); |
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|
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if (sd_entry_type == I40IW_SD_TYPE_DIRECT) |
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ret_code = add_sd_direct(dev, pble_rsrc, &info); |
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if (ret_code) |
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sd_entry_type = I40IW_SD_TYPE_PAGED; |
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else |
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pble_rsrc->stats_direct_sds++; |
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|
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if (sd_entry_type == I40IW_SD_TYPE_PAGED) { |
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ret_code = add_bp_pages(dev, pble_rsrc, &info); |
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if (ret_code) |
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goto error; |
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else |
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pble_rsrc->stats_paged_sds++; |
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} |
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|
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if (gen_pool_add_virt(pble_rsrc->pinfo.pool, (unsigned long)chunk->vaddr, |
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(phys_addr_t)chunk->fpm_addr, chunk->size, -1)) { |
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i40iw_pr_err("could not allocate memory by gen_pool_addr_virt()\n"); |
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ret_code = I40IW_ERR_NO_MEMORY; |
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goto error; |
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} |
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pble_rsrc->next_fpm_addr += chunk->size; |
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i40iw_debug(dev, I40IW_DEBUG_PBLE, "next_fpm_addr = %llx chunk_size[%u] = 0x%x\n", |
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pble_rsrc->next_fpm_addr, chunk->size, chunk->size); |
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pble_rsrc->unallocated_pble -= (chunk->size >> 3); |
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sd_reg_val = (sd_entry_type == I40IW_SD_TYPE_PAGED) ? |
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sd_entry->u.pd_table.pd_page_addr.pa : sd_entry->u.bp.addr.pa; |
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if (dev->is_pf && !sd_entry->valid) { |
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ret_code = i40iw_hmc_sd_one(dev, hmc_info->hmc_fn_id, |
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sd_reg_val, idx->sd_idx, |
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sd_entry->entry_type, true); |
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if (ret_code) { |
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i40iw_pr_err("cqp cmd failed for sd (pbles)\n"); |
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goto error; |
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} |
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} |
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sd_entry->valid = true; |
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list_add(&chunk->list, &pble_rsrc->pinfo.clist); |
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return 0; |
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error: |
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kfree(chunk); |
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return ret_code; |
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} |
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|
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/** |
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* free_lvl2 - fee level 2 pble |
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* @pble_rsrc: pble resource management |
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* @palloc: level 2 pble allocation |
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*/ |
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static void free_lvl2(struct i40iw_hmc_pble_rsrc *pble_rsrc, |
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struct i40iw_pble_alloc *palloc) |
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{ |
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u32 i; |
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struct gen_pool *pool; |
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struct i40iw_pble_level2 *lvl2 = &palloc->level2; |
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struct i40iw_pble_info *root = &lvl2->root; |
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struct i40iw_pble_info *leaf = lvl2->leaf; |
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|
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pool = pble_rsrc->pinfo.pool; |
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|
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for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) { |
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if (leaf->addr) |
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gen_pool_free(pool, leaf->addr, (leaf->cnt << 3)); |
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else |
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break; |
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} |
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|
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if (root->addr) |
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gen_pool_free(pool, root->addr, (root->cnt << 3)); |
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|
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kfree(lvl2->leaf); |
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lvl2->leaf = NULL; |
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} |
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|
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/** |
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* get_lvl2_pble - get level 2 pble resource |
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* @pble_rsrc: pble resource management |
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* @palloc: level 2 pble allocation |
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* @pool: pool pointer |
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*/ |
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static enum i40iw_status_code get_lvl2_pble(struct i40iw_hmc_pble_rsrc *pble_rsrc, |
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struct i40iw_pble_alloc *palloc, |
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struct gen_pool *pool) |
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{ |
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u32 lf4k, lflast, total, i; |
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u32 pblcnt = PBLE_PER_PAGE; |
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u64 *addr; |
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struct i40iw_pble_level2 *lvl2 = &palloc->level2; |
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struct i40iw_pble_info *root = &lvl2->root; |
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struct i40iw_pble_info *leaf; |
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|
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/* number of full 512 (4K) leafs) */ |
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lf4k = palloc->total_cnt >> 9; |
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lflast = palloc->total_cnt % PBLE_PER_PAGE; |
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total = (lflast == 0) ? lf4k : lf4k + 1; |
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lvl2->leaf_cnt = total; |
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|
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leaf = kzalloc((sizeof(*leaf) * total), GFP_ATOMIC); |
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if (!leaf) |
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return I40IW_ERR_NO_MEMORY; |
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lvl2->leaf = leaf; |
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/* allocate pbles for the root */ |
|
root->addr = gen_pool_alloc(pool, (total << 3)); |
|
if (!root->addr) { |
|
kfree(lvl2->leaf); |
|
lvl2->leaf = NULL; |
|
return I40IW_ERR_NO_MEMORY; |
|
} |
|
root->idx = fpm_to_idx(pble_rsrc, |
|
(u64)gen_pool_virt_to_phys(pool, root->addr)); |
|
root->cnt = total; |
|
addr = (u64 *)root->addr; |
|
for (i = 0; i < total; i++, leaf++) { |
|
pblcnt = (lflast && ((i + 1) == total)) ? lflast : PBLE_PER_PAGE; |
|
leaf->addr = gen_pool_alloc(pool, (pblcnt << 3)); |
|
if (!leaf->addr) |
|
goto error; |
|
leaf->idx = fpm_to_idx(pble_rsrc, (u64)gen_pool_virt_to_phys(pool, leaf->addr)); |
|
|
|
leaf->cnt = pblcnt; |
|
*addr = (u64)leaf->idx; |
|
addr++; |
|
} |
|
palloc->level = I40IW_LEVEL_2; |
|
pble_rsrc->stats_lvl2++; |
|
return 0; |
|
error: |
|
free_lvl2(pble_rsrc, palloc); |
|
return I40IW_ERR_NO_MEMORY; |
|
} |
|
|
|
/** |
|
* get_lvl1_pble - get level 1 pble resource |
|
* @dev: hardware control device structure |
|
* @pble_rsrc: pble resource management |
|
* @palloc: level 1 pble allocation |
|
*/ |
|
static enum i40iw_status_code get_lvl1_pble(struct i40iw_sc_dev *dev, |
|
struct i40iw_hmc_pble_rsrc *pble_rsrc, |
|
struct i40iw_pble_alloc *palloc) |
|
{ |
|
u64 *addr; |
|
struct gen_pool *pool; |
|
struct i40iw_pble_info *lvl1 = &palloc->level1; |
|
|
|
pool = pble_rsrc->pinfo.pool; |
|
addr = (u64 *)gen_pool_alloc(pool, (palloc->total_cnt << 3)); |
|
|
|
if (!addr) |
|
return I40IW_ERR_NO_MEMORY; |
|
|
|
palloc->level = I40IW_LEVEL_1; |
|
lvl1->addr = (unsigned long)addr; |
|
lvl1->idx = fpm_to_idx(pble_rsrc, (u64)gen_pool_virt_to_phys(pool, |
|
(unsigned long)addr)); |
|
lvl1->cnt = palloc->total_cnt; |
|
pble_rsrc->stats_lvl1++; |
|
return 0; |
|
} |
|
|
|
/** |
|
* get_lvl1_lvl2_pble - calls get_lvl1 and get_lvl2 pble routine |
|
* @dev: i40iw_sc_dev struct |
|
* @pble_rsrc: pble resources |
|
* @palloc: contains all inforamtion regarding pble (idx + pble addr) |
|
* @pool: pointer to general purpose special memory pool descriptor |
|
*/ |
|
static inline enum i40iw_status_code get_lvl1_lvl2_pble(struct i40iw_sc_dev *dev, |
|
struct i40iw_hmc_pble_rsrc *pble_rsrc, |
|
struct i40iw_pble_alloc *palloc, |
|
struct gen_pool *pool) |
|
{ |
|
enum i40iw_status_code status = 0; |
|
|
|
status = get_lvl1_pble(dev, pble_rsrc, palloc); |
|
if (status && (palloc->total_cnt > PBLE_PER_PAGE)) |
|
status = get_lvl2_pble(pble_rsrc, palloc, pool); |
|
return status; |
|
} |
|
|
|
/** |
|
* i40iw_get_pble - allocate pbles from the pool |
|
* @dev: i40iw_sc_dev struct |
|
* @pble_rsrc: pble resources |
|
* @palloc: contains all inforamtion regarding pble (idx + pble addr) |
|
* @pble_cnt: #of pbles requested |
|
*/ |
|
enum i40iw_status_code i40iw_get_pble(struct i40iw_sc_dev *dev, |
|
struct i40iw_hmc_pble_rsrc *pble_rsrc, |
|
struct i40iw_pble_alloc *palloc, |
|
u32 pble_cnt) |
|
{ |
|
struct gen_pool *pool; |
|
enum i40iw_status_code status = 0; |
|
u32 max_sds = 0; |
|
int i; |
|
|
|
pool = pble_rsrc->pinfo.pool; |
|
palloc->total_cnt = pble_cnt; |
|
palloc->level = I40IW_LEVEL_0; |
|
/*check first to see if we can get pble's without acquiring additional sd's */ |
|
status = get_lvl1_lvl2_pble(dev, pble_rsrc, palloc, pool); |
|
if (!status) |
|
goto exit; |
|
max_sds = (palloc->total_cnt >> 18) + 1; |
|
for (i = 0; i < max_sds; i++) { |
|
status = add_pble_pool(dev, pble_rsrc); |
|
if (status) |
|
break; |
|
status = get_lvl1_lvl2_pble(dev, pble_rsrc, palloc, pool); |
|
if (!status) |
|
break; |
|
} |
|
exit: |
|
if (!status) |
|
pble_rsrc->stats_alloc_ok++; |
|
else |
|
pble_rsrc->stats_alloc_fail++; |
|
|
|
return status; |
|
} |
|
|
|
/** |
|
* i40iw_free_pble - put pbles back into pool |
|
* @pble_rsrc: pble resources |
|
* @palloc: contains all inforamtion regarding pble resource being freed |
|
*/ |
|
void i40iw_free_pble(struct i40iw_hmc_pble_rsrc *pble_rsrc, |
|
struct i40iw_pble_alloc *palloc) |
|
{ |
|
struct gen_pool *pool; |
|
|
|
pool = pble_rsrc->pinfo.pool; |
|
if (palloc->level == I40IW_LEVEL_2) |
|
free_lvl2(pble_rsrc, palloc); |
|
else |
|
gen_pool_free(pool, palloc->level1.addr, |
|
(palloc->level1.cnt << 3)); |
|
pble_rsrc->stats_alloc_freed++; |
|
}
|
|
|