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741 lines
19 KiB
741 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2010 Sascha Hauer <[email protected]> |
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/export.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/errno.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/platform_device.h> |
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#include <video/imx-ipu-v3.h> |
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#include "ipu-prv.h" |
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struct ipu_di { |
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void __iomem *base; |
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int id; |
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u32 module; |
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struct clk *clk_di; /* display input clock */ |
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struct clk *clk_ipu; /* IPU bus clock */ |
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struct clk *clk_di_pixel; /* resulting pixel clock */ |
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bool inuse; |
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struct ipu_soc *ipu; |
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}; |
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static DEFINE_MUTEX(di_mutex); |
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struct di_sync_config { |
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int run_count; |
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int run_src; |
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int offset_count; |
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int offset_src; |
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int repeat_count; |
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int cnt_clr_src; |
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int cnt_polarity_gen_en; |
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int cnt_polarity_clr_src; |
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int cnt_polarity_trigger_src; |
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int cnt_up; |
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int cnt_down; |
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}; |
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enum di_pins { |
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DI_PIN11 = 0, |
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DI_PIN12 = 1, |
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DI_PIN13 = 2, |
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DI_PIN14 = 3, |
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DI_PIN15 = 4, |
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DI_PIN16 = 5, |
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DI_PIN17 = 6, |
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DI_PIN_CS = 7, |
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DI_PIN_SER_CLK = 0, |
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DI_PIN_SER_RS = 1, |
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}; |
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enum di_sync_wave { |
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DI_SYNC_NONE = 0, |
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DI_SYNC_CLK = 1, |
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DI_SYNC_INT_HSYNC = 2, |
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DI_SYNC_HSYNC = 3, |
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DI_SYNC_VSYNC = 4, |
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DI_SYNC_DE = 6, |
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DI_SYNC_CNT1 = 2, /* counter >= 2 only */ |
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DI_SYNC_CNT4 = 5, /* counter >= 5 only */ |
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DI_SYNC_CNT5 = 6, /* counter >= 6 only */ |
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}; |
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#define SYNC_WAVE 0 |
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#define DI_GENERAL 0x0000 |
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#define DI_BS_CLKGEN0 0x0004 |
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#define DI_BS_CLKGEN1 0x0008 |
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#define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) |
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#define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) |
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#define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) |
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#define DI_SYNC_AS_GEN 0x0054 |
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#define DI_DW_GEN(gen) (0x0058 + 4 * (gen)) |
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#define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set))) |
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#define DI_SER_CONF 0x015c |
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#define DI_SSC 0x0160 |
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#define DI_POL 0x0164 |
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#define DI_AW0 0x0168 |
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#define DI_AW1 0x016c |
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#define DI_SCR_CONF 0x0170 |
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#define DI_STAT 0x0174 |
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#define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19) |
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#define DI_SW_GEN0_RUN_SRC(x) ((x) << 16) |
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#define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3) |
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#define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0) |
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#define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29) |
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#define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25) |
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#define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12) |
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#define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9) |
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#define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16) |
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#define DI_SW_GEN1_CNT_UP(x) (x) |
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#define DI_SW_GEN1_AUTO_RELOAD (0x10000000) |
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#define DI_DW_GEN_ACCESS_SIZE_OFFSET 24 |
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#define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16 |
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#define DI_GEN_POLARITY_1 (1 << 0) |
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#define DI_GEN_POLARITY_2 (1 << 1) |
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#define DI_GEN_POLARITY_3 (1 << 2) |
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#define DI_GEN_POLARITY_4 (1 << 3) |
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#define DI_GEN_POLARITY_5 (1 << 4) |
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#define DI_GEN_POLARITY_6 (1 << 5) |
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#define DI_GEN_POLARITY_7 (1 << 6) |
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#define DI_GEN_POLARITY_8 (1 << 7) |
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#define DI_GEN_POLARITY_DISP_CLK (1 << 17) |
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#define DI_GEN_DI_CLK_EXT (1 << 20) |
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#define DI_GEN_DI_VSYNC_EXT (1 << 21) |
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#define DI_POL_DRDY_DATA_POLARITY (1 << 7) |
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#define DI_POL_DRDY_POLARITY_15 (1 << 4) |
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#define DI_VSYNC_SEL_OFFSET 13 |
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static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset) |
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{ |
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return readl(di->base + offset); |
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} |
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static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset) |
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{ |
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writel(value, di->base + offset); |
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} |
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static void ipu_di_data_wave_config(struct ipu_di *di, |
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int wave_gen, |
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int access_size, int component_size) |
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{ |
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u32 reg; |
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reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | |
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(component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET); |
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ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); |
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} |
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static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, |
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int set, int up, int down) |
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{ |
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u32 reg; |
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reg = ipu_di_read(di, DI_DW_GEN(wave_gen)); |
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reg &= ~(0x3 << (di_pin * 2)); |
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reg |= set << (di_pin * 2); |
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ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); |
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ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); |
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} |
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static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config, |
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int start, int count) |
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{ |
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u32 reg; |
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int i; |
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for (i = 0; i < count; i++) { |
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struct di_sync_config *c = &config[i]; |
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int wave_gen = start + i + 1; |
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if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) || |
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(c->repeat_count >= 0x1000) || |
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(c->cnt_up >= 0x400) || |
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(c->cnt_down >= 0x400)) { |
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dev_err(di->ipu->dev, "DI%d counters out of range.\n", |
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di->id); |
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return; |
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} |
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reg = DI_SW_GEN0_RUN_COUNT(c->run_count) | |
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DI_SW_GEN0_RUN_SRC(c->run_src) | |
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DI_SW_GEN0_OFFSET_COUNT(c->offset_count) | |
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DI_SW_GEN0_OFFSET_SRC(c->offset_src); |
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ipu_di_write(di, reg, DI_SW_GEN0(wave_gen)); |
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reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) | |
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DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) | |
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DI_SW_GEN1_CNT_POL_TRIGGER_SRC( |
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c->cnt_polarity_trigger_src) | |
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DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) | |
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DI_SW_GEN1_CNT_DOWN(c->cnt_down) | |
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DI_SW_GEN1_CNT_UP(c->cnt_up); |
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/* Enable auto reload */ |
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if (c->repeat_count == 0) |
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reg |= DI_SW_GEN1_AUTO_RELOAD; |
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ipu_di_write(di, reg, DI_SW_GEN1(wave_gen)); |
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reg = ipu_di_read(di, DI_STP_REP(wave_gen)); |
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reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1))); |
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reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1)); |
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ipu_di_write(di, reg, DI_STP_REP(wave_gen)); |
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} |
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} |
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static void ipu_di_sync_config_interlaced(struct ipu_di *di, |
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struct ipu_di_signal_cfg *sig) |
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{ |
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u32 h_total = sig->mode.hactive + sig->mode.hsync_len + |
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sig->mode.hback_porch + sig->mode.hfront_porch; |
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u32 v_total = sig->mode.vactive + sig->mode.vsync_len + |
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sig->mode.vback_porch + sig->mode.vfront_porch; |
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struct di_sync_config cfg[] = { |
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{ |
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/* 1: internal VSYNC for each frame */ |
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.run_count = v_total * 2 - 1, |
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.run_src = 3, /* == counter 7 */ |
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}, { |
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/* PIN2: HSYNC waveform */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_CLK, |
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.cnt_down = sig->mode.hsync_len * 2, |
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}, { |
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/* PIN3: VSYNC waveform */ |
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.run_count = v_total - 1, |
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.run_src = 4, /* == counter 7 */ |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = 4, /* == counter 7 */ |
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.cnt_down = sig->mode.vsync_len * 2, |
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.cnt_clr_src = DI_SYNC_CNT1, |
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}, { |
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/* 4: Field */ |
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.run_count = v_total / 2, |
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.run_src = DI_SYNC_HSYNC, |
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.offset_count = h_total / 2, |
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.offset_src = DI_SYNC_CLK, |
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.repeat_count = 2, |
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.cnt_clr_src = DI_SYNC_CNT1, |
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}, { |
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/* 5: Active lines */ |
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.run_src = DI_SYNC_HSYNC, |
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.offset_count = (sig->mode.vsync_len + |
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sig->mode.vback_porch) / 2, |
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.offset_src = DI_SYNC_HSYNC, |
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.repeat_count = sig->mode.vactive / 2, |
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.cnt_clr_src = DI_SYNC_CNT4, |
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}, { |
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/* 6: Active pixel, referenced by DC */ |
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.run_src = DI_SYNC_CLK, |
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.offset_count = sig->mode.hsync_len + |
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sig->mode.hback_porch, |
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.offset_src = DI_SYNC_CLK, |
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.repeat_count = sig->mode.hactive, |
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.cnt_clr_src = DI_SYNC_CNT5, |
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}, { |
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/* 7: Half line HSYNC */ |
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.run_count = h_total / 2 - 1, |
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.run_src = DI_SYNC_CLK, |
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} |
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}; |
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ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); |
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ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); |
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} |
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static void ipu_di_sync_config_noninterlaced(struct ipu_di *di, |
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struct ipu_di_signal_cfg *sig, int div) |
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{ |
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u32 h_total = sig->mode.hactive + sig->mode.hsync_len + |
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sig->mode.hback_porch + sig->mode.hfront_porch; |
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u32 v_total = sig->mode.vactive + sig->mode.vsync_len + |
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sig->mode.vback_porch + sig->mode.vfront_porch; |
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struct di_sync_config cfg[] = { |
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{ |
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/* 1: INT_HSYNC */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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} , { |
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/* PIN2: HSYNC */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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.offset_count = div * sig->v_to_h_sync, |
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.offset_src = DI_SYNC_CLK, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_CLK, |
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.cnt_down = sig->mode.hsync_len * 2, |
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} , { |
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/* PIN3: VSYNC */ |
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.run_count = v_total - 1, |
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.run_src = DI_SYNC_INT_HSYNC, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, |
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.cnt_down = sig->mode.vsync_len * 2, |
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} , { |
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/* 4: Line Active */ |
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.run_src = DI_SYNC_HSYNC, |
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.offset_count = sig->mode.vsync_len + |
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sig->mode.vback_porch, |
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.offset_src = DI_SYNC_HSYNC, |
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.repeat_count = sig->mode.vactive, |
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.cnt_clr_src = DI_SYNC_VSYNC, |
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} , { |
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/* 5: Pixel Active, referenced by DC */ |
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.run_src = DI_SYNC_CLK, |
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.offset_count = sig->mode.hsync_len + |
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sig->mode.hback_porch, |
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.offset_src = DI_SYNC_CLK, |
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.repeat_count = sig->mode.hactive, |
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.cnt_clr_src = 5, /* Line Active */ |
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} , { |
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/* unused */ |
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} , { |
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/* unused */ |
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}, |
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}; |
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/* can't use #7 and #8 for line active and pixel active counters */ |
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struct di_sync_config cfg_vga[] = { |
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{ |
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/* 1: INT_HSYNC */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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} , { |
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/* 2: VSYNC */ |
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.run_count = v_total - 1, |
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.run_src = DI_SYNC_INT_HSYNC, |
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} , { |
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/* 3: Line Active */ |
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.run_src = DI_SYNC_INT_HSYNC, |
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.offset_count = sig->mode.vsync_len + |
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sig->mode.vback_porch, |
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.offset_src = DI_SYNC_INT_HSYNC, |
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.repeat_count = sig->mode.vactive, |
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.cnt_clr_src = 3 /* VSYNC */, |
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} , { |
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/* PIN4: HSYNC for VGA via TVEv2 on TQ MBa53 */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ |
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.offset_src = DI_SYNC_CLK, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_CLK, |
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.cnt_down = sig->mode.hsync_len * 2, |
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} , { |
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/* 5: Pixel Active signal to DC */ |
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.run_src = DI_SYNC_CLK, |
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.offset_count = sig->mode.hsync_len + |
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sig->mode.hback_porch, |
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.offset_src = DI_SYNC_CLK, |
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.repeat_count = sig->mode.hactive, |
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.cnt_clr_src = 4, /* Line Active */ |
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} , { |
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/* PIN6: VSYNC for VGA via TVEv2 on TQ MBa53 */ |
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.run_count = v_total - 1, |
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.run_src = DI_SYNC_INT_HSYNC, |
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.offset_count = 1, /* magic value from Freescale TVE driver */ |
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.offset_src = DI_SYNC_INT_HSYNC, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, |
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.cnt_down = sig->mode.vsync_len * 2, |
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} , { |
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/* PIN4: HSYNC for VGA via TVEv2 on i.MX53-QSB */ |
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.run_count = h_total - 1, |
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.run_src = DI_SYNC_CLK, |
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.offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ |
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.offset_src = DI_SYNC_CLK, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_CLK, |
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.cnt_down = sig->mode.hsync_len * 2, |
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} , { |
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/* PIN6: VSYNC for VGA via TVEv2 on i.MX53-QSB */ |
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.run_count = v_total - 1, |
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.run_src = DI_SYNC_INT_HSYNC, |
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.offset_count = 1, /* magic value from Freescale TVE driver */ |
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.offset_src = DI_SYNC_INT_HSYNC, |
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.cnt_polarity_gen_en = 1, |
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.cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC, |
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.cnt_down = sig->mode.vsync_len * 2, |
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} , { |
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/* unused */ |
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}, |
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}; |
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ipu_di_write(di, v_total - 1, DI_SCR_CONF); |
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if (sig->hsync_pin == 2 && sig->vsync_pin == 3) |
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ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg)); |
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else |
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ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga)); |
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} |
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static void ipu_di_config_clock(struct ipu_di *di, |
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const struct ipu_di_signal_cfg *sig) |
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{ |
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struct clk *clk; |
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unsigned clkgen0; |
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uint32_t val; |
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if (sig->clkflags & IPU_DI_CLKMODE_EXT) { |
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/* |
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* CLKMODE_EXT means we must use the DI clock: this is |
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* needed for things like LVDS which needs to feed the |
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* DI and LDB with the same pixel clock. |
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*/ |
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clk = di->clk_di; |
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if (sig->clkflags & IPU_DI_CLKMODE_SYNC) { |
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/* |
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* CLKMODE_SYNC means that we want the DI to be |
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* clocked at the same rate as the parent clock. |
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* This is needed (eg) for LDB which needs to be |
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* fed with the same pixel clock. We assume that |
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* the LDB clock has already been set correctly. |
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*/ |
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clkgen0 = 1 << 4; |
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} else { |
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/* |
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* We can use the divider. We should really have |
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* a flag here indicating whether the bridge can |
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* cope with a fractional divider or not. For the |
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* time being, let's go for simplicitly and |
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* reliability. |
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*/ |
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unsigned long in_rate; |
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unsigned div; |
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clk_set_rate(clk, sig->mode.pixelclock); |
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in_rate = clk_get_rate(clk); |
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div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
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div = clamp(div, 1U, 255U); |
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|
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clkgen0 = div << 4; |
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} |
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} else { |
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/* |
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* For other interfaces, we can arbitarily select between |
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* the DI specific clock and the internal IPU clock. See |
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* DI_GENERAL bit 20. We select the IPU clock if it can |
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* give us a clock rate within 1% of the requested frequency, |
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* otherwise we use the DI clock. |
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*/ |
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unsigned long rate, clkrate; |
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unsigned div, error; |
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clkrate = clk_get_rate(di->clk_ipu); |
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div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); |
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div = clamp(div, 1U, 255U); |
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rate = clkrate / div; |
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error = rate / (sig->mode.pixelclock / 1000); |
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dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n", |
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rate, div, (signed)(error - 1000) / 10, error % 10); |
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/* Allow a 1% error */ |
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if (error < 1010 && error >= 990) { |
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clk = di->clk_ipu; |
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clkgen0 = div << 4; |
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} else { |
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unsigned long in_rate; |
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unsigned div; |
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clk = di->clk_di; |
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clk_set_rate(clk, sig->mode.pixelclock); |
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in_rate = clk_get_rate(clk); |
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div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); |
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div = clamp(div, 1U, 255U); |
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|
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clkgen0 = div << 4; |
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} |
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} |
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di->clk_di_pixel = clk; |
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|
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/* Set the divider */ |
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ipu_di_write(di, clkgen0, DI_BS_CLKGEN0); |
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|
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/* |
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* Set the high/low periods. Bits 24:16 give us the falling edge, |
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* and bits 8:0 give the rising edge. LSB is fraction, and is |
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* based on the divider above. We want a 50% duty cycle, so set |
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* the falling edge to be half the divider. |
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*/ |
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ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1); |
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|
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/* Finally select the input clock */ |
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val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT; |
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if (clk == di->clk_di) |
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val |= DI_GEN_DI_CLK_EXT; |
|
ipu_di_write(di, val, DI_GENERAL); |
|
|
|
dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n", |
|
sig->mode.pixelclock, |
|
clk_get_rate(di->clk_ipu), |
|
clk_get_rate(di->clk_di), |
|
clk == di->clk_di ? "DI" : "IPU", |
|
clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4)); |
|
} |
|
|
|
/* |
|
* This function is called to adjust a video mode to IPU restrictions. |
|
* It is meant to be called from drm crtc mode_fixup() methods. |
|
*/ |
|
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode) |
|
{ |
|
u32 diff; |
|
|
|
if (mode->vfront_porch >= 2) |
|
return 0; |
|
|
|
diff = 2 - mode->vfront_porch; |
|
|
|
if (mode->vback_porch >= diff) { |
|
mode->vfront_porch = 2; |
|
mode->vback_porch -= diff; |
|
} else if (mode->vsync_len > diff) { |
|
mode->vfront_porch = 2; |
|
mode->vsync_len = mode->vsync_len - diff; |
|
} else { |
|
dev_warn(di->ipu->dev, "failed to adjust videomode\n"); |
|
return -EINVAL; |
|
} |
|
|
|
dev_dbg(di->ipu->dev, "videomode adapted for IPU restrictions\n"); |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_adjust_videomode); |
|
|
|
static u32 ipu_di_gen_polarity(int pin) |
|
{ |
|
switch (pin) { |
|
case 1: |
|
return DI_GEN_POLARITY_1; |
|
case 2: |
|
return DI_GEN_POLARITY_2; |
|
case 3: |
|
return DI_GEN_POLARITY_3; |
|
case 4: |
|
return DI_GEN_POLARITY_4; |
|
case 5: |
|
return DI_GEN_POLARITY_5; |
|
case 6: |
|
return DI_GEN_POLARITY_6; |
|
case 7: |
|
return DI_GEN_POLARITY_7; |
|
case 8: |
|
return DI_GEN_POLARITY_8; |
|
} |
|
return 0; |
|
} |
|
|
|
int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig) |
|
{ |
|
u32 reg; |
|
u32 di_gen, vsync_cnt; |
|
u32 div; |
|
|
|
dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n", |
|
di->id, sig->mode.hactive, sig->mode.vactive); |
|
|
|
dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n", |
|
clk_get_rate(di->clk_ipu), |
|
clk_get_rate(di->clk_di), |
|
sig->mode.pixelclock); |
|
|
|
mutex_lock(&di_mutex); |
|
|
|
ipu_di_config_clock(di, sig); |
|
|
|
div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff; |
|
div = div / 16; /* Now divider is integer portion */ |
|
|
|
/* Setup pixel clock timing */ |
|
/* Down time is half of period */ |
|
ipu_di_write(di, (div << 16), DI_BS_CLKGEN1); |
|
|
|
ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1); |
|
ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2); |
|
|
|
di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT; |
|
di_gen |= DI_GEN_DI_VSYNC_EXT; |
|
|
|
if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) { |
|
ipu_di_sync_config_interlaced(di, sig); |
|
|
|
/* set y_sel = 1 */ |
|
di_gen |= 0x10000000; |
|
|
|
vsync_cnt = 3; |
|
} else { |
|
ipu_di_sync_config_noninterlaced(di, sig, div); |
|
|
|
vsync_cnt = 3; |
|
if (di->id == 1) |
|
/* |
|
* TODO: change only for TVEv2, parallel display |
|
* uses pin 2 / 3 |
|
*/ |
|
if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3)) |
|
vsync_cnt = 6; |
|
} |
|
|
|
if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH) |
|
di_gen |= ipu_di_gen_polarity(sig->hsync_pin); |
|
if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH) |
|
di_gen |= ipu_di_gen_polarity(sig->vsync_pin); |
|
|
|
if (sig->clk_pol) |
|
di_gen |= DI_GEN_POLARITY_DISP_CLK; |
|
|
|
ipu_di_write(di, di_gen, DI_GENERAL); |
|
|
|
ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002, |
|
DI_SYNC_AS_GEN); |
|
|
|
reg = ipu_di_read(di, DI_POL); |
|
reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); |
|
|
|
if (sig->enable_pol) |
|
reg |= DI_POL_DRDY_POLARITY_15; |
|
if (sig->data_pol) |
|
reg |= DI_POL_DRDY_DATA_POLARITY; |
|
|
|
ipu_di_write(di, reg, DI_POL); |
|
|
|
mutex_unlock(&di_mutex); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel); |
|
|
|
int ipu_di_enable(struct ipu_di *di) |
|
{ |
|
int ret; |
|
|
|
WARN_ON(IS_ERR(di->clk_di_pixel)); |
|
|
|
ret = clk_prepare_enable(di->clk_di_pixel); |
|
if (ret) |
|
return ret; |
|
|
|
ipu_module_enable(di->ipu, di->module); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_enable); |
|
|
|
int ipu_di_disable(struct ipu_di *di) |
|
{ |
|
WARN_ON(IS_ERR(di->clk_di_pixel)); |
|
|
|
ipu_module_disable(di->ipu, di->module); |
|
|
|
clk_disable_unprepare(di->clk_di_pixel); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_disable); |
|
|
|
int ipu_di_get_num(struct ipu_di *di) |
|
{ |
|
return di->id; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_get_num); |
|
|
|
static DEFINE_MUTEX(ipu_di_lock); |
|
|
|
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp) |
|
{ |
|
struct ipu_di *di; |
|
|
|
if (disp > 1) |
|
return ERR_PTR(-EINVAL); |
|
|
|
di = ipu->di_priv[disp]; |
|
|
|
mutex_lock(&ipu_di_lock); |
|
|
|
if (di->inuse) { |
|
di = ERR_PTR(-EBUSY); |
|
goto out; |
|
} |
|
|
|
di->inuse = true; |
|
out: |
|
mutex_unlock(&ipu_di_lock); |
|
|
|
return di; |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_get); |
|
|
|
void ipu_di_put(struct ipu_di *di) |
|
{ |
|
mutex_lock(&ipu_di_lock); |
|
|
|
di->inuse = false; |
|
|
|
mutex_unlock(&ipu_di_lock); |
|
} |
|
EXPORT_SYMBOL_GPL(ipu_di_put); |
|
|
|
int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, |
|
unsigned long base, |
|
u32 module, struct clk *clk_ipu) |
|
{ |
|
struct ipu_di *di; |
|
|
|
if (id > 1) |
|
return -ENODEV; |
|
|
|
di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL); |
|
if (!di) |
|
return -ENOMEM; |
|
|
|
ipu->di_priv[id] = di; |
|
|
|
di->clk_di = devm_clk_get(dev, id ? "di1" : "di0"); |
|
if (IS_ERR(di->clk_di)) |
|
return PTR_ERR(di->clk_di); |
|
|
|
di->module = module; |
|
di->id = id; |
|
di->clk_ipu = clk_ipu; |
|
di->base = devm_ioremap(dev, base, PAGE_SIZE); |
|
if (!di->base) |
|
return -ENOMEM; |
|
|
|
ipu_di_write(di, 0x10, DI_BS_CLKGEN0); |
|
|
|
dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n", |
|
id, base, di->base); |
|
di->inuse = false; |
|
di->ipu = ipu; |
|
|
|
return 0; |
|
} |
|
|
|
void ipu_di_exit(struct ipu_soc *ipu, int id) |
|
{ |
|
}
|
|
|