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905 lines
23 KiB
905 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_dma.h> |
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#include <linux/platform_device.h> |
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#include <linux/reset.h> |
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#include <linux/scatterlist.h> |
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#include <linux/slab.h> |
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|
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#include "../dmaengine.h" |
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#include "../virt-dma.h" |
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|
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/* ADM registers - calculated from channel number and security domain */ |
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#define ADM_CHAN_MULTI 0x4 |
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#define ADM_CI_MULTI 0x4 |
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#define ADM_CRCI_MULTI 0x4 |
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#define ADM_EE_MULTI 0x800 |
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#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) |
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#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * (ee)) |
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#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) |
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#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) |
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#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) |
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#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) |
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#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) |
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#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) |
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#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) |
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#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) |
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#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) |
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#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) |
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#define ADM_CI_CONF(ci) (0x390 + (ci) * ADM_CI_MULTI) |
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#define ADM_GP_CTL 0x3d8 |
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#define ADM_CRCI_CTL(crci, ee) (0x400 + (crci) * ADM_CRCI_MULTI + \ |
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ADM_EE_OFFS(ee)) |
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|
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/* channel status */ |
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#define ADM_CH_STATUS_VALID BIT(1) |
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|
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/* channel result */ |
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#define ADM_CH_RSLT_VALID BIT(31) |
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#define ADM_CH_RSLT_ERR BIT(3) |
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#define ADM_CH_RSLT_FLUSH BIT(2) |
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#define ADM_CH_RSLT_TPD BIT(1) |
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|
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/* channel conf */ |
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#define ADM_CH_CONF_SHADOW_EN BIT(12) |
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#define ADM_CH_CONF_MPU_DISABLE BIT(11) |
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#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) |
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#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) |
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#define ADM_CH_CONF_SEC_DOMAIN(ee) ((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11)) |
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|
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/* channel result conf */ |
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#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) |
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#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) |
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|
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/* CRCI CTL */ |
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#define ADM_CRCI_CTL_MUX_SEL BIT(18) |
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#define ADM_CRCI_CTL_RST BIT(17) |
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|
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/* CI configuration */ |
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#define ADM_CI_RANGE_END(x) ((x) << 24) |
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#define ADM_CI_RANGE_START(x) ((x) << 16) |
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#define ADM_CI_BURST_4_WORDS BIT(2) |
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#define ADM_CI_BURST_8_WORDS BIT(3) |
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|
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/* GP CTL */ |
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#define ADM_GP_CTL_LP_EN BIT(12) |
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#define ADM_GP_CTL_LP_CNT(x) ((x) << 8) |
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|
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/* Command pointer list entry */ |
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#define ADM_CPLE_LP BIT(31) |
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#define ADM_CPLE_CMD_PTR_LIST BIT(29) |
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|
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/* Command list entry */ |
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#define ADM_CMD_LC BIT(31) |
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#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) |
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#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) |
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|
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#define ADM_CMD_TYPE_SINGLE 0x0 |
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#define ADM_CMD_TYPE_BOX 0x3 |
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|
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#define ADM_CRCI_MUX_SEL BIT(4) |
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#define ADM_DESC_ALIGN 8 |
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#define ADM_MAX_XFER (SZ_64K - 1) |
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#define ADM_MAX_ROWS (SZ_64K - 1) |
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#define ADM_MAX_CHANNELS 16 |
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|
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struct adm_desc_hw_box { |
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u32 cmd; |
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u32 src_addr; |
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u32 dst_addr; |
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u32 row_len; |
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u32 num_rows; |
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u32 row_offset; |
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}; |
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struct adm_desc_hw_single { |
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u32 cmd; |
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u32 src_addr; |
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u32 dst_addr; |
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u32 len; |
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}; |
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struct adm_async_desc { |
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struct virt_dma_desc vd; |
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struct adm_device *adev; |
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size_t length; |
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enum dma_transfer_direction dir; |
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dma_addr_t dma_addr; |
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size_t dma_len; |
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|
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void *cpl; |
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dma_addr_t cp_addr; |
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u32 crci; |
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u32 mux; |
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u32 blk_size; |
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}; |
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struct adm_chan { |
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struct virt_dma_chan vc; |
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struct adm_device *adev; |
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|
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/* parsed from DT */ |
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u32 id; /* channel id */ |
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struct adm_async_desc *curr_txd; |
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struct dma_slave_config slave; |
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struct list_head node; |
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|
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int error; |
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int initialized; |
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}; |
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static inline struct adm_chan *to_adm_chan(struct dma_chan *common) |
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{ |
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return container_of(common, struct adm_chan, vc.chan); |
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} |
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struct adm_device { |
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void __iomem *regs; |
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struct device *dev; |
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struct dma_device common; |
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struct device_dma_parameters dma_parms; |
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struct adm_chan *channels; |
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u32 ee; |
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struct clk *core_clk; |
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struct clk *iface_clk; |
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struct reset_control *clk_reset; |
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struct reset_control *c0_reset; |
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struct reset_control *c1_reset; |
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struct reset_control *c2_reset; |
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int irq; |
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}; |
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/** |
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* adm_free_chan - Frees dma resources associated with the specific channel |
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* |
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* @chan: dma channel |
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* |
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* Free all allocated descriptors associated with this channel |
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*/ |
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static void adm_free_chan(struct dma_chan *chan) |
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{ |
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/* free all queued descriptors */ |
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vchan_free_chan_resources(to_virt_chan(chan)); |
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} |
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/** |
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* adm_get_blksize - Get block size from burst value |
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* |
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* @burst: Burst size of transaction |
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*/ |
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static int adm_get_blksize(unsigned int burst) |
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{ |
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int ret; |
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|
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switch (burst) { |
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case 16: |
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case 32: |
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case 64: |
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case 128: |
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ret = ffs(burst >> 4) - 1; |
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break; |
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case 192: |
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ret = 4; |
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break; |
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case 256: |
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ret = 5; |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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return ret; |
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} |
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|
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/** |
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* adm_process_fc_descriptors - Process descriptors for flow controlled xfers |
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* |
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* @achan: ADM channel |
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* @desc: Descriptor memory pointer |
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* @sg: Scatterlist entry |
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* @crci: CRCI value |
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* @burst: Burst size of transaction |
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* @direction: DMA transfer direction |
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*/ |
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static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc, |
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struct scatterlist *sg, u32 crci, |
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u32 burst, |
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enum dma_transfer_direction direction) |
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{ |
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struct adm_desc_hw_box *box_desc = NULL; |
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struct adm_desc_hw_single *single_desc; |
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u32 remainder = sg_dma_len(sg); |
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u32 rows, row_offset, crci_cmd; |
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u32 mem_addr = sg_dma_address(sg); |
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u32 *incr_addr = &mem_addr; |
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u32 *src, *dst; |
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|
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if (direction == DMA_DEV_TO_MEM) { |
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crci_cmd = ADM_CMD_SRC_CRCI(crci); |
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row_offset = burst; |
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src = &achan->slave.src_addr; |
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dst = &mem_addr; |
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} else { |
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crci_cmd = ADM_CMD_DST_CRCI(crci); |
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row_offset = burst << 16; |
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src = &mem_addr; |
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dst = &achan->slave.dst_addr; |
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} |
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while (remainder >= burst) { |
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box_desc = desc; |
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box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; |
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box_desc->row_offset = row_offset; |
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box_desc->src_addr = *src; |
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box_desc->dst_addr = *dst; |
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rows = remainder / burst; |
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rows = min_t(u32, rows, ADM_MAX_ROWS); |
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box_desc->num_rows = rows << 16 | rows; |
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box_desc->row_len = burst << 16 | burst; |
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*incr_addr += burst * rows; |
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remainder -= burst * rows; |
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desc += sizeof(*box_desc); |
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} |
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/* if leftover bytes, do one single descriptor */ |
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if (remainder) { |
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single_desc = desc; |
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single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; |
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single_desc->len = remainder; |
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single_desc->src_addr = *src; |
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single_desc->dst_addr = *dst; |
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desc += sizeof(*single_desc); |
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if (sg_is_last(sg)) |
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single_desc->cmd |= ADM_CMD_LC; |
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} else { |
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if (box_desc && sg_is_last(sg)) |
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box_desc->cmd |= ADM_CMD_LC; |
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} |
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return desc; |
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} |
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/** |
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* adm_process_non_fc_descriptors - Process descriptors for non-fc xfers |
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* |
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* @achan: ADM channel |
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* @desc: Descriptor memory pointer |
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* @sg: Scatterlist entry |
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* @direction: DMA transfer direction |
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*/ |
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static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc, |
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struct scatterlist *sg, |
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enum dma_transfer_direction direction) |
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{ |
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struct adm_desc_hw_single *single_desc; |
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u32 remainder = sg_dma_len(sg); |
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u32 mem_addr = sg_dma_address(sg); |
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u32 *incr_addr = &mem_addr; |
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u32 *src, *dst; |
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if (direction == DMA_DEV_TO_MEM) { |
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src = &achan->slave.src_addr; |
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dst = &mem_addr; |
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} else { |
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src = &mem_addr; |
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dst = &achan->slave.dst_addr; |
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} |
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do { |
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single_desc = desc; |
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single_desc->cmd = ADM_CMD_TYPE_SINGLE; |
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single_desc->src_addr = *src; |
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single_desc->dst_addr = *dst; |
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single_desc->len = (remainder > ADM_MAX_XFER) ? |
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ADM_MAX_XFER : remainder; |
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remainder -= single_desc->len; |
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*incr_addr += single_desc->len; |
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desc += sizeof(*single_desc); |
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} while (remainder); |
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/* set last command if this is the end of the whole transaction */ |
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if (sg_is_last(sg)) |
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single_desc->cmd |= ADM_CMD_LC; |
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|
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return desc; |
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} |
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/** |
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* adm_prep_slave_sg - Prep slave sg transaction |
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* |
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* @chan: dma channel |
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* @sgl: scatter gather list |
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* @sg_len: length of sg |
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* @direction: DMA transfer direction |
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* @flags: DMA flags |
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* @context: transfer context (unused) |
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*/ |
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static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, |
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struct scatterlist *sgl, |
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unsigned int sg_len, |
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enum dma_transfer_direction direction, |
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unsigned long flags, |
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void *context) |
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{ |
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struct adm_chan *achan = to_adm_chan(chan); |
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struct adm_device *adev = achan->adev; |
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struct adm_async_desc *async_desc; |
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struct scatterlist *sg; |
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dma_addr_t cple_addr; |
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u32 i, burst; |
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u32 single_count = 0, box_count = 0, crci = 0; |
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void *desc; |
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u32 *cple; |
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int blk_size = 0; |
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|
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if (!is_slave_direction(direction)) { |
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dev_err(adev->dev, "invalid dma direction\n"); |
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return NULL; |
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} |
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|
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/* |
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* get burst value from slave configuration |
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*/ |
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burst = (direction == DMA_MEM_TO_DEV) ? |
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achan->slave.dst_maxburst : |
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achan->slave.src_maxburst; |
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|
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/* if using flow control, validate burst and crci values */ |
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if (achan->slave.device_fc) { |
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blk_size = adm_get_blksize(burst); |
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if (blk_size < 0) { |
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dev_err(adev->dev, "invalid burst value: %d\n", |
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burst); |
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return ERR_PTR(-EINVAL); |
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} |
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|
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crci = achan->slave.slave_id & 0xf; |
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if (!crci || achan->slave.slave_id > 0x1f) { |
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dev_err(adev->dev, "invalid crci value\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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} |
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|
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/* iterate through sgs and compute allocation size of structures */ |
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for_each_sg(sgl, sg, sg_len, i) { |
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if (achan->slave.device_fc) { |
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box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, |
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ADM_MAX_ROWS); |
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if (sg_dma_len(sg) % burst) |
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single_count++; |
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} else { |
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single_count += DIV_ROUND_UP(sg_dma_len(sg), |
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ADM_MAX_XFER); |
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} |
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} |
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|
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async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT); |
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if (!async_desc) |
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return ERR_PTR(-ENOMEM); |
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|
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if (crci) |
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async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? |
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ADM_CRCI_CTL_MUX_SEL : 0; |
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async_desc->crci = crci; |
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async_desc->blk_size = blk_size; |
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async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + |
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box_count * sizeof(struct adm_desc_hw_box) + |
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sizeof(*cple) + 2 * ADM_DESC_ALIGN; |
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|
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async_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT); |
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if (!async_desc->cpl) |
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goto free; |
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async_desc->adev = adev; |
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|
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/* both command list entry and descriptors must be 8 byte aligned */ |
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cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); |
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desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); |
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|
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for_each_sg(sgl, sg, sg_len, i) { |
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async_desc->length += sg_dma_len(sg); |
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|
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if (achan->slave.device_fc) |
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desc = adm_process_fc_descriptors(achan, desc, sg, crci, |
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burst, direction); |
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else |
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desc = adm_process_non_fc_descriptors(achan, desc, sg, |
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direction); |
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} |
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|
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async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl, |
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async_desc->dma_len, |
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DMA_TO_DEVICE); |
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if (dma_mapping_error(adev->dev, async_desc->dma_addr)) |
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goto free; |
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|
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cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl); |
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|
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/* init cmd list */ |
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dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple), |
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DMA_TO_DEVICE); |
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*cple = ADM_CPLE_LP; |
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*cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3; |
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dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple), |
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DMA_TO_DEVICE); |
|
|
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return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); |
|
|
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free: |
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kfree(async_desc); |
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return ERR_PTR(-ENOMEM); |
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} |
|
|
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/** |
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* adm_terminate_all - terminate all transactions on a channel |
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* @chan: dma channel |
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* |
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* Dequeues and frees all transactions, aborts current transaction |
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* No callbacks are done |
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* |
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*/ |
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static int adm_terminate_all(struct dma_chan *chan) |
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{ |
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struct adm_chan *achan = to_adm_chan(chan); |
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struct adm_device *adev = achan->adev; |
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unsigned long flags; |
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LIST_HEAD(head); |
|
|
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spin_lock_irqsave(&achan->vc.lock, flags); |
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vchan_get_all_descriptors(&achan->vc, &head); |
|
|
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/* send flush command to terminate current transaction */ |
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writel_relaxed(0x0, |
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adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); |
|
|
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spin_unlock_irqrestore(&achan->vc.lock, flags); |
|
|
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vchan_dma_desc_free_list(&achan->vc, &head); |
|
|
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return 0; |
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} |
|
|
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static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
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{ |
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struct adm_chan *achan = to_adm_chan(chan); |
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unsigned long flag; |
|
|
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spin_lock_irqsave(&achan->vc.lock, flag); |
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memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); |
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spin_unlock_irqrestore(&achan->vc.lock, flag); |
|
|
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return 0; |
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} |
|
|
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/** |
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* adm_start_dma - start next transaction |
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* @achan: ADM dma channel |
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*/ |
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static void adm_start_dma(struct adm_chan *achan) |
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{ |
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struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); |
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struct adm_device *adev = achan->adev; |
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struct adm_async_desc *async_desc; |
|
|
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lockdep_assert_held(&achan->vc.lock); |
|
|
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if (!vd) |
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return; |
|
|
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list_del(&vd->node); |
|
|
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/* write next command list out to the CMD FIFO */ |
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async_desc = container_of(vd, struct adm_async_desc, vd); |
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achan->curr_txd = async_desc; |
|
|
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/* reset channel error */ |
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achan->error = 0; |
|
|
|
if (!achan->initialized) { |
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/* enable interrupts */ |
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writel(ADM_CH_CONF_SHADOW_EN | |
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ADM_CH_CONF_PERM_MPU_CONF | |
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ADM_CH_CONF_MPU_DISABLE | |
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ADM_CH_CONF_SEC_DOMAIN(adev->ee), |
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adev->regs + ADM_CH_CONF(achan->id)); |
|
|
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writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, |
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adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); |
|
|
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achan->initialized = 1; |
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} |
|
|
|
/* set the crci block size if this transaction requires CRCI */ |
|
if (async_desc->crci) { |
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writel(async_desc->mux | async_desc->blk_size, |
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adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); |
|
} |
|
|
|
/* make sure IRQ enable doesn't get reordered */ |
|
wmb(); |
|
|
|
/* write next command list out to the CMD FIFO */ |
|
writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, |
|
adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); |
|
} |
|
|
|
/** |
|
* adm_dma_irq - irq handler for ADM controller |
|
* @irq: IRQ of interrupt |
|
* @data: callback data |
|
* |
|
* IRQ handler for the bam controller |
|
*/ |
|
static irqreturn_t adm_dma_irq(int irq, void *data) |
|
{ |
|
struct adm_device *adev = data; |
|
u32 srcs, i; |
|
struct adm_async_desc *async_desc; |
|
unsigned long flags; |
|
|
|
srcs = readl_relaxed(adev->regs + |
|
ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); |
|
|
|
for (i = 0; i < ADM_MAX_CHANNELS; i++) { |
|
struct adm_chan *achan = &adev->channels[i]; |
|
u32 status, result; |
|
|
|
if (srcs & BIT(i)) { |
|
status = readl_relaxed(adev->regs + |
|
ADM_CH_STATUS_SD(i, adev->ee)); |
|
|
|
/* if no result present, skip */ |
|
if (!(status & ADM_CH_STATUS_VALID)) |
|
continue; |
|
|
|
result = readl_relaxed(adev->regs + |
|
ADM_CH_RSLT(i, adev->ee)); |
|
|
|
/* no valid results, skip */ |
|
if (!(result & ADM_CH_RSLT_VALID)) |
|
continue; |
|
|
|
/* flag error if transaction was flushed or failed */ |
|
if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) |
|
achan->error = 1; |
|
|
|
spin_lock_irqsave(&achan->vc.lock, flags); |
|
async_desc = achan->curr_txd; |
|
|
|
achan->curr_txd = NULL; |
|
|
|
if (async_desc) { |
|
vchan_cookie_complete(&async_desc->vd); |
|
|
|
/* kick off next DMA */ |
|
adm_start_dma(achan); |
|
} |
|
|
|
spin_unlock_irqrestore(&achan->vc.lock, flags); |
|
} |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
/** |
|
* adm_tx_status - returns status of transaction |
|
* @chan: dma channel |
|
* @cookie: transaction cookie |
|
* @txstate: DMA transaction state |
|
* |
|
* Return status of dma transaction |
|
*/ |
|
static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
|
struct dma_tx_state *txstate) |
|
{ |
|
struct adm_chan *achan = to_adm_chan(chan); |
|
struct virt_dma_desc *vd; |
|
enum dma_status ret; |
|
unsigned long flags; |
|
size_t residue = 0; |
|
|
|
ret = dma_cookie_status(chan, cookie, txstate); |
|
if (ret == DMA_COMPLETE || !txstate) |
|
return ret; |
|
|
|
spin_lock_irqsave(&achan->vc.lock, flags); |
|
|
|
vd = vchan_find_desc(&achan->vc, cookie); |
|
if (vd) |
|
residue = container_of(vd, struct adm_async_desc, vd)->length; |
|
|
|
spin_unlock_irqrestore(&achan->vc.lock, flags); |
|
|
|
/* |
|
* residue is either the full length if it is in the issued list, or 0 |
|
* if it is in progress. We have no reliable way of determining |
|
* anything inbetween |
|
*/ |
|
dma_set_residue(txstate, residue); |
|
|
|
if (achan->error) |
|
return DMA_ERROR; |
|
|
|
return ret; |
|
} |
|
|
|
/** |
|
* adm_issue_pending - starts pending transactions |
|
* @chan: dma channel |
|
* |
|
* Issues all pending transactions and starts DMA |
|
*/ |
|
static void adm_issue_pending(struct dma_chan *chan) |
|
{ |
|
struct adm_chan *achan = to_adm_chan(chan); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&achan->vc.lock, flags); |
|
|
|
if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) |
|
adm_start_dma(achan); |
|
spin_unlock_irqrestore(&achan->vc.lock, flags); |
|
} |
|
|
|
/** |
|
* adm_dma_free_desc - free descriptor memory |
|
* @vd: virtual descriptor |
|
* |
|
*/ |
|
static void adm_dma_free_desc(struct virt_dma_desc *vd) |
|
{ |
|
struct adm_async_desc *async_desc = container_of(vd, |
|
struct adm_async_desc, vd); |
|
|
|
dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr, |
|
async_desc->dma_len, DMA_TO_DEVICE); |
|
kfree(async_desc->cpl); |
|
kfree(async_desc); |
|
} |
|
|
|
static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, |
|
u32 index) |
|
{ |
|
achan->id = index; |
|
achan->adev = adev; |
|
|
|
vchan_init(&achan->vc, &adev->common); |
|
achan->vc.desc_free = adm_dma_free_desc; |
|
} |
|
|
|
static int adm_dma_probe(struct platform_device *pdev) |
|
{ |
|
struct adm_device *adev; |
|
int ret; |
|
u32 i; |
|
|
|
adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); |
|
if (!adev) |
|
return -ENOMEM; |
|
|
|
adev->dev = &pdev->dev; |
|
|
|
adev->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(adev->regs)) |
|
return PTR_ERR(adev->regs); |
|
|
|
adev->irq = platform_get_irq(pdev, 0); |
|
if (adev->irq < 0) |
|
return adev->irq; |
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); |
|
if (ret) { |
|
dev_err(adev->dev, "Execution environment unspecified\n"); |
|
return ret; |
|
} |
|
|
|
adev->core_clk = devm_clk_get(adev->dev, "core"); |
|
if (IS_ERR(adev->core_clk)) |
|
return PTR_ERR(adev->core_clk); |
|
|
|
adev->iface_clk = devm_clk_get(adev->dev, "iface"); |
|
if (IS_ERR(adev->iface_clk)) |
|
return PTR_ERR(adev->iface_clk); |
|
|
|
adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk"); |
|
if (IS_ERR(adev->clk_reset)) { |
|
dev_err(adev->dev, "failed to get ADM0 reset\n"); |
|
return PTR_ERR(adev->clk_reset); |
|
} |
|
|
|
adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0"); |
|
if (IS_ERR(adev->c0_reset)) { |
|
dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); |
|
return PTR_ERR(adev->c0_reset); |
|
} |
|
|
|
adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1"); |
|
if (IS_ERR(adev->c1_reset)) { |
|
dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); |
|
return PTR_ERR(adev->c1_reset); |
|
} |
|
|
|
adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2"); |
|
if (IS_ERR(adev->c2_reset)) { |
|
dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); |
|
return PTR_ERR(adev->c2_reset); |
|
} |
|
|
|
ret = clk_prepare_enable(adev->core_clk); |
|
if (ret) { |
|
dev_err(adev->dev, "failed to prepare/enable core clock\n"); |
|
return ret; |
|
} |
|
|
|
ret = clk_prepare_enable(adev->iface_clk); |
|
if (ret) { |
|
dev_err(adev->dev, "failed to prepare/enable iface clock\n"); |
|
goto err_disable_core_clk; |
|
} |
|
|
|
reset_control_assert(adev->clk_reset); |
|
reset_control_assert(adev->c0_reset); |
|
reset_control_assert(adev->c1_reset); |
|
reset_control_assert(adev->c2_reset); |
|
|
|
udelay(2); |
|
|
|
reset_control_deassert(adev->clk_reset); |
|
reset_control_deassert(adev->c0_reset); |
|
reset_control_deassert(adev->c1_reset); |
|
reset_control_deassert(adev->c2_reset); |
|
|
|
adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, |
|
sizeof(*adev->channels), GFP_KERNEL); |
|
|
|
if (!adev->channels) { |
|
ret = -ENOMEM; |
|
goto err_disable_clks; |
|
} |
|
|
|
/* allocate and initialize channels */ |
|
INIT_LIST_HEAD(&adev->common.channels); |
|
|
|
for (i = 0; i < ADM_MAX_CHANNELS; i++) |
|
adm_channel_init(adev, &adev->channels[i], i); |
|
|
|
/* reset CRCIs */ |
|
for (i = 0; i < 16; i++) |
|
writel(ADM_CRCI_CTL_RST, adev->regs + |
|
ADM_CRCI_CTL(i, adev->ee)); |
|
|
|
/* configure client interfaces */ |
|
writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | |
|
ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); |
|
writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | |
|
ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); |
|
writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | |
|
ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); |
|
writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), |
|
adev->regs + ADM_GP_CTL); |
|
|
|
ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, |
|
0, "adm_dma", adev); |
|
if (ret) |
|
goto err_disable_clks; |
|
|
|
platform_set_drvdata(pdev, adev); |
|
|
|
adev->common.dev = adev->dev; |
|
adev->common.dev->dma_parms = &adev->dma_parms; |
|
|
|
/* set capabilities */ |
|
dma_cap_zero(adev->common.cap_mask); |
|
dma_cap_set(DMA_SLAVE, adev->common.cap_mask); |
|
dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); |
|
|
|
/* initialize dmaengine apis */ |
|
adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); |
|
adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
|
adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
adev->common.device_free_chan_resources = adm_free_chan; |
|
adev->common.device_prep_slave_sg = adm_prep_slave_sg; |
|
adev->common.device_issue_pending = adm_issue_pending; |
|
adev->common.device_tx_status = adm_tx_status; |
|
adev->common.device_terminate_all = adm_terminate_all; |
|
adev->common.device_config = adm_slave_config; |
|
|
|
ret = dma_async_device_register(&adev->common); |
|
if (ret) { |
|
dev_err(adev->dev, "failed to register dma async device\n"); |
|
goto err_disable_clks; |
|
} |
|
|
|
ret = of_dma_controller_register(pdev->dev.of_node, |
|
of_dma_xlate_by_chan_id, |
|
&adev->common); |
|
if (ret) |
|
goto err_unregister_dma; |
|
|
|
return 0; |
|
|
|
err_unregister_dma: |
|
dma_async_device_unregister(&adev->common); |
|
err_disable_clks: |
|
clk_disable_unprepare(adev->iface_clk); |
|
err_disable_core_clk: |
|
clk_disable_unprepare(adev->core_clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int adm_dma_remove(struct platform_device *pdev) |
|
{ |
|
struct adm_device *adev = platform_get_drvdata(pdev); |
|
struct adm_chan *achan; |
|
u32 i; |
|
|
|
of_dma_controller_free(pdev->dev.of_node); |
|
dma_async_device_unregister(&adev->common); |
|
|
|
for (i = 0; i < ADM_MAX_CHANNELS; i++) { |
|
achan = &adev->channels[i]; |
|
|
|
/* mask IRQs for this channel/EE pair */ |
|
writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); |
|
|
|
tasklet_kill(&adev->channels[i].vc.task); |
|
adm_terminate_all(&adev->channels[i].vc.chan); |
|
} |
|
|
|
devm_free_irq(adev->dev, adev->irq, adev); |
|
|
|
clk_disable_unprepare(adev->core_clk); |
|
clk_disable_unprepare(adev->iface_clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id adm_of_match[] = { |
|
{ .compatible = "qcom,adm", }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, adm_of_match); |
|
|
|
static struct platform_driver adm_dma_driver = { |
|
.probe = adm_dma_probe, |
|
.remove = adm_dma_remove, |
|
.driver = { |
|
.name = "adm-dma-engine", |
|
.of_match_table = adm_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(adm_dma_driver); |
|
|
|
MODULE_AUTHOR("Andy Gross <[email protected]>"); |
|
MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|