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642 lines
15 KiB
642 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Microsemi Switchtec(tm) PCIe Management Driver |
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* Copyright (c) 2019, Logan Gunthorpe <[email protected]> |
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* Copyright (c) 2019, GigaIO Networks, Inc |
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*/ |
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#include "dmaengine.h" |
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#include <linux/circ_buf.h> |
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#include <linux/dmaengine.h> |
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#include <linux/kref.h> |
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#include <linux/list.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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MODULE_DESCRIPTION("PLX ExpressLane PEX PCI Switch DMA Engine"); |
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MODULE_VERSION("0.1"); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Logan Gunthorpe"); |
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#define PLX_REG_DESC_RING_ADDR 0x214 |
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#define PLX_REG_DESC_RING_ADDR_HI 0x218 |
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#define PLX_REG_DESC_RING_NEXT_ADDR 0x21C |
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#define PLX_REG_DESC_RING_COUNT 0x220 |
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#define PLX_REG_DESC_RING_LAST_ADDR 0x224 |
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#define PLX_REG_DESC_RING_LAST_SIZE 0x228 |
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#define PLX_REG_PREF_LIMIT 0x234 |
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#define PLX_REG_CTRL 0x238 |
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#define PLX_REG_CTRL2 0x23A |
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#define PLX_REG_INTR_CTRL 0x23C |
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#define PLX_REG_INTR_STATUS 0x23E |
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#define PLX_REG_PREF_LIMIT_PREF_FOUR 8 |
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#define PLX_REG_CTRL_GRACEFUL_PAUSE BIT(0) |
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#define PLX_REG_CTRL_ABORT BIT(1) |
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#define PLX_REG_CTRL_WRITE_BACK_EN BIT(2) |
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#define PLX_REG_CTRL_START BIT(3) |
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#define PLX_REG_CTRL_RING_STOP_MODE BIT(4) |
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#define PLX_REG_CTRL_DESC_MODE_BLOCK (0 << 5) |
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#define PLX_REG_CTRL_DESC_MODE_ON_CHIP (1 << 5) |
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#define PLX_REG_CTRL_DESC_MODE_OFF_CHIP (2 << 5) |
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#define PLX_REG_CTRL_DESC_INVALID BIT(8) |
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#define PLX_REG_CTRL_GRACEFUL_PAUSE_DONE BIT(9) |
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#define PLX_REG_CTRL_ABORT_DONE BIT(10) |
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#define PLX_REG_CTRL_IMM_PAUSE_DONE BIT(12) |
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#define PLX_REG_CTRL_IN_PROGRESS BIT(30) |
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#define PLX_REG_CTRL_RESET_VAL (PLX_REG_CTRL_DESC_INVALID | \ |
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PLX_REG_CTRL_GRACEFUL_PAUSE_DONE | \ |
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PLX_REG_CTRL_ABORT_DONE | \ |
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PLX_REG_CTRL_IMM_PAUSE_DONE) |
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#define PLX_REG_CTRL_START_VAL (PLX_REG_CTRL_WRITE_BACK_EN | \ |
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PLX_REG_CTRL_DESC_MODE_OFF_CHIP | \ |
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PLX_REG_CTRL_START | \ |
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PLX_REG_CTRL_RESET_VAL) |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_64B 0 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_128B 1 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_256B 2 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_512B 3 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_1KB 4 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_2KB 5 |
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#define PLX_REG_CTRL2_MAX_TXFR_SIZE_4B 7 |
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#define PLX_REG_INTR_CRTL_ERROR_EN BIT(0) |
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#define PLX_REG_INTR_CRTL_INV_DESC_EN BIT(1) |
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#define PLX_REG_INTR_CRTL_ABORT_DONE_EN BIT(3) |
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#define PLX_REG_INTR_CRTL_PAUSE_DONE_EN BIT(4) |
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#define PLX_REG_INTR_CRTL_IMM_PAUSE_DONE_EN BIT(5) |
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#define PLX_REG_INTR_STATUS_ERROR BIT(0) |
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#define PLX_REG_INTR_STATUS_INV_DESC BIT(1) |
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#define PLX_REG_INTR_STATUS_DESC_DONE BIT(2) |
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#define PLX_REG_INTR_CRTL_ABORT_DONE BIT(3) |
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struct plx_dma_hw_std_desc { |
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__le32 flags_and_size; |
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__le16 dst_addr_hi; |
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__le16 src_addr_hi; |
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__le32 dst_addr_lo; |
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__le32 src_addr_lo; |
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}; |
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#define PLX_DESC_SIZE_MASK 0x7ffffff |
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#define PLX_DESC_FLAG_VALID BIT(31) |
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#define PLX_DESC_FLAG_INT_WHEN_DONE BIT(30) |
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#define PLX_DESC_WB_SUCCESS BIT(30) |
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#define PLX_DESC_WB_RD_FAIL BIT(29) |
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#define PLX_DESC_WB_WR_FAIL BIT(28) |
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#define PLX_DMA_RING_COUNT 2048 |
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struct plx_dma_desc { |
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struct dma_async_tx_descriptor txd; |
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struct plx_dma_hw_std_desc *hw; |
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u32 orig_size; |
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}; |
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struct plx_dma_dev { |
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struct dma_device dma_dev; |
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struct dma_chan dma_chan; |
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struct pci_dev __rcu *pdev; |
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void __iomem *bar; |
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struct tasklet_struct desc_task; |
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spinlock_t ring_lock; |
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bool ring_active; |
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int head; |
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int tail; |
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struct plx_dma_hw_std_desc *hw_ring; |
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dma_addr_t hw_ring_dma; |
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struct plx_dma_desc **desc_ring; |
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}; |
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static struct plx_dma_dev *chan_to_plx_dma_dev(struct dma_chan *c) |
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{ |
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return container_of(c, struct plx_dma_dev, dma_chan); |
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} |
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static struct plx_dma_desc *to_plx_desc(struct dma_async_tx_descriptor *txd) |
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{ |
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return container_of(txd, struct plx_dma_desc, txd); |
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} |
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static struct plx_dma_desc *plx_dma_get_desc(struct plx_dma_dev *plxdev, int i) |
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{ |
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return plxdev->desc_ring[i & (PLX_DMA_RING_COUNT - 1)]; |
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} |
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static void plx_dma_process_desc(struct plx_dma_dev *plxdev) |
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{ |
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struct dmaengine_result res; |
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struct plx_dma_desc *desc; |
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u32 flags; |
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spin_lock_bh(&plxdev->ring_lock); |
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while (plxdev->tail != plxdev->head) { |
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desc = plx_dma_get_desc(plxdev, plxdev->tail); |
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flags = le32_to_cpu(READ_ONCE(desc->hw->flags_and_size)); |
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if (flags & PLX_DESC_FLAG_VALID) |
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break; |
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res.residue = desc->orig_size - (flags & PLX_DESC_SIZE_MASK); |
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if (flags & PLX_DESC_WB_SUCCESS) |
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res.result = DMA_TRANS_NOERROR; |
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else if (flags & PLX_DESC_WB_WR_FAIL) |
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res.result = DMA_TRANS_WRITE_FAILED; |
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else |
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res.result = DMA_TRANS_READ_FAILED; |
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dma_cookie_complete(&desc->txd); |
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dma_descriptor_unmap(&desc->txd); |
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dmaengine_desc_get_callback_invoke(&desc->txd, &res); |
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desc->txd.callback = NULL; |
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desc->txd.callback_result = NULL; |
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plxdev->tail++; |
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} |
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spin_unlock_bh(&plxdev->ring_lock); |
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} |
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static void plx_dma_abort_desc(struct plx_dma_dev *plxdev) |
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{ |
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struct dmaengine_result res; |
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struct plx_dma_desc *desc; |
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plx_dma_process_desc(plxdev); |
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spin_lock_bh(&plxdev->ring_lock); |
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while (plxdev->tail != plxdev->head) { |
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desc = plx_dma_get_desc(plxdev, plxdev->tail); |
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res.residue = desc->orig_size; |
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res.result = DMA_TRANS_ABORTED; |
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dma_cookie_complete(&desc->txd); |
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dma_descriptor_unmap(&desc->txd); |
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dmaengine_desc_get_callback_invoke(&desc->txd, &res); |
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desc->txd.callback = NULL; |
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desc->txd.callback_result = NULL; |
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plxdev->tail++; |
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} |
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spin_unlock_bh(&plxdev->ring_lock); |
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} |
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static void __plx_dma_stop(struct plx_dma_dev *plxdev) |
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{ |
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unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
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u32 val; |
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val = readl(plxdev->bar + PLX_REG_CTRL); |
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if (!(val & ~PLX_REG_CTRL_GRACEFUL_PAUSE)) |
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return; |
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writel(PLX_REG_CTRL_RESET_VAL | PLX_REG_CTRL_GRACEFUL_PAUSE, |
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plxdev->bar + PLX_REG_CTRL); |
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while (!time_after(jiffies, timeout)) { |
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val = readl(plxdev->bar + PLX_REG_CTRL); |
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if (val & PLX_REG_CTRL_GRACEFUL_PAUSE_DONE) |
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break; |
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cpu_relax(); |
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} |
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if (!(val & PLX_REG_CTRL_GRACEFUL_PAUSE_DONE)) |
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dev_err(plxdev->dma_dev.dev, |
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"Timeout waiting for graceful pause!\n"); |
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writel(PLX_REG_CTRL_RESET_VAL | PLX_REG_CTRL_GRACEFUL_PAUSE, |
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plxdev->bar + PLX_REG_CTRL); |
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writel(0, plxdev->bar + PLX_REG_DESC_RING_COUNT); |
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writel(0, plxdev->bar + PLX_REG_DESC_RING_ADDR); |
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writel(0, plxdev->bar + PLX_REG_DESC_RING_ADDR_HI); |
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writel(0, plxdev->bar + PLX_REG_DESC_RING_NEXT_ADDR); |
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} |
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static void plx_dma_stop(struct plx_dma_dev *plxdev) |
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{ |
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rcu_read_lock(); |
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if (!rcu_dereference(plxdev->pdev)) { |
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rcu_read_unlock(); |
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return; |
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} |
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__plx_dma_stop(plxdev); |
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rcu_read_unlock(); |
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} |
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static void plx_dma_desc_task(struct tasklet_struct *t) |
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{ |
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struct plx_dma_dev *plxdev = from_tasklet(plxdev, t, desc_task); |
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plx_dma_process_desc(plxdev); |
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} |
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static struct dma_async_tx_descriptor *plx_dma_prep_memcpy(struct dma_chan *c, |
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dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, |
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unsigned long flags) |
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__acquires(plxdev->ring_lock) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(c); |
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struct plx_dma_desc *plxdesc; |
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spin_lock_bh(&plxdev->ring_lock); |
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if (!plxdev->ring_active) |
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goto err_unlock; |
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if (!CIRC_SPACE(plxdev->head, plxdev->tail, PLX_DMA_RING_COUNT)) |
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goto err_unlock; |
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if (len > PLX_DESC_SIZE_MASK) |
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goto err_unlock; |
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plxdesc = plx_dma_get_desc(plxdev, plxdev->head); |
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plxdev->head++; |
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plxdesc->hw->dst_addr_lo = cpu_to_le32(lower_32_bits(dma_dst)); |
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plxdesc->hw->dst_addr_hi = cpu_to_le16(upper_32_bits(dma_dst)); |
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plxdesc->hw->src_addr_lo = cpu_to_le32(lower_32_bits(dma_src)); |
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plxdesc->hw->src_addr_hi = cpu_to_le16(upper_32_bits(dma_src)); |
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plxdesc->orig_size = len; |
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if (flags & DMA_PREP_INTERRUPT) |
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len |= PLX_DESC_FLAG_INT_WHEN_DONE; |
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plxdesc->hw->flags_and_size = cpu_to_le32(len); |
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plxdesc->txd.flags = flags; |
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/* return with the lock held, it will be released in tx_submit */ |
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return &plxdesc->txd; |
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err_unlock: |
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/* |
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* Keep sparse happy by restoring an even lock count on |
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* this lock. |
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*/ |
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__acquire(plxdev->ring_lock); |
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spin_unlock_bh(&plxdev->ring_lock); |
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return NULL; |
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} |
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static dma_cookie_t plx_dma_tx_submit(struct dma_async_tx_descriptor *desc) |
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__releases(plxdev->ring_lock) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(desc->chan); |
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struct plx_dma_desc *plxdesc = to_plx_desc(desc); |
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dma_cookie_t cookie; |
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cookie = dma_cookie_assign(desc); |
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/* |
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* Ensure the descriptor updates are visible to the dma device |
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* before setting the valid bit. |
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*/ |
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wmb(); |
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plxdesc->hw->flags_and_size |= cpu_to_le32(PLX_DESC_FLAG_VALID); |
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spin_unlock_bh(&plxdev->ring_lock); |
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return cookie; |
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} |
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static enum dma_status plx_dma_tx_status(struct dma_chan *chan, |
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dma_cookie_t cookie, struct dma_tx_state *txstate) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); |
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enum dma_status ret; |
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ret = dma_cookie_status(chan, cookie, txstate); |
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if (ret == DMA_COMPLETE) |
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return ret; |
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plx_dma_process_desc(plxdev); |
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return dma_cookie_status(chan, cookie, txstate); |
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} |
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static void plx_dma_issue_pending(struct dma_chan *chan) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); |
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rcu_read_lock(); |
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if (!rcu_dereference(plxdev->pdev)) { |
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rcu_read_unlock(); |
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return; |
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} |
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/* |
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* Ensure the valid bits are visible before starting the |
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* DMA engine. |
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*/ |
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wmb(); |
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writew(PLX_REG_CTRL_START_VAL, plxdev->bar + PLX_REG_CTRL); |
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rcu_read_unlock(); |
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} |
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static irqreturn_t plx_dma_isr(int irq, void *devid) |
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{ |
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struct plx_dma_dev *plxdev = devid; |
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u32 status; |
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status = readw(plxdev->bar + PLX_REG_INTR_STATUS); |
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if (!status) |
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return IRQ_NONE; |
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if (status & PLX_REG_INTR_STATUS_DESC_DONE && plxdev->ring_active) |
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tasklet_schedule(&plxdev->desc_task); |
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writew(status, plxdev->bar + PLX_REG_INTR_STATUS); |
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return IRQ_HANDLED; |
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} |
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static int plx_dma_alloc_desc(struct plx_dma_dev *plxdev) |
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{ |
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struct plx_dma_desc *desc; |
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int i; |
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plxdev->desc_ring = kcalloc(PLX_DMA_RING_COUNT, |
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sizeof(*plxdev->desc_ring), GFP_KERNEL); |
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if (!plxdev->desc_ring) |
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return -ENOMEM; |
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for (i = 0; i < PLX_DMA_RING_COUNT; i++) { |
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desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
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if (!desc) |
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goto free_and_exit; |
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dma_async_tx_descriptor_init(&desc->txd, &plxdev->dma_chan); |
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desc->txd.tx_submit = plx_dma_tx_submit; |
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desc->hw = &plxdev->hw_ring[i]; |
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plxdev->desc_ring[i] = desc; |
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} |
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return 0; |
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free_and_exit: |
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for (i = 0; i < PLX_DMA_RING_COUNT; i++) |
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kfree(plxdev->desc_ring[i]); |
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kfree(plxdev->desc_ring); |
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return -ENOMEM; |
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} |
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static int plx_dma_alloc_chan_resources(struct dma_chan *chan) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); |
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size_t ring_sz = PLX_DMA_RING_COUNT * sizeof(*plxdev->hw_ring); |
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int rc; |
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plxdev->head = plxdev->tail = 0; |
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plxdev->hw_ring = dma_alloc_coherent(plxdev->dma_dev.dev, ring_sz, |
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&plxdev->hw_ring_dma, GFP_KERNEL); |
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if (!plxdev->hw_ring) |
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return -ENOMEM; |
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rc = plx_dma_alloc_desc(plxdev); |
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if (rc) |
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goto out_free_hw_ring; |
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rcu_read_lock(); |
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if (!rcu_dereference(plxdev->pdev)) { |
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rcu_read_unlock(); |
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rc = -ENODEV; |
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goto out_free_hw_ring; |
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} |
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writel(PLX_REG_CTRL_RESET_VAL, plxdev->bar + PLX_REG_CTRL); |
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writel(lower_32_bits(plxdev->hw_ring_dma), |
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plxdev->bar + PLX_REG_DESC_RING_ADDR); |
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writel(upper_32_bits(plxdev->hw_ring_dma), |
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plxdev->bar + PLX_REG_DESC_RING_ADDR_HI); |
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writel(lower_32_bits(plxdev->hw_ring_dma), |
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plxdev->bar + PLX_REG_DESC_RING_NEXT_ADDR); |
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writel(PLX_DMA_RING_COUNT, plxdev->bar + PLX_REG_DESC_RING_COUNT); |
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writel(PLX_REG_PREF_LIMIT_PREF_FOUR, plxdev->bar + PLX_REG_PREF_LIMIT); |
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plxdev->ring_active = true; |
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rcu_read_unlock(); |
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return PLX_DMA_RING_COUNT; |
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out_free_hw_ring: |
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dma_free_coherent(plxdev->dma_dev.dev, ring_sz, plxdev->hw_ring, |
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plxdev->hw_ring_dma); |
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return rc; |
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} |
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static void plx_dma_free_chan_resources(struct dma_chan *chan) |
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{ |
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struct plx_dma_dev *plxdev = chan_to_plx_dma_dev(chan); |
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size_t ring_sz = PLX_DMA_RING_COUNT * sizeof(*plxdev->hw_ring); |
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struct pci_dev *pdev; |
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int irq = -1; |
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int i; |
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spin_lock_bh(&plxdev->ring_lock); |
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plxdev->ring_active = false; |
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spin_unlock_bh(&plxdev->ring_lock); |
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plx_dma_stop(plxdev); |
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rcu_read_lock(); |
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pdev = rcu_dereference(plxdev->pdev); |
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if (pdev) |
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irq = pci_irq_vector(pdev, 0); |
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rcu_read_unlock(); |
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if (irq > 0) |
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synchronize_irq(irq); |
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tasklet_kill(&plxdev->desc_task); |
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plx_dma_abort_desc(plxdev); |
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for (i = 0; i < PLX_DMA_RING_COUNT; i++) |
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kfree(plxdev->desc_ring[i]); |
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kfree(plxdev->desc_ring); |
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dma_free_coherent(plxdev->dma_dev.dev, ring_sz, plxdev->hw_ring, |
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plxdev->hw_ring_dma); |
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} |
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static void plx_dma_release(struct dma_device *dma_dev) |
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{ |
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struct plx_dma_dev *plxdev = |
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container_of(dma_dev, struct plx_dma_dev, dma_dev); |
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put_device(dma_dev->dev); |
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kfree(plxdev); |
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} |
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static int plx_dma_create(struct pci_dev *pdev) |
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{ |
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struct plx_dma_dev *plxdev; |
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struct dma_device *dma; |
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struct dma_chan *chan; |
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int rc; |
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plxdev = kzalloc(sizeof(*plxdev), GFP_KERNEL); |
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if (!plxdev) |
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return -ENOMEM; |
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rc = request_irq(pci_irq_vector(pdev, 0), plx_dma_isr, 0, |
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KBUILD_MODNAME, plxdev); |
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if (rc) |
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goto free_plx; |
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spin_lock_init(&plxdev->ring_lock); |
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tasklet_setup(&plxdev->desc_task, plx_dma_desc_task); |
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RCU_INIT_POINTER(plxdev->pdev, pdev); |
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plxdev->bar = pcim_iomap_table(pdev)[0]; |
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|
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dma = &plxdev->dma_dev; |
|
dma->chancnt = 1; |
|
INIT_LIST_HEAD(&dma->channels); |
|
dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
|
dma->copy_align = DMAENGINE_ALIGN_1_BYTE; |
|
dma->dev = get_device(&pdev->dev); |
|
|
|
dma->device_alloc_chan_resources = plx_dma_alloc_chan_resources; |
|
dma->device_free_chan_resources = plx_dma_free_chan_resources; |
|
dma->device_prep_dma_memcpy = plx_dma_prep_memcpy; |
|
dma->device_issue_pending = plx_dma_issue_pending; |
|
dma->device_tx_status = plx_dma_tx_status; |
|
dma->device_release = plx_dma_release; |
|
|
|
chan = &plxdev->dma_chan; |
|
chan->device = dma; |
|
dma_cookie_init(chan); |
|
list_add_tail(&chan->device_node, &dma->channels); |
|
|
|
rc = dma_async_device_register(dma); |
|
if (rc) { |
|
pci_err(pdev, "Failed to register dma device: %d\n", rc); |
|
goto put_device; |
|
} |
|
|
|
pci_set_drvdata(pdev, plxdev); |
|
|
|
return 0; |
|
|
|
put_device: |
|
put_device(&pdev->dev); |
|
free_irq(pci_irq_vector(pdev, 0), plxdev); |
|
free_plx: |
|
kfree(plxdev); |
|
|
|
return rc; |
|
} |
|
|
|
static int plx_dma_probe(struct pci_dev *pdev, |
|
const struct pci_device_id *id) |
|
{ |
|
int rc; |
|
|
|
rc = pcim_enable_device(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); |
|
if (rc) |
|
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); |
|
if (rc) |
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pcim_iomap_regions(pdev, 1, KBUILD_MODNAME); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
|
if (rc <= 0) |
|
return rc; |
|
|
|
pci_set_master(pdev); |
|
|
|
rc = plx_dma_create(pdev); |
|
if (rc) |
|
goto err_free_irq_vectors; |
|
|
|
pci_info(pdev, "PLX DMA Channel Registered\n"); |
|
|
|
return 0; |
|
|
|
err_free_irq_vectors: |
|
pci_free_irq_vectors(pdev); |
|
return rc; |
|
} |
|
|
|
static void plx_dma_remove(struct pci_dev *pdev) |
|
{ |
|
struct plx_dma_dev *plxdev = pci_get_drvdata(pdev); |
|
|
|
free_irq(pci_irq_vector(pdev, 0), plxdev); |
|
|
|
rcu_assign_pointer(plxdev->pdev, NULL); |
|
synchronize_rcu(); |
|
|
|
spin_lock_bh(&plxdev->ring_lock); |
|
plxdev->ring_active = false; |
|
spin_unlock_bh(&plxdev->ring_lock); |
|
|
|
__plx_dma_stop(plxdev); |
|
plx_dma_abort_desc(plxdev); |
|
|
|
plxdev->bar = NULL; |
|
dma_async_device_unregister(&plxdev->dma_dev); |
|
|
|
pci_free_irq_vectors(pdev); |
|
} |
|
|
|
static const struct pci_device_id plx_dma_pci_tbl[] = { |
|
{ |
|
.vendor = PCI_VENDOR_ID_PLX, |
|
.device = 0x87D0, |
|
.subvendor = PCI_ANY_ID, |
|
.subdevice = PCI_ANY_ID, |
|
.class = PCI_CLASS_SYSTEM_OTHER << 8, |
|
.class_mask = 0xFFFFFFFF, |
|
}, |
|
{0} |
|
}; |
|
MODULE_DEVICE_TABLE(pci, plx_dma_pci_tbl); |
|
|
|
static struct pci_driver plx_dma_pci_driver = { |
|
.name = KBUILD_MODNAME, |
|
.id_table = plx_dma_pci_tbl, |
|
.probe = plx_dma_probe, |
|
.remove = plx_dma_remove, |
|
}; |
|
module_pci_driver(plx_dma_pci_driver);
|
|
|