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677 lines
17 KiB
677 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/crypto.h> |
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#include <linux/moduleparam.h> |
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#include <linux/types.h> |
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#include <linux/interrupt.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/pm_runtime.h> |
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#include "cc_driver.h" |
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#include "cc_request_mgr.h" |
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#include "cc_buffer_mgr.h" |
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#include "cc_debugfs.h" |
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#include "cc_cipher.h" |
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#include "cc_aead.h" |
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#include "cc_hash.h" |
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#include "cc_sram_mgr.h" |
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#include "cc_pm.h" |
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#include "cc_fips.h" |
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bool cc_dump_desc; |
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module_param_named(dump_desc, cc_dump_desc, bool, 0600); |
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MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid"); |
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bool cc_dump_bytes; |
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module_param_named(dump_bytes, cc_dump_bytes, bool, 0600); |
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MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid"); |
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static bool cc_sec_disable; |
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module_param_named(sec_disable, cc_sec_disable, bool, 0600); |
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MODULE_PARM_DESC(cc_sec_disable, "Disable security functions"); |
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struct cc_hw_data { |
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char *name; |
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enum cc_hw_rev rev; |
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u32 sig; |
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u32 cidr_0123; |
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u32 pidr_0124; |
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int std_bodies; |
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}; |
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#define CC_NUM_IDRS 4 |
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#define CC_HW_RESET_LOOP_COUNT 10 |
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/* Note: PIDR3 holds CMOD/Rev so ignored for HW identification purposes */ |
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static const u32 pidr_0124_offsets[CC_NUM_IDRS] = { |
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CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1), |
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CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4) |
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}; |
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static const u32 cidr_0123_offsets[CC_NUM_IDRS] = { |
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CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1), |
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CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3) |
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}; |
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/* Hardware revisions defs. */ |
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/* The 703 is a OSCCA only variant of the 713 */ |
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static const struct cc_hw_data cc703_hw = { |
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.name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, |
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.pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA |
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}; |
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static const struct cc_hw_data cc713_hw = { |
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.name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU, |
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.pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL |
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}; |
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static const struct cc_hw_data cc712_hw = { |
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.name = "712", .rev = CC_HW_REV_712, .sig = 0xDCC71200U, |
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.std_bodies = CC_STD_ALL |
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}; |
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static const struct cc_hw_data cc710_hw = { |
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.name = "710", .rev = CC_HW_REV_710, .sig = 0xDCC63200U, |
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.std_bodies = CC_STD_ALL |
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}; |
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static const struct cc_hw_data cc630p_hw = { |
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.name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U, |
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.std_bodies = CC_STD_ALL |
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}; |
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static const struct of_device_id arm_ccree_dev_of_match[] = { |
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{ .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw }, |
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{ .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw }, |
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{ .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw }, |
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{ .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw }, |
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{ .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match); |
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static void init_cc_cache_params(struct cc_drvdata *drvdata) |
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{ |
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struct device *dev = drvdata_to_dev(drvdata); |
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u32 cache_params, ace_const, val, mask; |
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/* compute CC_AXIM_CACHE_PARAMS */ |
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cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS)); |
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dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params); |
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/* non cached or write-back, write allocate */ |
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val = drvdata->coherent ? 0xb : 0x2; |
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mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE); |
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cache_params &= ~mask; |
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cache_params |= FIELD_PREP(mask, val); |
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mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE_LAST); |
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cache_params &= ~mask; |
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cache_params |= FIELD_PREP(mask, val); |
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mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_ARCACHE); |
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cache_params &= ~mask; |
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cache_params |= FIELD_PREP(mask, val); |
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drvdata->cache_params = cache_params; |
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dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params); |
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if (drvdata->hw_rev <= CC_HW_REV_710) |
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return; |
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/* compute CC_AXIM_ACE_CONST */ |
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ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST)); |
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dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const); |
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/* system or outer-sharable */ |
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val = drvdata->coherent ? 0x2 : 0x3; |
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mask = CC_GENMASK(CC_AXIM_ACE_CONST_ARDOMAIN); |
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ace_const &= ~mask; |
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ace_const |= FIELD_PREP(mask, val); |
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mask = CC_GENMASK(CC_AXIM_ACE_CONST_AWDOMAIN); |
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ace_const &= ~mask; |
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ace_const |= FIELD_PREP(mask, val); |
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dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const); |
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drvdata->ace_const = ace_const; |
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} |
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static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets) |
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{ |
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int i; |
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union { |
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u8 regs[CC_NUM_IDRS]; |
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__le32 val; |
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} idr; |
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for (i = 0; i < CC_NUM_IDRS; ++i) |
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idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]); |
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return le32_to_cpu(idr.val); |
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} |
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void __dump_byte_array(const char *name, const u8 *buf, size_t len) |
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{ |
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char prefix[64]; |
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if (!buf) |
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return; |
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snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len); |
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print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf, |
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len, false); |
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} |
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static irqreturn_t cc_isr(int irq, void *dev_id) |
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{ |
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struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id; |
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struct device *dev = drvdata_to_dev(drvdata); |
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u32 irr; |
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u32 imr; |
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/* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ |
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/* if driver suspended return, probably shared interrupt */ |
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if (pm_runtime_suspended(dev)) |
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return IRQ_NONE; |
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/* read the interrupt status */ |
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irr = cc_ioread(drvdata, CC_REG(HOST_IRR)); |
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dev_dbg(dev, "Got IRR=0x%08X\n", irr); |
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if (irr == 0) /* Probably shared interrupt line */ |
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return IRQ_NONE; |
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imr = cc_ioread(drvdata, CC_REG(HOST_IMR)); |
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/* clear interrupt - must be before processing events */ |
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cc_iowrite(drvdata, CC_REG(HOST_ICR), irr); |
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drvdata->irq = irr; |
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/* Completion interrupt - most probable */ |
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if (irr & drvdata->comp_mask) { |
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/* Mask all completion interrupts - will be unmasked in |
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* deferred service handler |
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*/ |
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask); |
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irr &= ~drvdata->comp_mask; |
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complete_request(drvdata); |
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} |
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#ifdef CONFIG_CRYPTO_FIPS |
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/* TEE FIPS interrupt */ |
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if (irr & CC_GPR0_IRQ_MASK) { |
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/* Mask interrupt - will be unmasked in Deferred service |
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* handler |
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*/ |
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK); |
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irr &= ~CC_GPR0_IRQ_MASK; |
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fips_handler(drvdata); |
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} |
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#endif |
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/* AXI error interrupt */ |
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if (irr & CC_AXI_ERR_IRQ_MASK) { |
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u32 axi_err; |
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/* Read the AXI error ID */ |
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axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR)); |
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dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n", |
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axi_err); |
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irr &= ~CC_AXI_ERR_IRQ_MASK; |
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} |
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if (irr) { |
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dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n", |
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irr); |
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/* Just warning */ |
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} |
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return IRQ_HANDLED; |
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} |
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bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata) |
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{ |
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unsigned int val; |
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unsigned int i; |
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/* 712/710/63 has no reset completion indication, always return true */ |
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if (drvdata->hw_rev <= CC_HW_REV_712) |
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return true; |
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for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) { |
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/* in cc7x3 NVM_IS_IDLE indicates that CC reset is |
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* completed and device is fully functional |
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*/ |
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val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE)); |
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if (val & CC_NVM_IS_IDLE_MASK) { |
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/* hw indicate reset completed */ |
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return true; |
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} |
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/* allow scheduling other process on the processor */ |
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schedule(); |
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} |
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/* reset not completed */ |
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return false; |
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} |
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int init_cc_regs(struct cc_drvdata *drvdata) |
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{ |
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unsigned int val; |
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struct device *dev = drvdata_to_dev(drvdata); |
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/* Unmask all AXI interrupt sources AXI_CFG1 register */ |
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/* AXI interrupt config are obsoleted startign at cc7x3 */ |
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if (drvdata->hw_rev <= CC_HW_REV_712) { |
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val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); |
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cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); |
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dev_dbg(dev, "AXIM_CFG=0x%08X\n", |
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cc_ioread(drvdata, CC_REG(AXIM_CFG))); |
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} |
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/* Clear all pending interrupts */ |
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val = cc_ioread(drvdata, CC_REG(HOST_IRR)); |
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dev_dbg(dev, "IRR=0x%08X\n", val); |
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cc_iowrite(drvdata, CC_REG(HOST_ICR), val); |
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/* Unmask relevant interrupt cause */ |
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val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK; |
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if (drvdata->hw_rev >= CC_HW_REV_712) |
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val |= CC_GPR0_IRQ_MASK; |
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cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val); |
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cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params); |
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if (drvdata->hw_rev >= CC_HW_REV_712) |
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cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const); |
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return 0; |
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} |
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static int init_cc_resources(struct platform_device *plat_dev) |
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{ |
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struct resource *req_mem_cc_regs = NULL; |
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struct cc_drvdata *new_drvdata; |
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struct device *dev = &plat_dev->dev; |
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struct device_node *np = dev->of_node; |
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u32 val, hw_rev_pidr, sig_cidr; |
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u64 dma_mask; |
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const struct cc_hw_data *hw_rev; |
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struct clk *clk; |
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int irq; |
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int rc = 0; |
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new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL); |
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if (!new_drvdata) |
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return -ENOMEM; |
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hw_rev = of_device_get_match_data(dev); |
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new_drvdata->hw_rev_name = hw_rev->name; |
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new_drvdata->hw_rev = hw_rev->rev; |
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new_drvdata->std_bodies = hw_rev->std_bodies; |
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if (hw_rev->rev >= CC_HW_REV_712) { |
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new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); |
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new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); |
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new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); |
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} else { |
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new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); |
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new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); |
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new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); |
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} |
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new_drvdata->comp_mask = CC_COMP_IRQ_MASK; |
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platform_set_drvdata(plat_dev, new_drvdata); |
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new_drvdata->plat_dev = plat_dev; |
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clk = devm_clk_get_optional(dev, NULL); |
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if (IS_ERR(clk)) |
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return dev_err_probe(dev, PTR_ERR(clk), "Error getting clock\n"); |
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new_drvdata->clk = clk; |
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new_drvdata->coherent = of_dma_is_coherent(np); |
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/* Get device resources */ |
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/* First CC registers space */ |
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req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); |
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/* Map registers space */ |
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new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs); |
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if (IS_ERR(new_drvdata->cc_base)) { |
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dev_err(dev, "Failed to ioremap registers"); |
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return PTR_ERR(new_drvdata->cc_base); |
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} |
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dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name, |
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req_mem_cc_regs); |
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dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n", |
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&req_mem_cc_regs->start, new_drvdata->cc_base); |
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/* Then IRQ */ |
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irq = platform_get_irq(plat_dev, 0); |
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if (irq < 0) |
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return irq; |
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init_completion(&new_drvdata->hw_queue_avail); |
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if (!dev->dma_mask) |
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dev->dma_mask = &dev->coherent_dma_mask; |
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dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN); |
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while (dma_mask > 0x7fffffffUL) { |
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if (dma_supported(dev, dma_mask)) { |
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rc = dma_set_coherent_mask(dev, dma_mask); |
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if (!rc) |
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break; |
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} |
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dma_mask >>= 1; |
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} |
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if (rc) { |
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dev_err(dev, "Failed in dma_set_mask, mask=%llx\n", dma_mask); |
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return rc; |
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} |
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rc = clk_prepare_enable(new_drvdata->clk); |
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if (rc) { |
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dev_err(dev, "Failed to enable clock"); |
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return rc; |
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} |
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new_drvdata->sec_disabled = cc_sec_disable; |
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pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT); |
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pm_runtime_use_autosuspend(dev); |
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pm_runtime_set_active(dev); |
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pm_runtime_enable(dev); |
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rc = pm_runtime_get_sync(dev); |
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if (rc < 0) { |
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dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc); |
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goto post_pm_err; |
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} |
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/* Wait for Cryptocell reset completion */ |
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if (!cc_wait_for_reset_completion(new_drvdata)) { |
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dev_err(dev, "Cryptocell reset not completed"); |
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} |
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if (hw_rev->rev <= CC_HW_REV_712) { |
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/* Verify correct mapping */ |
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val = cc_ioread(new_drvdata, new_drvdata->sig_offset); |
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if (val != hw_rev->sig) { |
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dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", |
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val, hw_rev->sig); |
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rc = -EINVAL; |
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goto post_pm_err; |
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} |
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sig_cidr = val; |
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hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset); |
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} else { |
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/* Verify correct mapping */ |
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val = cc_read_idr(new_drvdata, pidr_0124_offsets); |
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if (val != hw_rev->pidr_0124) { |
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dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n", |
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val, hw_rev->pidr_0124); |
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rc = -EINVAL; |
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goto post_pm_err; |
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} |
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hw_rev_pidr = val; |
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val = cc_read_idr(new_drvdata, cidr_0123_offsets); |
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if (val != hw_rev->cidr_0123) { |
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dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n", |
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val, hw_rev->cidr_0123); |
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rc = -EINVAL; |
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goto post_pm_err; |
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} |
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sig_cidr = val; |
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/* Check HW engine configuration */ |
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val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS)); |
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switch (val) { |
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case CC_PINS_FULL: |
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/* This is fine */ |
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break; |
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case CC_PINS_SLIM: |
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if (new_drvdata->std_bodies & CC_STD_NIST) { |
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dev_warn(dev, "703 mode forced due to HW configuration.\n"); |
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new_drvdata->std_bodies = CC_STD_OSCCA; |
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} |
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break; |
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default: |
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dev_err(dev, "Unsupported engines configuration.\n"); |
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rc = -EINVAL; |
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goto post_pm_err; |
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} |
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/* Check security disable state */ |
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val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED)); |
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val &= CC_SECURITY_DISABLED_MASK; |
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new_drvdata->sec_disabled |= !!val; |
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if (!new_drvdata->sec_disabled) { |
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new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK; |
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if (new_drvdata->std_bodies & CC_STD_NIST) |
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new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK; |
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} |
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} |
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if (new_drvdata->sec_disabled) |
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dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n"); |
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/* Display HW versions */ |
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dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n", |
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hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION); |
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/* register the driver isr function */ |
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rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree", |
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new_drvdata); |
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if (rc) { |
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dev_err(dev, "Could not register to interrupt %d\n", irq); |
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goto post_pm_err; |
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} |
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dev_dbg(dev, "Registered to IRQ: %d\n", irq); |
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init_cc_cache_params(new_drvdata); |
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rc = init_cc_regs(new_drvdata); |
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if (rc) { |
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dev_err(dev, "init_cc_regs failed\n"); |
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goto post_pm_err; |
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} |
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rc = cc_debugfs_init(new_drvdata); |
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if (rc) { |
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dev_err(dev, "Failed registering debugfs interface\n"); |
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goto post_regs_err; |
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} |
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rc = cc_fips_init(new_drvdata); |
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if (rc) { |
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dev_err(dev, "cc_fips_init failed 0x%x\n", rc); |
|
goto post_debugfs_err; |
|
} |
|
rc = cc_sram_mgr_init(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_sram_mgr_init failed\n"); |
|
goto post_fips_init_err; |
|
} |
|
|
|
new_drvdata->mlli_sram_addr = |
|
cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE); |
|
if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) { |
|
rc = -ENOMEM; |
|
goto post_fips_init_err; |
|
} |
|
|
|
rc = cc_req_mgr_init(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_req_mgr_init failed\n"); |
|
goto post_fips_init_err; |
|
} |
|
|
|
rc = cc_buffer_mgr_init(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_buffer_mgr_init failed\n"); |
|
goto post_req_mgr_err; |
|
} |
|
|
|
/* Allocate crypto algs */ |
|
rc = cc_cipher_alloc(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_cipher_alloc failed\n"); |
|
goto post_buf_mgr_err; |
|
} |
|
|
|
/* hash must be allocated before aead since hash exports APIs */ |
|
rc = cc_hash_alloc(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_hash_alloc failed\n"); |
|
goto post_cipher_err; |
|
} |
|
|
|
rc = cc_aead_alloc(new_drvdata); |
|
if (rc) { |
|
dev_err(dev, "cc_aead_alloc failed\n"); |
|
goto post_hash_err; |
|
} |
|
|
|
/* If we got here and FIPS mode is enabled |
|
* it means all FIPS test passed, so let TEE |
|
* know we're good. |
|
*/ |
|
cc_set_ree_fips_status(new_drvdata, true); |
|
|
|
pm_runtime_put(dev); |
|
return 0; |
|
|
|
post_hash_err: |
|
cc_hash_free(new_drvdata); |
|
post_cipher_err: |
|
cc_cipher_free(new_drvdata); |
|
post_buf_mgr_err: |
|
cc_buffer_mgr_fini(new_drvdata); |
|
post_req_mgr_err: |
|
cc_req_mgr_fini(new_drvdata); |
|
post_fips_init_err: |
|
cc_fips_fini(new_drvdata); |
|
post_debugfs_err: |
|
cc_debugfs_fini(new_drvdata); |
|
post_regs_err: |
|
fini_cc_regs(new_drvdata); |
|
post_pm_err: |
|
pm_runtime_put_noidle(dev); |
|
pm_runtime_disable(dev); |
|
pm_runtime_set_suspended(dev); |
|
clk_disable_unprepare(new_drvdata->clk); |
|
return rc; |
|
} |
|
|
|
void fini_cc_regs(struct cc_drvdata *drvdata) |
|
{ |
|
/* Mask all interrupts */ |
|
cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); |
|
} |
|
|
|
static void cleanup_cc_resources(struct platform_device *plat_dev) |
|
{ |
|
struct device *dev = &plat_dev->dev; |
|
struct cc_drvdata *drvdata = |
|
(struct cc_drvdata *)platform_get_drvdata(plat_dev); |
|
|
|
cc_aead_free(drvdata); |
|
cc_hash_free(drvdata); |
|
cc_cipher_free(drvdata); |
|
cc_buffer_mgr_fini(drvdata); |
|
cc_req_mgr_fini(drvdata); |
|
cc_fips_fini(drvdata); |
|
cc_debugfs_fini(drvdata); |
|
fini_cc_regs(drvdata); |
|
pm_runtime_put_noidle(dev); |
|
pm_runtime_disable(dev); |
|
pm_runtime_set_suspended(dev); |
|
clk_disable_unprepare(drvdata->clk); |
|
} |
|
|
|
unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata) |
|
{ |
|
if (drvdata->hw_rev >= CC_HW_REV_712) |
|
return HASH_LEN_SIZE_712; |
|
else |
|
return HASH_LEN_SIZE_630; |
|
} |
|
|
|
static int ccree_probe(struct platform_device *plat_dev) |
|
{ |
|
int rc; |
|
struct device *dev = &plat_dev->dev; |
|
|
|
/* Map registers space */ |
|
rc = init_cc_resources(plat_dev); |
|
if (rc) |
|
return rc; |
|
|
|
dev_info(dev, "ARM ccree device initialized\n"); |
|
|
|
return 0; |
|
} |
|
|
|
static int ccree_remove(struct platform_device *plat_dev) |
|
{ |
|
struct device *dev = &plat_dev->dev; |
|
|
|
dev_dbg(dev, "Releasing ccree resources...\n"); |
|
|
|
cleanup_cc_resources(plat_dev); |
|
|
|
dev_info(dev, "ARM ccree device terminated\n"); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver ccree_driver = { |
|
.driver = { |
|
.name = "ccree", |
|
.of_match_table = arm_ccree_dev_of_match, |
|
#ifdef CONFIG_PM |
|
.pm = &ccree_pm, |
|
#endif |
|
}, |
|
.probe = ccree_probe, |
|
.remove = ccree_remove, |
|
}; |
|
|
|
static int __init ccree_init(void) |
|
{ |
|
cc_debugfs_global_init(); |
|
|
|
return platform_driver_register(&ccree_driver); |
|
} |
|
module_init(ccree_init); |
|
|
|
static void __exit ccree_exit(void) |
|
{ |
|
platform_driver_unregister(&ccree_driver); |
|
cc_debugfs_global_fini(); |
|
} |
|
module_exit(ccree_exit); |
|
|
|
/* Module description */ |
|
MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver"); |
|
MODULE_VERSION(DRV_MODULE_VERSION); |
|
MODULE_AUTHOR("ARM"); |
|
MODULE_LICENSE("GPL v2");
|
|
|