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598 lines
15 KiB
598 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* AMD Cryptographic Coprocessor (CCP) driver |
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* |
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* Copyright (C) 2013,2017 Advanced Micro Devices, Inc. |
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* |
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* Author: Tom Lendacky <[email protected]> |
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* Author: Gary R Hook <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/kthread.h> |
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#include <linux/interrupt.h> |
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#include <linux/ccp.h> |
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#include "ccp-dev.h" |
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static u32 ccp_alloc_ksb(struct ccp_cmd_queue *cmd_q, unsigned int count) |
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{ |
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int start; |
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struct ccp_device *ccp = cmd_q->ccp; |
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for (;;) { |
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mutex_lock(&ccp->sb_mutex); |
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start = (u32)bitmap_find_next_zero_area(ccp->sb, |
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ccp->sb_count, |
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ccp->sb_start, |
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count, 0); |
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if (start <= ccp->sb_count) { |
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bitmap_set(ccp->sb, start, count); |
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mutex_unlock(&ccp->sb_mutex); |
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break; |
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} |
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ccp->sb_avail = 0; |
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mutex_unlock(&ccp->sb_mutex); |
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/* Wait for KSB entries to become available */ |
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if (wait_event_interruptible(ccp->sb_queue, ccp->sb_avail)) |
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return 0; |
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} |
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return KSB_START + start; |
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} |
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static void ccp_free_ksb(struct ccp_cmd_queue *cmd_q, unsigned int start, |
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unsigned int count) |
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{ |
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struct ccp_device *ccp = cmd_q->ccp; |
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if (!start) |
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return; |
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mutex_lock(&ccp->sb_mutex); |
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bitmap_clear(ccp->sb, start - KSB_START, count); |
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ccp->sb_avail = 1; |
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mutex_unlock(&ccp->sb_mutex); |
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wake_up_interruptible_all(&ccp->sb_queue); |
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} |
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static unsigned int ccp_get_free_slots(struct ccp_cmd_queue *cmd_q) |
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{ |
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return CMD_Q_DEPTH(ioread32(cmd_q->reg_status)); |
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} |
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static int ccp_do_cmd(struct ccp_op *op, u32 *cr, unsigned int cr_count) |
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{ |
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struct ccp_cmd_queue *cmd_q = op->cmd_q; |
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struct ccp_device *ccp = cmd_q->ccp; |
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void __iomem *cr_addr; |
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u32 cr0, cmd; |
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unsigned int i; |
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int ret = 0; |
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/* We could read a status register to see how many free slots |
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* are actually available, but reading that register resets it |
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* and you could lose some error information. |
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*/ |
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cmd_q->free_slots--; |
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cr0 = (cmd_q->id << REQ0_CMD_Q_SHIFT) |
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| (op->jobid << REQ0_JOBID_SHIFT) |
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| REQ0_WAIT_FOR_WRITE; |
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if (op->soc) |
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cr0 |= REQ0_STOP_ON_COMPLETE |
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| REQ0_INT_ON_COMPLETE; |
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if (op->ioc || !cmd_q->free_slots) |
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cr0 |= REQ0_INT_ON_COMPLETE; |
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/* Start at CMD_REQ1 */ |
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cr_addr = ccp->io_regs + CMD_REQ0 + CMD_REQ_INCR; |
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mutex_lock(&ccp->req_mutex); |
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/* Write CMD_REQ1 through CMD_REQx first */ |
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for (i = 0; i < cr_count; i++, cr_addr += CMD_REQ_INCR) |
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iowrite32(*(cr + i), cr_addr); |
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/* Tell the CCP to start */ |
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wmb(); |
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iowrite32(cr0, ccp->io_regs + CMD_REQ0); |
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mutex_unlock(&ccp->req_mutex); |
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if (cr0 & REQ0_INT_ON_COMPLETE) { |
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/* Wait for the job to complete */ |
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ret = wait_event_interruptible(cmd_q->int_queue, |
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cmd_q->int_rcvd); |
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if (ret || cmd_q->cmd_error) { |
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/* On error delete all related jobs from the queue */ |
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cmd = (cmd_q->id << DEL_Q_ID_SHIFT) |
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| op->jobid; |
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if (cmd_q->cmd_error) |
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ccp_log_error(cmd_q->ccp, |
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cmd_q->cmd_error); |
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iowrite32(cmd, ccp->io_regs + DEL_CMD_Q_JOB); |
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if (!ret) |
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ret = -EIO; |
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} else if (op->soc) { |
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/* Delete just head job from the queue on SoC */ |
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cmd = DEL_Q_ACTIVE |
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| (cmd_q->id << DEL_Q_ID_SHIFT) |
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| op->jobid; |
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iowrite32(cmd, ccp->io_regs + DEL_CMD_Q_JOB); |
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} |
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cmd_q->free_slots = CMD_Q_DEPTH(cmd_q->q_status); |
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cmd_q->int_rcvd = 0; |
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} |
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return ret; |
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} |
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static int ccp_perform_aes(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = (CCP_ENGINE_AES << REQ1_ENGINE_SHIFT) |
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| (op->u.aes.type << REQ1_AES_TYPE_SHIFT) |
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| (op->u.aes.mode << REQ1_AES_MODE_SHIFT) |
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| (op->u.aes.action << REQ1_AES_ACTION_SHIFT) |
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| (op->sb_key << REQ1_KEY_KSB_SHIFT); |
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cr[1] = op->src.u.dma.length - 1; |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) |
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| (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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cr[4] = ccp_addr_lo(&op->dst.u.dma); |
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cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->dst.u.dma); |
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if (op->u.aes.mode == CCP_AES_MODE_CFB) |
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cr[0] |= ((0x7f) << REQ1_AES_CFB_SIZE_SHIFT); |
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if (op->eom) |
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cr[0] |= REQ1_EOM; |
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if (op->init) |
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cr[0] |= REQ1_INIT; |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static int ccp_perform_xts_aes(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = (CCP_ENGINE_XTS_AES_128 << REQ1_ENGINE_SHIFT) |
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| (op->u.xts.action << REQ1_AES_ACTION_SHIFT) |
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| (op->u.xts.unit_size << REQ1_XTS_AES_SIZE_SHIFT) |
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| (op->sb_key << REQ1_KEY_KSB_SHIFT); |
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cr[1] = op->src.u.dma.length - 1; |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) |
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| (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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cr[4] = ccp_addr_lo(&op->dst.u.dma); |
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cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->dst.u.dma); |
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if (op->eom) |
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cr[0] |= REQ1_EOM; |
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if (op->init) |
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cr[0] |= REQ1_INIT; |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static int ccp_perform_sha(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = (CCP_ENGINE_SHA << REQ1_ENGINE_SHIFT) |
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| (op->u.sha.type << REQ1_SHA_TYPE_SHIFT) |
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| REQ1_INIT; |
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cr[1] = op->src.u.dma.length - 1; |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) |
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| (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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if (op->eom) { |
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cr[0] |= REQ1_EOM; |
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cr[4] = lower_32_bits(op->u.sha.msg_bits); |
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cr[5] = upper_32_bits(op->u.sha.msg_bits); |
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} else { |
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cr[4] = 0; |
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cr[5] = 0; |
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} |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static int ccp_perform_rsa(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = (CCP_ENGINE_RSA << REQ1_ENGINE_SHIFT) |
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| (op->u.rsa.mod_size << REQ1_RSA_MOD_SIZE_SHIFT) |
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| (op->sb_key << REQ1_KEY_KSB_SHIFT) |
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| REQ1_EOM; |
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cr[1] = op->u.rsa.input_len - 1; |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) |
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| (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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cr[4] = ccp_addr_lo(&op->dst.u.dma); |
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cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->dst.u.dma); |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static int ccp_perform_passthru(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = (CCP_ENGINE_PASSTHRU << REQ1_ENGINE_SHIFT) |
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| (op->u.passthru.bit_mod << REQ1_PT_BW_SHIFT) |
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| (op->u.passthru.byte_swap << REQ1_PT_BS_SHIFT); |
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if (op->src.type == CCP_MEMTYPE_SYSTEM) |
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cr[1] = op->src.u.dma.length - 1; |
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else |
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cr[1] = op->dst.u.dma.length - 1; |
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if (op->src.type == CCP_MEMTYPE_SYSTEM) { |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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if (op->u.passthru.bit_mod != CCP_PASSTHRU_BITWISE_NOOP) |
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cr[3] |= (op->sb_key << REQ4_KSB_SHIFT); |
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} else { |
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cr[2] = op->src.u.sb * CCP_SB_BYTES; |
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cr[3] = (CCP_MEMTYPE_SB << REQ4_MEMTYPE_SHIFT); |
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} |
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if (op->dst.type == CCP_MEMTYPE_SYSTEM) { |
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cr[4] = ccp_addr_lo(&op->dst.u.dma); |
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cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->dst.u.dma); |
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} else { |
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cr[4] = op->dst.u.sb * CCP_SB_BYTES; |
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cr[5] = (CCP_MEMTYPE_SB << REQ6_MEMTYPE_SHIFT); |
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} |
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if (op->eom) |
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cr[0] |= REQ1_EOM; |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static int ccp_perform_ecc(struct ccp_op *op) |
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{ |
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u32 cr[6]; |
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/* Fill out the register contents for REQ1 through REQ6 */ |
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cr[0] = REQ1_ECC_AFFINE_CONVERT |
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| (CCP_ENGINE_ECC << REQ1_ENGINE_SHIFT) |
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| (op->u.ecc.function << REQ1_ECC_FUNCTION_SHIFT) |
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| REQ1_EOM; |
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cr[1] = op->src.u.dma.length - 1; |
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cr[2] = ccp_addr_lo(&op->src.u.dma); |
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cr[3] = (CCP_MEMTYPE_SYSTEM << REQ4_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->src.u.dma); |
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cr[4] = ccp_addr_lo(&op->dst.u.dma); |
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cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) |
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| ccp_addr_hi(&op->dst.u.dma); |
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return ccp_do_cmd(op, cr, ARRAY_SIZE(cr)); |
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} |
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static void ccp_disable_queue_interrupts(struct ccp_device *ccp) |
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{ |
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iowrite32(0x00, ccp->io_regs + IRQ_MASK_REG); |
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} |
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static void ccp_enable_queue_interrupts(struct ccp_device *ccp) |
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{ |
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iowrite32(ccp->qim, ccp->io_regs + IRQ_MASK_REG); |
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} |
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static void ccp_irq_bh(unsigned long data) |
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{ |
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struct ccp_device *ccp = (struct ccp_device *)data; |
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struct ccp_cmd_queue *cmd_q; |
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u32 q_int, status; |
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unsigned int i; |
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status = ioread32(ccp->io_regs + IRQ_STATUS_REG); |
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for (i = 0; i < ccp->cmd_q_count; i++) { |
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cmd_q = &ccp->cmd_q[i]; |
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q_int = status & (cmd_q->int_ok | cmd_q->int_err); |
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if (q_int) { |
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cmd_q->int_status = status; |
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cmd_q->q_status = ioread32(cmd_q->reg_status); |
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cmd_q->q_int_status = ioread32(cmd_q->reg_int_status); |
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/* On error, only save the first error value */ |
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if ((q_int & cmd_q->int_err) && !cmd_q->cmd_error) |
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cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status); |
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cmd_q->int_rcvd = 1; |
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|
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/* Acknowledge the interrupt and wake the kthread */ |
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iowrite32(q_int, ccp->io_regs + IRQ_STATUS_REG); |
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wake_up_interruptible(&cmd_q->int_queue); |
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} |
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} |
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ccp_enable_queue_interrupts(ccp); |
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} |
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static irqreturn_t ccp_irq_handler(int irq, void *data) |
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{ |
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struct ccp_device *ccp = (struct ccp_device *)data; |
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ccp_disable_queue_interrupts(ccp); |
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if (ccp->use_tasklet) |
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tasklet_schedule(&ccp->irq_tasklet); |
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else |
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ccp_irq_bh((unsigned long)ccp); |
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return IRQ_HANDLED; |
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} |
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static int ccp_init(struct ccp_device *ccp) |
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{ |
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struct device *dev = ccp->dev; |
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struct ccp_cmd_queue *cmd_q; |
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struct dma_pool *dma_pool; |
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char dma_pool_name[MAX_DMAPOOL_NAME_LEN]; |
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unsigned int qmr, i; |
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int ret; |
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/* Find available queues */ |
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ccp->qim = 0; |
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qmr = ioread32(ccp->io_regs + Q_MASK_REG); |
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for (i = 0; (i < MAX_HW_QUEUES) && (ccp->cmd_q_count < ccp->max_q_count); i++) { |
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if (!(qmr & (1 << i))) |
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continue; |
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/* Allocate a dma pool for this queue */ |
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snprintf(dma_pool_name, sizeof(dma_pool_name), "%s_q%d", |
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ccp->name, i); |
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dma_pool = dma_pool_create(dma_pool_name, dev, |
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CCP_DMAPOOL_MAX_SIZE, |
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CCP_DMAPOOL_ALIGN, 0); |
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if (!dma_pool) { |
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dev_err(dev, "unable to allocate dma pool\n"); |
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ret = -ENOMEM; |
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goto e_pool; |
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} |
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cmd_q = &ccp->cmd_q[ccp->cmd_q_count]; |
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ccp->cmd_q_count++; |
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|
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cmd_q->ccp = ccp; |
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cmd_q->id = i; |
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cmd_q->dma_pool = dma_pool; |
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|
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/* Reserve 2 KSB regions for the queue */ |
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cmd_q->sb_key = KSB_START + ccp->sb_start++; |
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cmd_q->sb_ctx = KSB_START + ccp->sb_start++; |
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ccp->sb_count -= 2; |
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|
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/* Preset some register values and masks that are queue |
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* number dependent |
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*/ |
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cmd_q->reg_status = ccp->io_regs + CMD_Q_STATUS_BASE + |
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(CMD_Q_STATUS_INCR * i); |
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cmd_q->reg_int_status = ccp->io_regs + CMD_Q_INT_STATUS_BASE + |
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(CMD_Q_STATUS_INCR * i); |
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cmd_q->int_ok = 1 << (i * 2); |
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cmd_q->int_err = 1 << ((i * 2) + 1); |
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|
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cmd_q->free_slots = ccp_get_free_slots(cmd_q); |
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|
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init_waitqueue_head(&cmd_q->int_queue); |
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|
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/* Build queue interrupt mask (two interrupts per queue) */ |
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ccp->qim |= cmd_q->int_ok | cmd_q->int_err; |
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|
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#ifdef CONFIG_ARM64 |
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/* For arm64 set the recommended queue cache settings */ |
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iowrite32(ccp->axcache, ccp->io_regs + CMD_Q_CACHE_BASE + |
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(CMD_Q_CACHE_INC * i)); |
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#endif |
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|
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dev_dbg(dev, "queue #%u available\n", i); |
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} |
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if (ccp->cmd_q_count == 0) { |
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dev_notice(dev, "no command queues available\n"); |
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ret = -EIO; |
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goto e_pool; |
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} |
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dev_notice(dev, "%u command queues available\n", ccp->cmd_q_count); |
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|
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/* Disable and clear interrupts until ready */ |
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ccp_disable_queue_interrupts(ccp); |
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for (i = 0; i < ccp->cmd_q_count; i++) { |
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cmd_q = &ccp->cmd_q[i]; |
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|
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ioread32(cmd_q->reg_int_status); |
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ioread32(cmd_q->reg_status); |
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} |
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iowrite32(ccp->qim, ccp->io_regs + IRQ_STATUS_REG); |
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|
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/* Request an irq */ |
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ret = sp_request_ccp_irq(ccp->sp, ccp_irq_handler, ccp->name, ccp); |
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if (ret) { |
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dev_err(dev, "unable to allocate an IRQ\n"); |
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goto e_pool; |
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} |
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|
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/* Initialize the ISR tasklet? */ |
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if (ccp->use_tasklet) |
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tasklet_init(&ccp->irq_tasklet, ccp_irq_bh, |
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(unsigned long)ccp); |
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|
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dev_dbg(dev, "Starting threads...\n"); |
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/* Create a kthread for each queue */ |
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for (i = 0; i < ccp->cmd_q_count; i++) { |
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struct task_struct *kthread; |
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|
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cmd_q = &ccp->cmd_q[i]; |
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|
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kthread = kthread_create(ccp_cmd_queue_thread, cmd_q, |
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"%s-q%u", ccp->name, cmd_q->id); |
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if (IS_ERR(kthread)) { |
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dev_err(dev, "error creating queue thread (%ld)\n", |
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PTR_ERR(kthread)); |
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ret = PTR_ERR(kthread); |
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goto e_kthread; |
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} |
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|
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cmd_q->kthread = kthread; |
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wake_up_process(kthread); |
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} |
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|
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dev_dbg(dev, "Enabling interrupts...\n"); |
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/* Enable interrupts */ |
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ccp_enable_queue_interrupts(ccp); |
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|
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dev_dbg(dev, "Registering device...\n"); |
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ccp_add_device(ccp); |
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|
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ret = ccp_register_rng(ccp); |
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if (ret) |
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goto e_kthread; |
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|
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/* Register the DMA engine support */ |
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ret = ccp_dmaengine_register(ccp); |
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if (ret) |
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goto e_hwrng; |
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|
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return 0; |
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|
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e_hwrng: |
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ccp_unregister_rng(ccp); |
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|
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e_kthread: |
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for (i = 0; i < ccp->cmd_q_count; i++) |
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if (ccp->cmd_q[i].kthread) |
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kthread_stop(ccp->cmd_q[i].kthread); |
|
|
|
sp_free_ccp_irq(ccp->sp, ccp); |
|
|
|
e_pool: |
|
for (i = 0; i < ccp->cmd_q_count; i++) |
|
dma_pool_destroy(ccp->cmd_q[i].dma_pool); |
|
|
|
return ret; |
|
} |
|
|
|
static void ccp_destroy(struct ccp_device *ccp) |
|
{ |
|
struct ccp_cmd_queue *cmd_q; |
|
struct ccp_cmd *cmd; |
|
unsigned int i; |
|
|
|
/* Unregister the DMA engine */ |
|
ccp_dmaengine_unregister(ccp); |
|
|
|
/* Unregister the RNG */ |
|
ccp_unregister_rng(ccp); |
|
|
|
/* Remove this device from the list of available units */ |
|
ccp_del_device(ccp); |
|
|
|
/* Disable and clear interrupts */ |
|
ccp_disable_queue_interrupts(ccp); |
|
for (i = 0; i < ccp->cmd_q_count; i++) { |
|
cmd_q = &ccp->cmd_q[i]; |
|
|
|
ioread32(cmd_q->reg_int_status); |
|
ioread32(cmd_q->reg_status); |
|
} |
|
iowrite32(ccp->qim, ccp->io_regs + IRQ_STATUS_REG); |
|
|
|
/* Stop the queue kthreads */ |
|
for (i = 0; i < ccp->cmd_q_count; i++) |
|
if (ccp->cmd_q[i].kthread) |
|
kthread_stop(ccp->cmd_q[i].kthread); |
|
|
|
sp_free_ccp_irq(ccp->sp, ccp); |
|
|
|
for (i = 0; i < ccp->cmd_q_count; i++) |
|
dma_pool_destroy(ccp->cmd_q[i].dma_pool); |
|
|
|
/* Flush the cmd and backlog queue */ |
|
while (!list_empty(&ccp->cmd)) { |
|
/* Invoke the callback directly with an error code */ |
|
cmd = list_first_entry(&ccp->cmd, struct ccp_cmd, entry); |
|
list_del(&cmd->entry); |
|
cmd->callback(cmd->data, -ENODEV); |
|
} |
|
while (!list_empty(&ccp->backlog)) { |
|
/* Invoke the callback directly with an error code */ |
|
cmd = list_first_entry(&ccp->backlog, struct ccp_cmd, entry); |
|
list_del(&cmd->entry); |
|
cmd->callback(cmd->data, -ENODEV); |
|
} |
|
} |
|
|
|
static const struct ccp_actions ccp3_actions = { |
|
.aes = ccp_perform_aes, |
|
.xts_aes = ccp_perform_xts_aes, |
|
.des3 = NULL, |
|
.sha = ccp_perform_sha, |
|
.rsa = ccp_perform_rsa, |
|
.passthru = ccp_perform_passthru, |
|
.ecc = ccp_perform_ecc, |
|
.sballoc = ccp_alloc_ksb, |
|
.sbfree = ccp_free_ksb, |
|
.init = ccp_init, |
|
.destroy = ccp_destroy, |
|
.get_free_slots = ccp_get_free_slots, |
|
.irqhandler = ccp_irq_handler, |
|
}; |
|
|
|
const struct ccp_vdata ccpv3_platform = { |
|
.version = CCP_VERSION(3, 0), |
|
.setup = NULL, |
|
.perform = &ccp3_actions, |
|
.offset = 0, |
|
.rsamax = CCP_RSA_MAX_WIDTH, |
|
}; |
|
|
|
const struct ccp_vdata ccpv3 = { |
|
.version = CCP_VERSION(3, 0), |
|
.setup = NULL, |
|
.perform = &ccp3_actions, |
|
.offset = 0x20000, |
|
.rsamax = CCP_RSA_MAX_WIDTH, |
|
};
|
|
|