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579 lines
15 KiB
579 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
|
/* |
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* sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC |
|
* |
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* Copyright (C) 2013-2015 Corentin LABBE <[email protected]> |
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* |
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* Core file which registers crypto algorithms supported by the SS. |
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* |
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* You could find a link for the datasheet in Documentation/arm/sunxi.rst |
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*/ |
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#include <linux/clk.h> |
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#include <linux/crypto.h> |
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#include <linux/debugfs.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <crypto/scatterwalk.h> |
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#include <linux/scatterlist.h> |
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/reset.h> |
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|
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#include "sun4i-ss.h" |
|
|
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static const struct ss_variant ss_a10_variant = { |
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.sha1_in_be = false, |
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}; |
|
|
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static const struct ss_variant ss_a33_variant = { |
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.sha1_in_be = true, |
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}; |
|
|
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static struct sun4i_ss_alg_template ss_algs[] = { |
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{ .type = CRYPTO_ALG_TYPE_AHASH, |
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.mode = SS_OP_MD5, |
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.alg.hash = { |
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.init = sun4i_hash_init, |
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.update = sun4i_hash_update, |
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.final = sun4i_hash_final, |
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.finup = sun4i_hash_finup, |
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.digest = sun4i_hash_digest, |
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.export = sun4i_hash_export_md5, |
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.import = sun4i_hash_import_md5, |
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.halg = { |
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.digestsize = MD5_DIGEST_SIZE, |
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.statesize = sizeof(struct md5_state), |
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.base = { |
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.cra_name = "md5", |
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.cra_driver_name = "md5-sun4i-ss", |
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.cra_priority = 300, |
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.cra_alignmask = 3, |
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.cra_blocksize = MD5_HMAC_BLOCK_SIZE, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_init = sun4i_hash_crainit, |
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.cra_exit = sun4i_hash_craexit, |
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} |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_AHASH, |
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.mode = SS_OP_SHA1, |
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.alg.hash = { |
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.init = sun4i_hash_init, |
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.update = sun4i_hash_update, |
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.final = sun4i_hash_final, |
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.finup = sun4i_hash_finup, |
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.digest = sun4i_hash_digest, |
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.export = sun4i_hash_export_sha1, |
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.import = sun4i_hash_import_sha1, |
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.halg = { |
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.digestsize = SHA1_DIGEST_SIZE, |
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.statesize = sizeof(struct sha1_state), |
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.base = { |
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.cra_name = "sha1", |
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.cra_driver_name = "sha1-sun4i-ss", |
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.cra_priority = 300, |
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.cra_alignmask = 3, |
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.cra_blocksize = SHA1_BLOCK_SIZE, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_init = sun4i_hash_crainit, |
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.cra_exit = sun4i_hash_craexit, |
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} |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_aes_setkey, |
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.encrypt = sun4i_ss_cbc_aes_encrypt, |
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.decrypt = sun4i_ss_cbc_aes_decrypt, |
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.min_keysize = AES_MIN_KEY_SIZE, |
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.max_keysize = AES_MAX_KEY_SIZE, |
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.ivsize = AES_BLOCK_SIZE, |
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.base = { |
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.cra_name = "cbc(aes)", |
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.cra_driver_name = "cbc-aes-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = AES_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_tfm_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_aes_setkey, |
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.encrypt = sun4i_ss_ecb_aes_encrypt, |
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.decrypt = sun4i_ss_ecb_aes_decrypt, |
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.min_keysize = AES_MIN_KEY_SIZE, |
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.max_keysize = AES_MAX_KEY_SIZE, |
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.base = { |
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.cra_name = "ecb(aes)", |
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.cra_driver_name = "ecb-aes-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = AES_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_tfm_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_des_setkey, |
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.encrypt = sun4i_ss_cbc_des_encrypt, |
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.decrypt = sun4i_ss_cbc_des_decrypt, |
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.min_keysize = DES_KEY_SIZE, |
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.max_keysize = DES_KEY_SIZE, |
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.ivsize = DES_BLOCK_SIZE, |
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.base = { |
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.cra_name = "cbc(des)", |
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.cra_driver_name = "cbc-des-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = DES_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_des_setkey, |
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.encrypt = sun4i_ss_ecb_des_encrypt, |
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.decrypt = sun4i_ss_ecb_des_decrypt, |
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.min_keysize = DES_KEY_SIZE, |
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.max_keysize = DES_KEY_SIZE, |
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.base = { |
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.cra_name = "ecb(des)", |
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.cra_driver_name = "ecb-des-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = DES_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_des3_setkey, |
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.encrypt = sun4i_ss_cbc_des3_encrypt, |
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.decrypt = sun4i_ss_cbc_des3_decrypt, |
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.min_keysize = DES3_EDE_KEY_SIZE, |
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.max_keysize = DES3_EDE_KEY_SIZE, |
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.ivsize = DES3_EDE_BLOCK_SIZE, |
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.base = { |
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.cra_name = "cbc(des3_ede)", |
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.cra_driver_name = "cbc-des3-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = DES3_EDE_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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{ .type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.alg.crypto = { |
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.setkey = sun4i_ss_des3_setkey, |
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.encrypt = sun4i_ss_ecb_des3_encrypt, |
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.decrypt = sun4i_ss_ecb_des3_decrypt, |
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.min_keysize = DES3_EDE_KEY_SIZE, |
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.max_keysize = DES3_EDE_KEY_SIZE, |
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.base = { |
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.cra_name = "ecb(des3_ede)", |
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.cra_driver_name = "ecb-des3-sun4i-ss", |
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.cra_priority = 300, |
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.cra_blocksize = DES3_EDE_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sun4i_req_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 3, |
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.cra_init = sun4i_ss_cipher_init, |
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.cra_exit = sun4i_ss_cipher_exit, |
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} |
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} |
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}, |
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#ifdef CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG |
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{ |
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.type = CRYPTO_ALG_TYPE_RNG, |
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.alg.rng = { |
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.base = { |
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.cra_name = "stdrng", |
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.cra_driver_name = "sun4i_ss_rng", |
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.cra_priority = 300, |
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.cra_ctxsize = 0, |
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.cra_module = THIS_MODULE, |
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}, |
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.generate = sun4i_ss_prng_generate, |
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.seed = sun4i_ss_prng_seed, |
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.seedsize = SS_SEED_LEN / BITS_PER_BYTE, |
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} |
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}, |
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#endif |
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}; |
|
|
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static int sun4i_ss_dbgfs_read(struct seq_file *seq, void *v) |
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{ |
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unsigned int i; |
|
|
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for (i = 0; i < ARRAY_SIZE(ss_algs); i++) { |
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if (!ss_algs[i].ss) |
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continue; |
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switch (ss_algs[i].type) { |
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case CRYPTO_ALG_TYPE_SKCIPHER: |
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seq_printf(seq, "%s %s reqs=%lu opti=%lu fallback=%lu tsize=%lu\n", |
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ss_algs[i].alg.crypto.base.cra_driver_name, |
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ss_algs[i].alg.crypto.base.cra_name, |
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ss_algs[i].stat_req, ss_algs[i].stat_opti, ss_algs[i].stat_fb, |
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ss_algs[i].stat_bytes); |
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break; |
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case CRYPTO_ALG_TYPE_RNG: |
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seq_printf(seq, "%s %s reqs=%lu tsize=%lu\n", |
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ss_algs[i].alg.rng.base.cra_driver_name, |
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ss_algs[i].alg.rng.base.cra_name, |
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ss_algs[i].stat_req, ss_algs[i].stat_bytes); |
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break; |
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case CRYPTO_ALG_TYPE_AHASH: |
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seq_printf(seq, "%s %s reqs=%lu\n", |
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ss_algs[i].alg.hash.halg.base.cra_driver_name, |
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ss_algs[i].alg.hash.halg.base.cra_name, |
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ss_algs[i].stat_req); |
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break; |
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} |
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} |
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return 0; |
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} |
|
|
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static int sun4i_ss_dbgfs_open(struct inode *inode, struct file *file) |
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{ |
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return single_open(file, sun4i_ss_dbgfs_read, inode->i_private); |
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} |
|
|
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static const struct file_operations sun4i_ss_debugfs_fops = { |
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.owner = THIS_MODULE, |
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.open = sun4i_ss_dbgfs_open, |
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.read = seq_read, |
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.llseek = seq_lseek, |
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.release = single_release, |
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}; |
|
|
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/* |
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* Power management strategy: The device is suspended unless a TFM exists for |
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* one of the algorithms proposed by this driver. |
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*/ |
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static int sun4i_ss_pm_suspend(struct device *dev) |
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{ |
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struct sun4i_ss_ctx *ss = dev_get_drvdata(dev); |
|
|
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if (ss->reset) |
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reset_control_assert(ss->reset); |
|
|
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clk_disable_unprepare(ss->ssclk); |
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clk_disable_unprepare(ss->busclk); |
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return 0; |
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} |
|
|
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static int sun4i_ss_pm_resume(struct device *dev) |
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{ |
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struct sun4i_ss_ctx *ss = dev_get_drvdata(dev); |
|
|
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int err; |
|
|
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err = clk_prepare_enable(ss->busclk); |
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if (err) { |
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dev_err(ss->dev, "Cannot prepare_enable busclk\n"); |
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goto err_enable; |
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} |
|
|
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err = clk_prepare_enable(ss->ssclk); |
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if (err) { |
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dev_err(ss->dev, "Cannot prepare_enable ssclk\n"); |
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goto err_enable; |
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} |
|
|
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if (ss->reset) { |
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err = reset_control_deassert(ss->reset); |
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if (err) { |
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dev_err(ss->dev, "Cannot deassert reset control\n"); |
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goto err_enable; |
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} |
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} |
|
|
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return err; |
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err_enable: |
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sun4i_ss_pm_suspend(dev); |
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return err; |
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} |
|
|
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static const struct dev_pm_ops sun4i_ss_pm_ops = { |
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SET_RUNTIME_PM_OPS(sun4i_ss_pm_suspend, sun4i_ss_pm_resume, NULL) |
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}; |
|
|
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/* |
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* When power management is enabled, this function enables the PM and set the |
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* device as suspended |
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* When power management is disabled, this function just enables the device |
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*/ |
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static int sun4i_ss_pm_init(struct sun4i_ss_ctx *ss) |
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{ |
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int err; |
|
|
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pm_runtime_use_autosuspend(ss->dev); |
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pm_runtime_set_autosuspend_delay(ss->dev, 2000); |
|
|
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err = pm_runtime_set_suspended(ss->dev); |
|
if (err) |
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return err; |
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pm_runtime_enable(ss->dev); |
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return err; |
|
} |
|
|
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static void sun4i_ss_pm_exit(struct sun4i_ss_ctx *ss) |
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{ |
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pm_runtime_disable(ss->dev); |
|
} |
|
|
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static int sun4i_ss_probe(struct platform_device *pdev) |
|
{ |
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u32 v; |
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int err, i; |
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unsigned long cr; |
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const unsigned long cr_ahb = 24 * 1000 * 1000; |
|
const unsigned long cr_mod = 150 * 1000 * 1000; |
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struct sun4i_ss_ctx *ss; |
|
|
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if (!pdev->dev.of_node) |
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return -ENODEV; |
|
|
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ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL); |
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if (!ss) |
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return -ENOMEM; |
|
|
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ss->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(ss->base)) { |
|
dev_err(&pdev->dev, "Cannot request MMIO\n"); |
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return PTR_ERR(ss->base); |
|
} |
|
|
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ss->variant = of_device_get_match_data(&pdev->dev); |
|
if (!ss->variant) { |
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dev_err(&pdev->dev, "Missing Security System variant\n"); |
|
return -EINVAL; |
|
} |
|
|
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ss->ssclk = devm_clk_get(&pdev->dev, "mod"); |
|
if (IS_ERR(ss->ssclk)) { |
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err = PTR_ERR(ss->ssclk); |
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dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err); |
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return err; |
|
} |
|
dev_dbg(&pdev->dev, "clock ss acquired\n"); |
|
|
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ss->busclk = devm_clk_get(&pdev->dev, "ahb"); |
|
if (IS_ERR(ss->busclk)) { |
|
err = PTR_ERR(ss->busclk); |
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dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err); |
|
return err; |
|
} |
|
dev_dbg(&pdev->dev, "clock ahb_ss acquired\n"); |
|
|
|
ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb"); |
|
if (IS_ERR(ss->reset)) { |
|
if (PTR_ERR(ss->reset) == -EPROBE_DEFER) |
|
return PTR_ERR(ss->reset); |
|
dev_info(&pdev->dev, "no reset control found\n"); |
|
ss->reset = NULL; |
|
} |
|
|
|
/* |
|
* Check that clock have the correct rates given in the datasheet |
|
* Try to set the clock to the maximum allowed |
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*/ |
|
err = clk_set_rate(ss->ssclk, cr_mod); |
|
if (err) { |
|
dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n"); |
|
return err; |
|
} |
|
|
|
/* |
|
* The only impact on clocks below requirement are bad performance, |
|
* so do not print "errors" |
|
* warn on Overclocked clocks |
|
*/ |
|
cr = clk_get_rate(ss->busclk); |
|
if (cr >= cr_ahb) |
|
dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n", |
|
cr, cr / 1000000, cr_ahb); |
|
else |
|
dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n", |
|
cr, cr / 1000000, cr_ahb); |
|
|
|
cr = clk_get_rate(ss->ssclk); |
|
if (cr <= cr_mod) |
|
if (cr < cr_mod) |
|
dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n", |
|
cr, cr / 1000000, cr_mod); |
|
else |
|
dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n", |
|
cr, cr / 1000000, cr_mod); |
|
else |
|
dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n", |
|
cr, cr / 1000000, cr_mod); |
|
|
|
ss->dev = &pdev->dev; |
|
platform_set_drvdata(pdev, ss); |
|
|
|
spin_lock_init(&ss->slock); |
|
|
|
err = sun4i_ss_pm_init(ss); |
|
if (err) |
|
return err; |
|
|
|
/* |
|
* Datasheet named it "Die Bonding ID" |
|
* I expect to be a sort of Security System Revision number. |
|
* Since the A80 seems to have an other version of SS |
|
* this info could be useful |
|
*/ |
|
|
|
err = pm_runtime_resume_and_get(ss->dev); |
|
if (err < 0) |
|
goto error_pm; |
|
|
|
writel(SS_ENABLED, ss->base + SS_CTL); |
|
v = readl(ss->base + SS_CTL); |
|
v >>= 16; |
|
v &= 0x07; |
|
dev_info(&pdev->dev, "Die ID %d\n", v); |
|
writel(0, ss->base + SS_CTL); |
|
|
|
pm_runtime_put_sync(ss->dev); |
|
|
|
for (i = 0; i < ARRAY_SIZE(ss_algs); i++) { |
|
ss_algs[i].ss = ss; |
|
switch (ss_algs[i].type) { |
|
case CRYPTO_ALG_TYPE_SKCIPHER: |
|
err = crypto_register_skcipher(&ss_algs[i].alg.crypto); |
|
if (err) { |
|
dev_err(ss->dev, "Fail to register %s\n", |
|
ss_algs[i].alg.crypto.base.cra_name); |
|
goto error_alg; |
|
} |
|
break; |
|
case CRYPTO_ALG_TYPE_AHASH: |
|
err = crypto_register_ahash(&ss_algs[i].alg.hash); |
|
if (err) { |
|
dev_err(ss->dev, "Fail to register %s\n", |
|
ss_algs[i].alg.hash.halg.base.cra_name); |
|
goto error_alg; |
|
} |
|
break; |
|
case CRYPTO_ALG_TYPE_RNG: |
|
err = crypto_register_rng(&ss_algs[i].alg.rng); |
|
if (err) { |
|
dev_err(ss->dev, "Fail to register %s\n", |
|
ss_algs[i].alg.rng.base.cra_name); |
|
} |
|
break; |
|
} |
|
} |
|
|
|
/* Ignore error of debugfs */ |
|
ss->dbgfs_dir = debugfs_create_dir("sun4i-ss", NULL); |
|
ss->dbgfs_stats = debugfs_create_file("stats", 0444, ss->dbgfs_dir, ss, |
|
&sun4i_ss_debugfs_fops); |
|
|
|
return 0; |
|
error_alg: |
|
i--; |
|
for (; i >= 0; i--) { |
|
switch (ss_algs[i].type) { |
|
case CRYPTO_ALG_TYPE_SKCIPHER: |
|
crypto_unregister_skcipher(&ss_algs[i].alg.crypto); |
|
break; |
|
case CRYPTO_ALG_TYPE_AHASH: |
|
crypto_unregister_ahash(&ss_algs[i].alg.hash); |
|
break; |
|
case CRYPTO_ALG_TYPE_RNG: |
|
crypto_unregister_rng(&ss_algs[i].alg.rng); |
|
break; |
|
} |
|
} |
|
error_pm: |
|
sun4i_ss_pm_exit(ss); |
|
return err; |
|
} |
|
|
|
static int sun4i_ss_remove(struct platform_device *pdev) |
|
{ |
|
int i; |
|
struct sun4i_ss_ctx *ss = platform_get_drvdata(pdev); |
|
|
|
for (i = 0; i < ARRAY_SIZE(ss_algs); i++) { |
|
switch (ss_algs[i].type) { |
|
case CRYPTO_ALG_TYPE_SKCIPHER: |
|
crypto_unregister_skcipher(&ss_algs[i].alg.crypto); |
|
break; |
|
case CRYPTO_ALG_TYPE_AHASH: |
|
crypto_unregister_ahash(&ss_algs[i].alg.hash); |
|
break; |
|
case CRYPTO_ALG_TYPE_RNG: |
|
crypto_unregister_rng(&ss_algs[i].alg.rng); |
|
break; |
|
} |
|
} |
|
|
|
sun4i_ss_pm_exit(ss); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id a20ss_crypto_of_match_table[] = { |
|
{ .compatible = "allwinner,sun4i-a10-crypto", |
|
.data = &ss_a10_variant |
|
}, |
|
{ .compatible = "allwinner,sun8i-a33-crypto", |
|
.data = &ss_a33_variant |
|
}, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(of, a20ss_crypto_of_match_table); |
|
|
|
static struct platform_driver sun4i_ss_driver = { |
|
.probe = sun4i_ss_probe, |
|
.remove = sun4i_ss_remove, |
|
.driver = { |
|
.name = "sun4i-ss", |
|
.pm = &sun4i_ss_pm_ops, |
|
.of_match_table = a20ss_crypto_of_match_table, |
|
}, |
|
}; |
|
|
|
module_platform_driver(sun4i_ss_driver); |
|
|
|
MODULE_ALIAS("platform:sun4i-ss"); |
|
MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Corentin LABBE <[email protected]>");
|
|
|