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447 lines
17 KiB
447 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* ahci.h - Common AHCI SATA definitions and declarations |
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* |
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* Maintained by: Tejun Heo <[email protected]> |
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* Please ALWAYS copy [email protected] |
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* on emails. |
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* |
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* Copyright 2004-2005 Red Hat, Inc. |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* AHCI hardware documentation: |
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* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
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* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
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*/ |
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#ifndef _AHCI_H |
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#define _AHCI_H |
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#include <linux/pci.h> |
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#include <linux/clk.h> |
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#include <linux/libata.h> |
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#include <linux/phy/phy.h> |
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#include <linux/regulator/consumer.h> |
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/* Enclosure Management Control */ |
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#define EM_CTRL_MSG_TYPE 0x000f0000 |
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/* Enclosure Management LED Message Type */ |
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#define EM_MSG_LED_HBA_PORT 0x0000000f |
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#define EM_MSG_LED_PMP_SLOT 0x0000ff00 |
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#define EM_MSG_LED_VALUE 0xffff0000 |
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#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000 |
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#define EM_MSG_LED_VALUE_OFF 0xfff80000 |
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#define EM_MSG_LED_VALUE_ON 0x00010000 |
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enum { |
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AHCI_MAX_PORTS = 32, |
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AHCI_MAX_CLKS = 5, |
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AHCI_MAX_SG = 168, /* hardware max is 64K */ |
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AHCI_DMA_BOUNDARY = 0xffffffff, |
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AHCI_MAX_CMDS = 32, |
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AHCI_CMD_SZ = 32, |
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AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
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AHCI_RX_FIS_SZ = 256, |
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AHCI_CMD_TBL_CDB = 0x40, |
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AHCI_CMD_TBL_HDR_SZ = 0x80, |
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AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
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AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
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AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
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AHCI_RX_FIS_SZ, |
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AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + |
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AHCI_CMD_TBL_AR_SZ + |
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(AHCI_RX_FIS_SZ * 16), |
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AHCI_IRQ_ON_SG = (1 << 31), |
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AHCI_CMD_ATAPI = (1 << 5), |
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AHCI_CMD_WRITE = (1 << 6), |
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AHCI_CMD_PREFETCH = (1 << 7), |
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AHCI_CMD_RESET = (1 << 8), |
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AHCI_CMD_CLR_BUSY = (1 << 10), |
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RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ |
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RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
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RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
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RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
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/* global controller registers */ |
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HOST_CAP = 0x00, /* host capabilities */ |
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HOST_CTL = 0x04, /* global host control */ |
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HOST_IRQ_STAT = 0x08, /* interrupt status */ |
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HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
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HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
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HOST_EM_LOC = 0x1c, /* Enclosure Management location */ |
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HOST_EM_CTL = 0x20, /* Enclosure Management Control */ |
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HOST_CAP2 = 0x24, /* host capabilities, extended */ |
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/* HOST_CTL bits */ |
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HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
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HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
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HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ |
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HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
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/* HOST_CAP bits */ |
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HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ |
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HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ |
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HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ |
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HOST_CAP_PART = (1 << 13), /* Partial state capable */ |
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HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ |
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HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ |
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HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ |
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HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ |
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HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ |
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HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
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HOST_CAP_LED = (1 << 25), /* Supports activity LED */ |
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HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ |
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HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
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HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ |
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HOST_CAP_SNTF = (1 << 29), /* SNotification register */ |
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HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
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HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
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/* HOST_CAP2 bits */ |
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HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ |
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HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ |
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HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ |
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HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ |
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HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ |
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HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ |
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/* registers for each SATA port */ |
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PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
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PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
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PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
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PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
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PORT_IRQ_STAT = 0x10, /* interrupt status */ |
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PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
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PORT_CMD = 0x18, /* port command */ |
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PORT_TFDATA = 0x20, /* taskfile data */ |
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PORT_SIG = 0x24, /* device TF signature */ |
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PORT_CMD_ISSUE = 0x38, /* command issue */ |
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PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
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PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
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PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
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PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
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PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */ |
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PORT_FBS = 0x40, /* FIS-based Switching */ |
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PORT_DEVSLP = 0x44, /* device sleep */ |
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/* PORT_IRQ_{STAT,MASK} bits */ |
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PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
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PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
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PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
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PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
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PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
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PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
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PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
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PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
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PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
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PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
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PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
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PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
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PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
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PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
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PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
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PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
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PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
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PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
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PORT_IRQ_IF_ERR | |
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PORT_IRQ_CONNECT | |
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PORT_IRQ_PHYRDY | |
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PORT_IRQ_UNK_FIS | |
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PORT_IRQ_BAD_PMP, |
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PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
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PORT_IRQ_TF_ERR | |
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PORT_IRQ_HBUS_DATA_ERR, |
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DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
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PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
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PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
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/* PORT_CMD bits */ |
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PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ |
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PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ |
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PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
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PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ |
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PORT_CMD_ESP = (1 << 21), /* External Sata Port */ |
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PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ |
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PORT_CMD_PMP = (1 << 17), /* PMP attached */ |
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PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
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PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
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PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
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PORT_CMD_CLO = (1 << 3), /* Command list override */ |
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PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
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PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
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PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
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PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
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PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
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PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
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PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
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/* PORT_FBS bits */ |
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PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ |
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PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ |
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PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ |
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PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ |
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PORT_FBS_SDE = (1 << 2), /* FBS single device error */ |
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PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ |
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PORT_FBS_EN = (1 << 0), /* Enable FBS */ |
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/* PORT_DEVSLP bits */ |
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PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ |
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PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */ |
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PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ |
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PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ |
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PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ |
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PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ |
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PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ |
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/* hpriv->flags bits */ |
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#define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
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AHCI_HFLAG_NO_NCQ = (1 << 0), |
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AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ |
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AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ |
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AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ |
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AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ |
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AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ |
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AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ |
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AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ |
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AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ |
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AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ |
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AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as |
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link offline */ |
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AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ |
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AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ |
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AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ |
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AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on |
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port start (wait until |
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error-handling stage) */ |
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AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ |
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AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ |
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#ifdef CONFIG_PCI_MSI |
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AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */ |
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#else |
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/* compile out MSI infrastructure */ |
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AHCI_HFLAG_MULTI_MSI = 0, |
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#endif |
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AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ |
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AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */ |
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AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read |
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only registers */ |
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AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use |
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SATA_MOBILE_LPM_POLICY |
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as default lpm_policy */ |
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AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during |
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suspend/resume */ |
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AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP |
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from phy_power_on() */ |
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AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */ |
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/* ap->flags bits */ |
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AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
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ATA_FLAG_ACPI_SATA | ATA_FLAG_AN, |
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ICH_MAP = 0x90, /* ICH MAP register */ |
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PCS_6 = 0x92, /* 6 port PCS */ |
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PCS_7 = 0x94, /* 7+ port PCS (Denverton) */ |
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/* em constants */ |
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EM_MAX_SLOTS = 8, |
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EM_MAX_RETRY = 5, |
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/* em_ctl bits */ |
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EM_CTL_RST = (1 << 9), /* Reset */ |
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EM_CTL_TM = (1 << 8), /* Transmit Message */ |
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EM_CTL_MR = (1 << 0), /* Message Received */ |
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EM_CTL_ALHD = (1 << 26), /* Activity LED */ |
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EM_CTL_XMT = (1 << 25), /* Transmit Only */ |
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EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ |
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EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ |
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EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ |
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EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ |
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EM_CTL_LED = (1 << 16), /* LED messages supported */ |
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/* em message type */ |
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EM_MSG_TYPE_LED = (1 << 0), /* LED */ |
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EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ |
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EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ |
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EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ |
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}; |
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struct ahci_cmd_hdr { |
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__le32 opts; |
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__le32 status; |
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__le32 tbl_addr; |
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__le32 tbl_addr_hi; |
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__le32 reserved[4]; |
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}; |
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struct ahci_sg { |
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__le32 addr; |
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__le32 addr_hi; |
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__le32 reserved; |
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__le32 flags_size; |
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}; |
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struct ahci_em_priv { |
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enum sw_activity blink_policy; |
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struct timer_list timer; |
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unsigned long saved_activity; |
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unsigned long activity; |
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unsigned long led_state; |
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struct ata_link *link; |
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}; |
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struct ahci_port_priv { |
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struct ata_link *active_link; |
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struct ahci_cmd_hdr *cmd_slot; |
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dma_addr_t cmd_slot_dma; |
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void *cmd_tbl; |
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dma_addr_t cmd_tbl_dma; |
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void *rx_fis; |
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dma_addr_t rx_fis_dma; |
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/* for NCQ spurious interrupt analysis */ |
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unsigned int ncq_saw_d2h:1; |
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unsigned int ncq_saw_dmas:1; |
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unsigned int ncq_saw_sdb:1; |
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spinlock_t lock; /* protects parent ata_port */ |
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u32 intr_mask; /* interrupts to enable */ |
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bool fbs_supported; /* set iff FBS is supported */ |
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bool fbs_enabled; /* set iff FBS is enabled */ |
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int fbs_last_dev; /* save FBS.DEV of last FIS */ |
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/* enclosure management info per PM slot */ |
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struct ahci_em_priv em_priv[EM_MAX_SLOTS]; |
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char *irq_desc; /* desc in /proc/interrupts */ |
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}; |
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struct ahci_host_priv { |
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/* Input fields */ |
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unsigned int flags; /* AHCI_HFLAG_* */ |
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u32 force_port_map; /* force port map */ |
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u32 mask_port_map; /* mask out particular bits */ |
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void __iomem * mmio; /* bus-independent mem map */ |
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u32 cap; /* cap to use */ |
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u32 cap2; /* cap2 to use */ |
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u32 version; /* cached version */ |
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u32 port_map; /* port map to use */ |
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u32 saved_cap; /* saved initial cap */ |
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u32 saved_cap2; /* saved initial cap2 */ |
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u32 saved_port_map; /* saved initial port_map */ |
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u32 em_loc; /* enclosure management location */ |
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u32 em_buf_sz; /* EM buffer size in byte */ |
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u32 em_msg_type; /* EM message type */ |
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u32 remapped_nvme; /* NVMe remapped device count */ |
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bool got_runtime_pm; /* Did we do pm_runtime_get? */ |
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struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ |
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struct reset_control *rsts; /* Optional */ |
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struct regulator **target_pwrs; /* Optional */ |
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struct regulator *ahci_regulator;/* Optional */ |
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struct regulator *phy_regulator;/* Optional */ |
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/* |
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* If platform uses PHYs. There is a 1:1 relation between the port number and |
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* the PHY position in this array. |
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*/ |
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struct phy **phys; |
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unsigned nports; /* Number of ports */ |
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void *plat_data; /* Other platform data */ |
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unsigned int irq; /* interrupt line */ |
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/* |
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* Optional ahci_start_engine override, if not set this gets set to the |
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* default ahci_start_engine during ahci_save_initial_config, this can |
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* be overridden anytime before the host is activated. |
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*/ |
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void (*start_engine)(struct ata_port *ap); |
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/* |
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* Optional ahci_stop_engine override, if not set this gets set to the |
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* default ahci_stop_engine during ahci_save_initial_config, this can |
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* be overridden anytime before the host is activated. |
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*/ |
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int (*stop_engine)(struct ata_port *ap); |
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irqreturn_t (*irq_handler)(int irq, void *dev_instance); |
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/* only required for per-port MSI(-X) support */ |
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int (*get_irq_vector)(struct ata_host *host, |
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int port); |
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}; |
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extern int ahci_ignore_sss; |
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extern struct device_attribute *ahci_shost_attrs[]; |
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extern struct device_attribute *ahci_sdev_attrs[]; |
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/* |
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* This must be instantiated by the edge drivers. Read the comments |
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* for ATA_BASE_SHT |
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*/ |
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#define AHCI_SHT(drv_name) \ |
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ATA_NCQ_SHT(drv_name), \ |
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.can_queue = AHCI_MAX_CMDS, \ |
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.sg_tablesize = AHCI_MAX_SG, \ |
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.dma_boundary = AHCI_DMA_BOUNDARY, \ |
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.shost_attrs = ahci_shost_attrs, \ |
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.sdev_attrs = ahci_sdev_attrs |
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extern struct ata_port_operations ahci_ops; |
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extern struct ata_port_operations ahci_platform_ops; |
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extern struct ata_port_operations ahci_pmp_retry_srst_ops; |
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unsigned int ahci_dev_classify(struct ata_port *ap); |
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void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
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u32 opts); |
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void ahci_save_initial_config(struct device *dev, |
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struct ahci_host_priv *hpriv); |
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void ahci_init_controller(struct ata_host *host); |
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int ahci_reset_controller(struct ata_host *host); |
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int ahci_do_softreset(struct ata_link *link, unsigned int *class, |
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int pmp, unsigned long deadline, |
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int (*check_ready)(struct ata_link *link)); |
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int ahci_do_hardreset(struct ata_link *link, unsigned int *class, |
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unsigned long deadline, bool *online); |
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unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
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int ahci_stop_engine(struct ata_port *ap); |
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void ahci_start_fis_rx(struct ata_port *ap); |
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void ahci_start_engine(struct ata_port *ap); |
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int ahci_check_ready(struct ata_link *link); |
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int ahci_kick_engine(struct ata_port *ap); |
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int ahci_port_resume(struct ata_port *ap); |
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void ahci_set_em_messages(struct ahci_host_priv *hpriv, |
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struct ata_port_info *pi); |
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int ahci_reset_em(struct ata_host *host); |
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void ahci_print_info(struct ata_host *host, const char *scc_s); |
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int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht); |
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void ahci_error_handler(struct ata_port *ap); |
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u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked); |
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static inline void __iomem *__ahci_port_base(struct ata_host *host, |
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unsigned int port_no) |
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{ |
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struct ahci_host_priv *hpriv = host->private_data; |
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void __iomem *mmio = hpriv->mmio; |
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return mmio + 0x100 + (port_no * 0x80); |
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} |
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static inline void __iomem *ahci_port_base(struct ata_port *ap) |
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{ |
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return __ahci_port_base(ap->host, ap->port_no); |
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} |
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static inline int ahci_nr_ports(u32 cap) |
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{ |
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return (cap & 0x1f) + 1; |
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} |
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#endif /* _AHCI_H */
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