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95 lines
2.2 KiB
95 lines
2.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* arch/sh/mm/tlb-sh3.c |
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* |
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* SH-3 specific TLB operations |
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* |
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* Copyright (C) 1999 Niibe Yutaka |
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* Copyright (C) 2002 Paul Mundt |
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*/ |
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#include <linux/signal.h> |
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#include <linux/sched.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/types.h> |
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#include <linux/ptrace.h> |
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#include <linux/mman.h> |
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#include <linux/mm.h> |
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#include <linux/smp.h> |
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#include <linux/interrupt.h> |
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#include <asm/io.h> |
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#include <linux/uaccess.h> |
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#include <asm/mmu_context.h> |
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#include <asm/cacheflush.h> |
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
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{ |
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unsigned long flags, pteval, vpn; |
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/* |
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* Handle debugger faulting in for debugee. |
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*/ |
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if (vma && current->active_mm != vma->vm_mm) |
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return; |
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local_irq_save(flags); |
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/* Set PTEH register */ |
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vpn = (address & MMU_VPN_MASK) | get_asid(); |
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__raw_writel(vpn, MMU_PTEH); |
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pteval = pte_val(pte); |
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/* Set PTEL register */ |
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ |
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/* conveniently, we want all the software flags to be 0 anyway */ |
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__raw_writel(pteval, MMU_PTEL); |
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/* Load the TLB */ |
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); |
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local_irq_restore(flags); |
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} |
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void local_flush_tlb_one(unsigned long asid, unsigned long page) |
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{ |
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unsigned long addr, data; |
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int i, ways = MMU_NTLB_WAYS; |
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/* |
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* NOTE: PTEH.ASID should be set to this MM |
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* _AND_ we need to write ASID to the array. |
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* |
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* It would be simple if we didn't need to set PTEH.ASID... |
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*/ |
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addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000); |
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data = (page & 0xfffe0000) | asid; /* VALID bit is off */ |
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if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) { |
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addr |= MMU_PAGE_ASSOC_BIT; |
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ways = 1; /* we already know the way .. */ |
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} |
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for (i = 0; i < ways; i++) |
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__raw_writel(data, addr + (i << 8)); |
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} |
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void local_flush_tlb_all(void) |
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{ |
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unsigned long flags, status; |
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/* |
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* Flush all the TLB. |
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* |
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* Write to the MMU control register's bit: |
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* TF-bit for SH-3, TI-bit for SH-4. |
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* It's same position, bit #2. |
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*/ |
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local_irq_save(flags); |
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status = __raw_readl(MMUCR); |
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status |= 0x04; |
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__raw_writel(status, MMUCR); |
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ctrl_barrier(); |
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local_irq_restore(flags); |
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}
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