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390 lines
12 KiB
390 lines
12 KiB
/* |
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* Copyright (c) 2003-2014 Broadcom Corporation |
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* All Rights Reserved |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the Broadcom |
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* license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <linux/dma-mapping.h> |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/irq.h> |
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#include <linux/bitops.h> |
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#include <linux/pci_ids.h> |
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#include <linux/nodemask.h> |
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#include <asm/cpu.h> |
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#include <asm/mipsregs.h> |
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#include <asm/netlogic/common.h> |
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#include <asm/netlogic/haldefs.h> |
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#include <asm/netlogic/mips-extns.h> |
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#include <asm/netlogic/xlp-hal/xlp.h> |
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#include <asm/netlogic/xlp-hal/iomap.h> |
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#define SATA_CTL 0x0 |
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#define SATA_STATUS 0x1 /* Status Reg */ |
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#define SATA_INT 0x2 /* Interrupt Reg */ |
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#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */ |
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#define SATA_BIU_TIMEOUT 0x4 |
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#define AXIWRSPERRLOG 0x5 |
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#define AXIRDSPERRLOG 0x6 |
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#define BiuTimeoutLow 0x7 |
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#define BiuTimeoutHi 0x8 |
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#define BiuSlvErLow 0x9 |
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#define BiuSlvErHi 0xa |
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#define IO_CONFIG_SWAP_DIS 0xb |
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#define CR_REG_TIMER 0xc |
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#define CORE_ID 0xd |
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#define AXI_SLAVE_OPT1 0xe |
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#define PHY_MEM_ACCESS 0xf |
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#define PHY0_CNTRL 0x10 |
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#define PHY0_STAT 0x11 |
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#define PHY0_RX_ALIGN 0x12 |
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#define PHY0_RX_EQ_LO 0x13 |
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#define PHY0_RX_EQ_HI 0x14 |
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#define PHY0_BIST_LOOP 0x15 |
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#define PHY1_CNTRL 0x16 |
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#define PHY1_STAT 0x17 |
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#define PHY1_RX_ALIGN 0x18 |
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#define PHY1_RX_EQ_LO 0x19 |
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#define PHY1_RX_EQ_HI 0x1a |
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#define PHY1_BIST_LOOP 0x1b |
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#define RdExBase 0x1c |
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#define RdExLimit 0x1d |
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#define CacheAllocBase 0x1e |
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#define CacheAllocLimit 0x1f |
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#define BiuSlaveCmdGstNum 0x20 |
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/*SATA_CTL Bits */ |
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#define SATA_RST_N BIT(0) /* Active low reset sata_core phy */ |
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#define SataCtlReserve0 BIT(1) |
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#define M_CSYSREQ BIT(2) /* AXI master low power, not used */ |
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#define S_CSYSREQ BIT(3) /* AXI slave low power, not used */ |
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#define P0_CP_DET BIT(8) /* Reserved, bring in from pad */ |
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#define P0_MP_SW BIT(9) /* Mech Switch */ |
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#define P0_DISABLE BIT(10) /* disable p0 */ |
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#define P0_ACT_LED_EN BIT(11) /* Active LED enable */ |
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#define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */ |
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#define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */ |
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#define P0_IRST_POR BIT(14) /* PHY power on reset*/ |
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#define P0_IPDTXL BIT(15) /* PHY Tx lane dis/power down */ |
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#define P0_IPDRXL BIT(16) /* PHY Rx lane dis/power down */ |
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#define P0_IPDIPDMSYNTH BIT(17) /* PHY synthesizer dis/porwer down */ |
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#define P0_CP_POD_EN BIT(18) /* CP_POD enable */ |
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#define P0_AT_BYPASS BIT(19) /* P0 address translation by pass */ |
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#define P1_CP_DET BIT(20) /* Reserved,Cold Detect */ |
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#define P1_MP_SW BIT(21) /* Mech Switch */ |
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#define P1_DISABLE BIT(22) /* disable p1 */ |
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#define P1_ACT_LED_EN BIT(23) /* Active LED enable */ |
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#define P1_IRST_HARD_SYNTH BIT(24) /* PHY hard synth reset */ |
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#define P1_IRST_HARD_TXRX BIT(25) /* PHY lane hard reset */ |
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#define P1_IRST_POR BIT(26) /* PHY power on reset*/ |
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#define P1_IPDTXL BIT(27) /* PHY Tx lane dis/porwer down */ |
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#define P1_IPDRXL BIT(28) /* PHY Rx lane dis/porwer down */ |
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#define P1_IPDIPDMSYNTH BIT(29) /* PHY synthesizer dis/porwer down */ |
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#define P1_CP_POD_EN BIT(30) |
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#define P1_AT_BYPASS BIT(31) /* P1 address translation by pass */ |
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/* Status register */ |
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#define M_CACTIVE BIT(0) /* m_cactive, not used */ |
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#define S_CACTIVE BIT(1) /* s_cactive, not used */ |
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#define P0_PHY_READY BIT(8) /* phy is ready */ |
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#define P0_CP_POD BIT(9) /* Cold PowerOn */ |
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#define P0_SLUMBER BIT(10) /* power mode slumber */ |
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#define P0_PATIAL BIT(11) /* power mode patial */ |
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#define P0_PHY_SIG_DET BIT(12) /* phy dignal detect */ |
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#define P0_PHY_CALI BIT(13) /* phy calibration done */ |
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#define P1_PHY_READY BIT(16) /* phy is ready */ |
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#define P1_CP_POD BIT(17) /* Cold PowerOn */ |
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#define P1_SLUMBER BIT(18) /* power mode slumber */ |
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#define P1_PATIAL BIT(19) /* power mode patial */ |
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#define P1_PHY_SIG_DET BIT(20) /* phy dignal detect */ |
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#define P1_PHY_CALI BIT(21) /* phy calibration done */ |
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/* SATA CR_REG_TIMER bits */ |
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#define CR_TIME_SCALE (0x1000 << 0) |
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/* SATA PHY specific registers start and end address */ |
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#define RXCDRCALFOSC0 0x0065 |
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#define CALDUTY 0x006e |
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#define RXDPIF 0x8065 |
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#define PPMDRIFTMAX_HI 0x80A4 |
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#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r) |
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#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) |
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#define nlm_get_sata_pcibase(node) \ |
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nlm_pcicfg_base(XLP9XX_IO_SATA_OFFSET(node)) |
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#define nlm_get_sata_regbase(node) \ |
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(nlm_get_sata_pcibase(node) + 0x100) |
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/* SATA PHY config for register block 1 0x0065 .. 0x006e */ |
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static const u8 sata_phy_config1[] = { |
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0xC9, 0xC9, 0x07, 0x07, 0x18, 0x18, 0x01, 0x01, 0x22, 0x00 |
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}; |
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/* SATA PHY config for register block 2 0x8065 .. 0x80A4 */ |
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static const u8 sata_phy_config2[] = { |
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0xAA, 0x00, 0x4C, 0xC9, 0xC9, 0x07, 0x07, 0x18, |
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0x18, 0x05, 0x0C, 0x10, 0x00, 0x10, 0x00, 0xFF, |
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0xCF, 0xF7, 0xE1, 0xF5, 0xFD, 0xFD, 0xFF, 0xFF, |
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0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, 0xFD, 0xFD, |
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0xF5, 0xF5, 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, |
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0xFD, 0xFD, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xF5, |
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0x3F, 0x00, 0x32, 0x00, 0x03, 0x01, 0x05, 0x05, |
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0x04, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04, |
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}; |
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const int sata_phy_debug = 0; /* set to verify PHY writes */ |
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static void sata_clear_glue_reg(u64 regbase, u32 off, u32 bit) |
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{ |
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u32 reg_val; |
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reg_val = nlm_read_sata_reg(regbase, off); |
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nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); |
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} |
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static void sata_set_glue_reg(u64 regbase, u32 off, u32 bit) |
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{ |
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u32 reg_val; |
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reg_val = nlm_read_sata_reg(regbase, off); |
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nlm_write_sata_reg(regbase, off, (reg_val | bit)); |
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} |
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static void write_phy_reg(u64 regbase, u32 addr, u32 physel, u8 data) |
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{ |
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nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, |
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(1u << 31) | (physel << 24) | (data << 16) | addr); |
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udelay(850); |
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} |
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static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) |
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{ |
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u32 val; |
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nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, |
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(0 << 31) | (physel << 24) | (0 << 16) | addr); |
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udelay(850); |
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val = nlm_read_sata_reg(regbase, PHY_MEM_ACCESS); |
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return (val >> 16) & 0xff; |
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} |
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static void config_sata_phy(u64 regbase) |
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{ |
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u32 port, i, reg; |
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u8 val; |
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for (port = 0; port < 2; port++) { |
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for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) |
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write_phy_reg(regbase, reg, port, sata_phy_config1[i]); |
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for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) |
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write_phy_reg(regbase, reg, port, sata_phy_config2[i]); |
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/* Fix for PHY link up failures at lower temperatures */ |
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write_phy_reg(regbase, 0x800F, port, 0x1f); |
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val = read_phy_reg(regbase, 0x0029, port); |
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write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); |
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val = read_phy_reg(regbase, 0x0056, port); |
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write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); |
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val = read_phy_reg(regbase, 0x0018, port); |
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write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); |
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} |
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} |
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static void check_phy_register(u64 regbase, u32 addr, u32 physel, u8 xdata) |
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{ |
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u8 data; |
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data = read_phy_reg(regbase, addr, physel); |
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pr_info("PHY read addr = 0x%x physel = %d data = 0x%x %s\n", |
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addr, physel, data, data == xdata ? "TRUE" : "FALSE"); |
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} |
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static void verify_sata_phy_config(u64 regbase) |
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{ |
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u32 port, i, reg; |
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for (port = 0; port < 2; port++) { |
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for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) |
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check_phy_register(regbase, reg, port, |
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sata_phy_config1[i]); |
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for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) |
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check_phy_register(regbase, reg, port, |
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sata_phy_config2[i]); |
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} |
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} |
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static void nlm_sata_firmware_init(int node) |
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{ |
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u32 reg_val; |
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u64 regbase; |
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int n; |
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pr_info("Initializing XLP9XX On-chip AHCI...\n"); |
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regbase = nlm_get_sata_regbase(node); |
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/* Reset port0 */ |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_POR); |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDTXL); |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDRXL); |
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sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); |
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/* port1 */ |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_POR); |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDTXL); |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDRXL); |
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sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); |
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udelay(300); |
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/* Set PHY */ |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IPDTXL); |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IPDRXL); |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IPDTXL); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IPDRXL); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); |
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udelay(1000); |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_POR); |
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udelay(1000); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_POR); |
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udelay(1000); |
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/* setup PHY */ |
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config_sata_phy(regbase); |
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if (sata_phy_debug) |
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verify_sata_phy_config(regbase); |
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udelay(1000); |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); |
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sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); |
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sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); |
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udelay(300); |
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/* Override reset in serial PHY mode */ |
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sata_set_glue_reg(regbase, CR_REG_TIMER, CR_TIME_SCALE); |
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/* Set reset SATA */ |
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sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N); |
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sata_set_glue_reg(regbase, SATA_CTL, M_CSYSREQ); |
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sata_set_glue_reg(regbase, SATA_CTL, S_CSYSREQ); |
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pr_debug("Waiting for PHYs to come up.\n"); |
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n = 10000; |
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do { |
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reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); |
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if ((reg_val & P1_PHY_READY) && (reg_val & P0_PHY_READY)) |
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break; |
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udelay(10); |
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} while (--n > 0); |
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if (reg_val & P0_PHY_READY) |
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pr_info("PHY0 is up.\n"); |
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else |
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pr_info("PHY0 is down.\n"); |
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if (reg_val & P1_PHY_READY) |
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pr_info("PHY1 is up.\n"); |
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else |
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pr_info("PHY1 is down.\n"); |
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pr_info("XLP AHCI Init Done.\n"); |
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} |
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static int __init nlm_ahci_init(void) |
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{ |
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int node; |
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if (!cpu_is_xlp9xx()) |
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return 0; |
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for (node = 0; node < NLM_NR_NODES; node++) |
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if (nlm_node_present(node)) |
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nlm_sata_firmware_init(node); |
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return 0; |
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} |
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static void nlm_sata_intr_ack(struct irq_data *data) |
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{ |
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u64 regbase; |
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u32 val; |
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int node; |
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node = data->irq / NLM_IRQS_PER_NODE; |
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regbase = nlm_get_sata_regbase(node); |
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val = nlm_read_sata_reg(regbase, SATA_INT); |
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sata_set_glue_reg(regbase, SATA_INT, val); |
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} |
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static void nlm_sata_fixup_bar(struct pci_dev *dev) |
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{ |
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dev->resource[5] = dev->resource[0]; |
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memset(&dev->resource[0], 0, sizeof(dev->resource[0])); |
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} |
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static void nlm_sata_fixup_final(struct pci_dev *dev) |
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{ |
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u32 val; |
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u64 regbase; |
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int node; |
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/* Find end bridge function to find node */ |
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node = xlp_socdev_to_node(dev); |
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regbase = nlm_get_sata_regbase(node); |
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/* clear pending interrupts and then enable them */ |
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val = nlm_read_sata_reg(regbase, SATA_INT); |
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sata_set_glue_reg(regbase, SATA_INT, val); |
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/* Enable only the core interrupt */ |
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sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); |
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dev->irq = nlm_irq_to_xirq(node, PIC_SATA_IRQ); |
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nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack); |
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} |
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arch_initcall(nlm_ahci_init); |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, |
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nlm_sata_fixup_bar); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, |
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nlm_sata_fixup_final);
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