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96 lines
2.6 KiB
96 lines
2.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* arch/arm/mach-footbridge/include/mach/hardware.h |
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* |
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* Copyright (C) 1998-1999 Russell King. |
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* |
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* This file contains the hardware definitions of the EBSA-285. |
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*/ |
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#ifndef __ASM_ARCH_HARDWARE_H |
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#define __ASM_ARCH_HARDWARE_H |
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/* Virtual Physical Size |
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* 0xff800000 0x40000000 1MB X-Bus |
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* 0xff000000 0x7c000000 1MB PCI I/O space |
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* 0xfe000000 0x42000000 1MB CSR |
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* 0xfd000000 0x78000000 1MB Outbound write flush (not supported) |
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* 0xfc000000 0x79000000 1MB PCI IACK/special space |
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* 0xfb000000 0x7a000000 16MB PCI Config type 1 |
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* 0xfa000000 0x7b000000 16MB PCI Config type 0 |
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* 0xf9000000 0x50000000 1MB Cache flush |
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* 0xf0000000 0x80000000 16MB ISA memory |
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*/ |
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#ifdef CONFIG_MMU |
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#define MMU_IO(a, b) (a) |
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#else |
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#define MMU_IO(a, b) (b) |
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#endif |
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#define XBUS_SIZE 0x00100000 |
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#define XBUS_BASE MMU_IO(0xff800000, 0x40000000) |
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#define ARMCSR_SIZE 0x00100000 |
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#define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) |
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#define WFLUSH_SIZE 0x00100000 |
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#define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) |
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#define PCIIACK_SIZE 0x00100000 |
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#define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) |
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#define PCICFG1_SIZE 0x01000000 |
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#define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) |
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#define PCICFG0_SIZE 0x01000000 |
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#define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) |
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#define PCIMEM_SIZE 0x01000000 |
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#define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) |
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#define XBUS_CS2 0x40012000 |
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#define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000)) |
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#define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15) |
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#define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4)) |
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#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5)) |
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#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6)) |
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#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108) /* CSR_ROMBASEMASK */ |
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/* PIC irq control */ |
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#define PIC_LO 0x20 |
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#define PIC_MASK_LO 0x21 |
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#define PIC_HI 0xA0 |
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#define PIC_MASK_HI 0xA1 |
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/* GPIO pins */ |
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#define GPIO_CCLK 0x800 |
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#define GPIO_DSCLK 0x400 |
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#define GPIO_E2CLK 0x200 |
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#define GPIO_IOLOAD 0x100 |
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#define GPIO_RED_LED 0x080 |
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#define GPIO_WDTIMER 0x040 |
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#define GPIO_DATA 0x020 |
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#define GPIO_IOCLK 0x010 |
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#define GPIO_DONE 0x008 |
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#define GPIO_FAN 0x004 |
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#define GPIO_GREEN_LED 0x002 |
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#define GPIO_RESET 0x001 |
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/* CPLD pins */ |
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#define CPLD_DS_ENABLE 8 |
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#define CPLD_7111_DISABLE 4 |
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#define CPLD_UNMUTE 2 |
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#define CPLD_FLASH_WR_ENABLE 1 |
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#ifndef __ASSEMBLY__ |
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extern raw_spinlock_t nw_gpio_lock; |
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extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); |
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extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); |
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extern unsigned int nw_gpio_read(void); |
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extern void nw_cpld_modify(unsigned int mask, unsigned int set); |
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#endif |
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#endif
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