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238 lines
5.7 KiB
238 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_eb64p.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* |
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* Code supporting the EB64+ and EB66. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_apecs.h> |
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#include <asm/core_lca.h> |
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#include <asm/hwrpb.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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/* Note mask bit is true for DISABLED irqs. */ |
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static unsigned int cached_irq_mask = -1; |
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static inline void |
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eb64p_update_irq_hw(unsigned int irq, unsigned long mask) |
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{ |
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outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26)); |
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} |
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static inline void |
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eb64p_enable_irq(struct irq_data *d) |
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{ |
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eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); |
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} |
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static void |
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eb64p_disable_irq(struct irq_data *d) |
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{ |
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eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq); |
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} |
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static struct irq_chip eb64p_irq_type = { |
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.name = "EB64P", |
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.irq_unmask = eb64p_enable_irq, |
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.irq_mask = eb64p_disable_irq, |
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.irq_mask_ack = eb64p_disable_irq, |
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}; |
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static void |
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eb64p_device_interrupt(unsigned long vector) |
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{ |
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unsigned long pld; |
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unsigned int i; |
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/* Read the interrupt summary registers */ |
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pld = inb(0x26) | (inb(0x27) << 8); |
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/* |
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* Now, for every possible bit set, work through |
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* them and call the appropriate interrupt handler. |
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*/ |
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while (pld) { |
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i = ffz(~pld); |
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pld &= pld - 1; /* clear least bit set */ |
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if (i == 5) { |
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isa_device_interrupt(vector); |
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} else { |
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handle_irq(16 + i); |
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} |
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} |
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} |
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static void __init |
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eb64p_init_irq(void) |
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{ |
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long i; |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) |
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/* |
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* CABRIO SRM may not set variation correctly, so here we test |
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* the high word of the interrupt summary register for the RAZ |
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* bits, and hope that a true EB64+ would read all ones... |
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*/ |
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if (inw(0x806) != 0xffff) { |
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extern struct alpha_machine_vector cabriolet_mv; |
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printk("Detected Cabriolet: correcting HWRPB.\n"); |
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hwrpb->sys_variation |= 2L << 10; |
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hwrpb_update_checksum(hwrpb); |
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alpha_mv = cabriolet_mv; |
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alpha_mv.init_irq(); |
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return; |
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} |
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#endif /* GENERIC */ |
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outb(0xff, 0x26); |
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outb(0xff, 0x27); |
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init_i8259a_irqs(); |
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for (i = 16; i < 32; ++i) { |
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irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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common_init_isa_dma(); |
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if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL)) |
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pr_err("Failed to register isa-cascade interrupt\n"); |
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} |
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/* |
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* PCI Fixup configuration. |
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* |
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* There are two 8 bit external summary registers as follows: |
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* |
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* Summary @ 0x26: |
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* Bit Meaning |
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* 0 Interrupt Line A from slot 0 |
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* 1 Interrupt Line A from slot 1 |
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* 2 Interrupt Line B from slot 0 |
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* 3 Interrupt Line B from slot 1 |
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* 4 Interrupt Line C from slot 0 |
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* 5 Interrupt line from the two ISA PICs |
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* 6 Tulip |
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* 7 NCR SCSI |
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* |
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* Summary @ 0x27 |
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* Bit Meaning |
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* 0 Interrupt Line C from slot 1 |
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* 1 Interrupt Line D from slot 0 |
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* 2 Interrupt Line D from slot 1 |
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* 3 RAZ |
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* 4 RAZ |
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* 5 RAZ |
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* 6 RAZ |
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* 7 RAZ |
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* |
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* The device to slot mapping looks like: |
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* |
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* Slot Device |
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* 5 NCR SCSI controller |
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* 6 PCI on board slot 0 |
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* 7 PCI on board slot 1 |
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* 8 Intel SIO PCI-ISA bridge chip |
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* 9 Tulip - DECchip 21040 Ethernet controller |
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* |
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* |
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* This two layered interrupt approach means that we allocate IRQ 16 and |
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* above for PCI interrupts. The IRQ relates to which bit the interrupt |
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* comes in on. This makes interrupt processing much easier. |
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*/ |
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static int |
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eb64p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[5][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */ |
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{16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */ |
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{16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ |
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{16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */ |
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}; |
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const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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/* |
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* The System Vector |
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*/ |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P) |
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struct alpha_machine_vector eb64p_mv __initmv = { |
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.vector_name = "EB64+", |
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DO_EV4_MMU, |
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DO_DEFAULT_RTC, |
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DO_APECS_IO, |
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.machine_check = apecs_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, |
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.nr_irqs = 32, |
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.device_interrupt = eb64p_device_interrupt, |
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.init_arch = apecs_init_arch, |
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.init_irq = eb64p_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = common_init_pci, |
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.kill_arch = NULL, |
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.pci_map_irq = eb64p_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(eb64p) |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66) |
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struct alpha_machine_vector eb66_mv __initmv = { |
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.vector_name = "EB66", |
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DO_EV4_MMU, |
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DO_DEFAULT_RTC, |
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DO_LCA_IO, |
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.machine_check = lca_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, |
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.nr_irqs = 32, |
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.device_interrupt = eb64p_device_interrupt, |
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.init_arch = lca_init_arch, |
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.init_irq = eb64p_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = common_init_pci, |
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.pci_map_irq = eb64p_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(eb66) |
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#endif
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