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401 lines
10 KiB
401 lines
10 KiB
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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// |
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// Copyright (c) 2018 BayLibre, SAS. |
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// Author: Jerome Brunet <[email protected]> |
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#include <linux/clk.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/module.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/soc-dai.h> |
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#include "axg-fifo.h" |
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/* |
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* This file implements the platform operations common to the playback and |
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* capture frontend DAI. The logic behind this two types of fifo is very |
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* similar but some difference exist. |
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* These differences are handled in the respective DAI drivers |
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*/ |
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static struct snd_pcm_hardware axg_fifo_hw = { |
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.info = (SNDRV_PCM_INFO_INTERLEAVED | |
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SNDRV_PCM_INFO_MMAP | |
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SNDRV_PCM_INFO_MMAP_VALID | |
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SNDRV_PCM_INFO_BLOCK_TRANSFER | |
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SNDRV_PCM_INFO_PAUSE), |
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.formats = AXG_FIFO_FORMATS, |
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.rate_min = 5512, |
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.rate_max = 192000, |
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.channels_min = 1, |
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.channels_max = AXG_FIFO_CH_MAX, |
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.period_bytes_min = AXG_FIFO_BURST, |
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.period_bytes_max = UINT_MAX, |
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.periods_min = 2, |
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.periods_max = UINT_MAX, |
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/* No real justification for this */ |
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.buffer_bytes_max = 1 * 1024 * 1024, |
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}; |
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static struct snd_soc_dai *axg_fifo_dai(struct snd_pcm_substream *ss) |
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{ |
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struct snd_soc_pcm_runtime *rtd = ss->private_data; |
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return asoc_rtd_to_cpu(rtd, 0); |
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} |
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static struct axg_fifo *axg_fifo_data(struct snd_pcm_substream *ss) |
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{ |
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struct snd_soc_dai *dai = axg_fifo_dai(ss); |
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return snd_soc_dai_get_drvdata(dai); |
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} |
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static struct device *axg_fifo_dev(struct snd_pcm_substream *ss) |
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{ |
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struct snd_soc_dai *dai = axg_fifo_dai(ss); |
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return dai->dev; |
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} |
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static void __dma_enable(struct axg_fifo *fifo, bool enable) |
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{ |
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regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, |
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enable ? CTRL0_DMA_EN : 0); |
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} |
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int axg_fifo_pcm_trigger(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss, int cmd) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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case SNDRV_PCM_TRIGGER_RESUME: |
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
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__dma_enable(fifo, true); |
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break; |
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case SNDRV_PCM_TRIGGER_SUSPEND: |
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
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case SNDRV_PCM_TRIGGER_STOP: |
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__dma_enable(fifo, false); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_trigger); |
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snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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struct snd_pcm_runtime *runtime = ss->runtime; |
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unsigned int addr; |
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regmap_read(fifo->map, FIFO_STATUS2, &addr); |
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return bytes_to_frames(runtime, addr - (unsigned int)runtime->dma_addr); |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_pointer); |
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int axg_fifo_pcm_hw_params(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss, |
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struct snd_pcm_hw_params *params) |
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{ |
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struct snd_pcm_runtime *runtime = ss->runtime; |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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unsigned int burst_num, period, threshold; |
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dma_addr_t end_ptr; |
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period = params_period_bytes(params); |
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/* Setup dma memory pointers */ |
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end_ptr = runtime->dma_addr + runtime->dma_bytes - AXG_FIFO_BURST; |
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regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr); |
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regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr); |
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/* Setup interrupt periodicity */ |
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burst_num = period / AXG_FIFO_BURST; |
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regmap_write(fifo->map, FIFO_INT_ADDR, burst_num); |
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/* |
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* Start the fifo request on the smallest of the following: |
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* - Half the fifo size |
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* - Half the period size |
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*/ |
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threshold = min(period / 2, fifo->depth / 2); |
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/* |
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* With the threshold in bytes, register value is: |
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* V = (threshold / burst) - 1 |
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*/ |
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threshold /= AXG_FIFO_BURST; |
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regmap_field_write(fifo->field_threshold, |
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threshold ? threshold - 1 : 0); |
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/* Enable block count irq */ |
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regmap_update_bits(fifo->map, FIFO_CTRL0, |
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), |
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT)); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_params); |
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int g12a_fifo_pcm_hw_params(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss, |
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struct snd_pcm_hw_params *params) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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struct snd_pcm_runtime *runtime = ss->runtime; |
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int ret; |
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ret = axg_fifo_pcm_hw_params(component, ss, params); |
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if (ret) |
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return ret; |
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/* Set the initial memory address of the DMA */ |
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regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(g12a_fifo_pcm_hw_params); |
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int axg_fifo_pcm_hw_free(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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/* Disable the block count irq */ |
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regmap_update_bits(fifo->map, FIFO_CTRL0, |
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_hw_free); |
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static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask) |
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{ |
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regmap_update_bits(fifo->map, FIFO_CTRL1, |
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CTRL1_INT_CLR(FIFO_INT_MASK), |
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CTRL1_INT_CLR(mask)); |
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/* Clear must also be cleared */ |
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regmap_update_bits(fifo->map, FIFO_CTRL1, |
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CTRL1_INT_CLR(FIFO_INT_MASK), |
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0); |
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} |
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static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) |
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{ |
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struct snd_pcm_substream *ss = dev_id; |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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unsigned int status; |
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regmap_read(fifo->map, FIFO_STATUS1, &status); |
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status = STATUS1_INT_STS(status) & FIFO_INT_MASK; |
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if (status & FIFO_INT_COUNT_REPEAT) |
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snd_pcm_period_elapsed(ss); |
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else |
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dev_dbg(axg_fifo_dev(ss), "unexpected irq - STS 0x%02x\n", |
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status); |
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/* Ack irqs */ |
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axg_fifo_ack_irq(fifo, status); |
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return IRQ_RETVAL(status); |
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} |
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int axg_fifo_pcm_open(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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struct device *dev = axg_fifo_dev(ss); |
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int ret; |
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snd_soc_set_runtime_hwparams(ss, &axg_fifo_hw); |
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/* |
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* Make sure the buffer and period size are multiple of the FIFO |
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* burst |
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*/ |
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0, |
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SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
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AXG_FIFO_BURST); |
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if (ret) |
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return ret; |
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ret = snd_pcm_hw_constraint_step(ss->runtime, 0, |
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SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
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AXG_FIFO_BURST); |
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if (ret) |
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return ret; |
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ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0, |
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dev_name(dev), ss); |
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if (ret) |
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return ret; |
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/* Enable pclk to access registers and clock the fifo ip */ |
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ret = clk_prepare_enable(fifo->pclk); |
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if (ret) |
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goto free_irq; |
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/* Setup status2 so it reports the memory pointer */ |
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regmap_update_bits(fifo->map, FIFO_CTRL1, |
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CTRL1_STATUS2_SEL_MASK, |
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CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ)); |
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/* Make sure the dma is initially disabled */ |
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__dma_enable(fifo, false); |
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/* Disable irqs until params are ready */ |
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regmap_update_bits(fifo->map, FIFO_CTRL0, |
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CTRL0_INT_EN(FIFO_INT_MASK), 0); |
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/* Clear any pending interrupt */ |
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axg_fifo_ack_irq(fifo, FIFO_INT_MASK); |
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/* Take memory arbitror out of reset */ |
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ret = reset_control_deassert(fifo->arb); |
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if (ret) |
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goto free_clk; |
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return 0; |
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free_clk: |
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clk_disable_unprepare(fifo->pclk); |
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free_irq: |
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free_irq(fifo->irq, ss); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_open); |
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int axg_fifo_pcm_close(struct snd_soc_component *component, |
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struct snd_pcm_substream *ss) |
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{ |
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struct axg_fifo *fifo = axg_fifo_data(ss); |
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int ret; |
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/* Put the memory arbitror back in reset */ |
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ret = reset_control_assert(fifo->arb); |
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/* Disable fifo ip and register access */ |
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clk_disable_unprepare(fifo->pclk); |
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/* remove IRQ */ |
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free_irq(fifo->irq, ss); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_close); |
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int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type) |
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{ |
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struct snd_card *card = rtd->card->snd_card; |
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size_t size = axg_fifo_hw.buffer_bytes_max; |
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snd_pcm_set_managed_buffer(rtd->pcm->streams[type].substream, |
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SNDRV_DMA_TYPE_DEV, card->dev, |
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size, size); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_pcm_new); |
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static const struct regmap_config axg_fifo_regmap_cfg = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = FIFO_CTRL2, |
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}; |
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int axg_fifo_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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const struct axg_fifo_match_data *data; |
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struct axg_fifo *fifo; |
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void __iomem *regs; |
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int ret; |
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data = of_device_get_match_data(dev); |
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if (!data) { |
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dev_err(dev, "failed to match device\n"); |
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return -ENODEV; |
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} |
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fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL); |
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if (!fifo) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, fifo); |
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regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(regs)) |
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return PTR_ERR(regs); |
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fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg); |
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if (IS_ERR(fifo->map)) { |
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dev_err(dev, "failed to init regmap: %ld\n", |
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PTR_ERR(fifo->map)); |
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return PTR_ERR(fifo->map); |
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} |
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fifo->pclk = devm_clk_get(dev, NULL); |
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if (IS_ERR(fifo->pclk)) { |
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if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER) |
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dev_err(dev, "failed to get pclk: %ld\n", |
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PTR_ERR(fifo->pclk)); |
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return PTR_ERR(fifo->pclk); |
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} |
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fifo->arb = devm_reset_control_get_exclusive(dev, NULL); |
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if (IS_ERR(fifo->arb)) { |
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if (PTR_ERR(fifo->arb) != -EPROBE_DEFER) |
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dev_err(dev, "failed to get arb reset: %ld\n", |
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PTR_ERR(fifo->arb)); |
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return PTR_ERR(fifo->arb); |
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} |
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fifo->irq = of_irq_get(dev->of_node, 0); |
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if (fifo->irq <= 0) { |
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dev_err(dev, "failed to get irq: %d\n", fifo->irq); |
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return fifo->irq; |
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} |
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fifo->field_threshold = |
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devm_regmap_field_alloc(dev, fifo->map, data->field_threshold); |
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if (IS_ERR(fifo->field_threshold)) |
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return PTR_ERR(fifo->field_threshold); |
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ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth", |
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&fifo->depth); |
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if (ret) { |
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/* Error out for anything but a missing property */ |
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if (ret != -EINVAL) |
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return ret; |
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/* |
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* If the property is missing, it might be because of an old |
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* DT. In such case, assume the smallest known fifo depth |
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*/ |
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fifo->depth = 256; |
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dev_warn(dev, "fifo depth not found, assume %u bytes\n", |
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fifo->depth); |
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} |
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return devm_snd_soc_register_component(dev, data->component_drv, |
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data->dai_drv, 1); |
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} |
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EXPORT_SYMBOL_GPL(axg_fifo_probe); |
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MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver"); |
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MODULE_AUTHOR("Jerome Brunet <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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