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1063 lines
28 KiB
1063 lines
28 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* wm8580.c -- WM8580 and WM8581 ALSA Soc Audio driver |
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* |
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* Copyright 2008-12 Wolfson Microelectronics PLC. |
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* |
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* Notes: |
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* The WM8580 is a multichannel codec with S/PDIF support, featuring six |
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* DAC channels and two ADC channels. |
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* |
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* The WM8581 is a multichannel codec with S/PDIF support, featuring eight |
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* DAC channels and two ADC channels. |
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* |
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* Currently only the primary audio interface is supported - S/PDIF and |
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* the secondary audio interfaces are not. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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#include <linux/pm.h> |
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#include <linux/i2c.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/slab.h> |
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#include <linux/of_device.h> |
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|
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#include <sound/core.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/soc.h> |
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#include <sound/tlv.h> |
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#include <sound/initval.h> |
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#include <asm/div64.h> |
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|
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#include "wm8580.h" |
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|
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/* WM8580 register space */ |
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#define WM8580_PLLA1 0x00 |
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#define WM8580_PLLA2 0x01 |
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#define WM8580_PLLA3 0x02 |
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#define WM8580_PLLA4 0x03 |
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#define WM8580_PLLB1 0x04 |
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#define WM8580_PLLB2 0x05 |
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#define WM8580_PLLB3 0x06 |
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#define WM8580_PLLB4 0x07 |
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#define WM8580_CLKSEL 0x08 |
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#define WM8580_PAIF1 0x09 |
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#define WM8580_PAIF2 0x0A |
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#define WM8580_SAIF1 0x0B |
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#define WM8580_PAIF3 0x0C |
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#define WM8580_PAIF4 0x0D |
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#define WM8580_SAIF2 0x0E |
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#define WM8580_DAC_CONTROL1 0x0F |
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#define WM8580_DAC_CONTROL2 0x10 |
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#define WM8580_DAC_CONTROL3 0x11 |
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#define WM8580_DAC_CONTROL4 0x12 |
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#define WM8580_DAC_CONTROL5 0x13 |
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#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14 |
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#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15 |
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#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16 |
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#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17 |
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#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18 |
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#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19 |
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#define WM8581_DIGITAL_ATTENUATION_DACL4 0x1A |
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#define WM8581_DIGITAL_ATTENUATION_DACR4 0x1B |
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#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C |
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#define WM8580_ADC_CONTROL1 0x1D |
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#define WM8580_SPDTXCHAN0 0x1E |
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#define WM8580_SPDTXCHAN1 0x1F |
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#define WM8580_SPDTXCHAN2 0x20 |
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#define WM8580_SPDTXCHAN3 0x21 |
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#define WM8580_SPDTXCHAN4 0x22 |
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#define WM8580_SPDTXCHAN5 0x23 |
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#define WM8580_SPDMODE 0x24 |
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#define WM8580_INTMASK 0x25 |
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#define WM8580_GPO1 0x26 |
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#define WM8580_GPO2 0x27 |
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#define WM8580_GPO3 0x28 |
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#define WM8580_GPO4 0x29 |
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#define WM8580_GPO5 0x2A |
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#define WM8580_INTSTAT 0x2B |
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#define WM8580_SPDRXCHAN1 0x2C |
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#define WM8580_SPDRXCHAN2 0x2D |
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#define WM8580_SPDRXCHAN3 0x2E |
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#define WM8580_SPDRXCHAN4 0x2F |
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#define WM8580_SPDRXCHAN5 0x30 |
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#define WM8580_SPDSTAT 0x31 |
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#define WM8580_PWRDN1 0x32 |
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#define WM8580_PWRDN2 0x33 |
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#define WM8580_READBACK 0x34 |
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#define WM8580_RESET 0x35 |
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|
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#define WM8580_MAX_REGISTER 0x35 |
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|
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#define WM8580_DACOSR 0x40 |
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|
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/* PLLB4 (register 7h) */ |
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#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 |
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#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 |
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#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40 |
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#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60 |
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|
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#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180 |
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#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080 |
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#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100 |
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#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180 |
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|
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/* CLKSEL (register 8h) */ |
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#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03 |
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#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01 |
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#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02 |
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/* AIF control 1 (registers 9h-bh) */ |
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#define WM8580_AIF_RATE_MASK 0x7 |
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#define WM8580_AIF_BCLKSEL_MASK 0x18 |
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|
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#define WM8580_AIF_MS 0x20 |
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#define WM8580_AIF_CLKSRC_MASK 0xc0 |
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#define WM8580_AIF_CLKSRC_PLLA 0x40 |
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#define WM8580_AIF_CLKSRC_PLLB 0x40 |
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#define WM8580_AIF_CLKSRC_MCLK 0xc0 |
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|
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/* AIF control 2 (registers ch-eh) */ |
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#define WM8580_AIF_FMT_MASK 0x03 |
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#define WM8580_AIF_FMT_RIGHTJ 0x00 |
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#define WM8580_AIF_FMT_LEFTJ 0x01 |
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#define WM8580_AIF_FMT_I2S 0x02 |
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#define WM8580_AIF_FMT_DSP 0x03 |
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|
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#define WM8580_AIF_LENGTH_MASK 0x0c |
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#define WM8580_AIF_LENGTH_16 0x00 |
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#define WM8580_AIF_LENGTH_20 0x04 |
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#define WM8580_AIF_LENGTH_24 0x08 |
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#define WM8580_AIF_LENGTH_32 0x0c |
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#define WM8580_AIF_LRP 0x10 |
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#define WM8580_AIF_BCP 0x20 |
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/* Powerdown Register 1 (register 32h) */ |
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#define WM8580_PWRDN1_PWDN 0x001 |
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#define WM8580_PWRDN1_ALLDACPD 0x040 |
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/* Powerdown Register 2 (register 33h) */ |
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#define WM8580_PWRDN2_OSSCPD 0x001 |
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#define WM8580_PWRDN2_PLLAPD 0x002 |
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#define WM8580_PWRDN2_PLLBPD 0x004 |
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#define WM8580_PWRDN2_SPDIFPD 0x008 |
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#define WM8580_PWRDN2_SPDIFTXD 0x010 |
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#define WM8580_PWRDN2_SPDIFRXD 0x020 |
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|
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#define WM8580_DAC_CONTROL5_MUTEALL 0x10 |
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|
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/* |
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* wm8580 register cache |
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* We can't read the WM8580 register space when we |
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* are using 2 wire for device control, so we cache them instead. |
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*/ |
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static const struct reg_default wm8580_reg_defaults[] = { |
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{ 0, 0x0121 }, |
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{ 1, 0x017e }, |
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{ 2, 0x007d }, |
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{ 3, 0x0014 }, |
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{ 4, 0x0121 }, |
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{ 5, 0x017e }, |
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{ 6, 0x007d }, |
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{ 7, 0x0194 }, |
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{ 8, 0x0010 }, |
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{ 9, 0x0002 }, |
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{ 10, 0x0002 }, |
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{ 11, 0x00c2 }, |
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{ 12, 0x0182 }, |
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{ 13, 0x0082 }, |
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{ 14, 0x000a }, |
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{ 15, 0x0024 }, |
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{ 16, 0x0009 }, |
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{ 17, 0x0000 }, |
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{ 18, 0x00ff }, |
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{ 19, 0x0000 }, |
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{ 20, 0x00ff }, |
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{ 21, 0x00ff }, |
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{ 22, 0x00ff }, |
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{ 23, 0x00ff }, |
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{ 24, 0x00ff }, |
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{ 25, 0x00ff }, |
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{ 26, 0x00ff }, |
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{ 27, 0x00ff }, |
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{ 28, 0x01f0 }, |
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{ 29, 0x0040 }, |
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{ 30, 0x0000 }, |
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{ 31, 0x0000 }, |
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{ 32, 0x0000 }, |
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{ 33, 0x0000 }, |
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{ 34, 0x0031 }, |
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{ 35, 0x000b }, |
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{ 36, 0x0039 }, |
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{ 37, 0x0000 }, |
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{ 38, 0x0010 }, |
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{ 39, 0x0032 }, |
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{ 40, 0x0054 }, |
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{ 41, 0x0076 }, |
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{ 42, 0x0098 }, |
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{ 43, 0x0000 }, |
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{ 44, 0x0000 }, |
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{ 45, 0x0000 }, |
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{ 46, 0x0000 }, |
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{ 47, 0x0000 }, |
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{ 48, 0x0000 }, |
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{ 49, 0x0000 }, |
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{ 50, 0x005e }, |
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{ 51, 0x003e }, |
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{ 52, 0x0000 }, |
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}; |
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static bool wm8580_volatile(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case WM8580_RESET: |
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return true; |
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default: |
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return false; |
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} |
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} |
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struct pll_state { |
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unsigned int in; |
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unsigned int out; |
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}; |
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#define WM8580_NUM_SUPPLIES 3 |
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static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { |
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"AVDD", |
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"DVDD", |
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"PVDD", |
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}; |
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struct wm8580_driver_data { |
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int num_dacs; |
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}; |
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|
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/* codec private data */ |
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struct wm8580_priv { |
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struct regmap *regmap; |
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struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; |
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struct pll_state a; |
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struct pll_state b; |
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const struct wm8580_driver_data *drvdata; |
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int sysclk[2]; |
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}; |
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static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); |
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|
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static int wm8580_out_vu(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct soc_mixer_control *mc = |
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(struct soc_mixer_control *)kcontrol->private_value; |
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struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
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struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
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unsigned int reg = mc->reg; |
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unsigned int reg2 = mc->rreg; |
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int ret; |
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/* Clear the register cache VU so we write without VU set */ |
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regcache_cache_only(wm8580->regmap, true); |
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regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000); |
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regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000); |
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regcache_cache_only(wm8580->regmap, false); |
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ret = snd_soc_put_volsw(kcontrol, ucontrol); |
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if (ret < 0) |
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return ret; |
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/* Now write again with the volume update bit set */ |
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snd_soc_component_update_bits(component, reg, 0x100, 0x100); |
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snd_soc_component_update_bits(component, reg2, 0x100, 0x100); |
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return 0; |
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} |
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static const struct snd_kcontrol_new wm8580_snd_controls[] = { |
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SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume", |
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WM8580_DIGITAL_ATTENUATION_DACL1, |
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WM8580_DIGITAL_ATTENUATION_DACR1, |
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0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
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SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume", |
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WM8580_DIGITAL_ATTENUATION_DACL2, |
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WM8580_DIGITAL_ATTENUATION_DACR2, |
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0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
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SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume", |
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WM8580_DIGITAL_ATTENUATION_DACL3, |
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WM8580_DIGITAL_ATTENUATION_DACR3, |
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0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
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SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0), |
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SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0), |
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SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0), |
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SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0), |
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SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0), |
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SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0), |
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|
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SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0), |
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SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1), |
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SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1), |
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SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1), |
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SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1), |
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SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0), |
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}; |
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static const struct snd_kcontrol_new wm8581_snd_controls[] = { |
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SOC_DOUBLE_R_EXT_TLV("DAC4 Playback Volume", |
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WM8581_DIGITAL_ATTENUATION_DACL4, |
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WM8581_DIGITAL_ATTENUATION_DACR4, |
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0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
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SOC_SINGLE("DAC4 Deemphasis Switch", WM8580_DAC_CONTROL3, 3, 1, 0), |
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SOC_DOUBLE("DAC4 Invert Switch", WM8580_DAC_CONTROL4, 8, 7, 1, 0), |
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SOC_SINGLE("DAC4 Switch", WM8580_DAC_CONTROL5, 3, 1, 1), |
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}; |
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static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { |
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SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1), |
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SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1), |
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SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1), |
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SND_SOC_DAPM_OUTPUT("VOUT1L"), |
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SND_SOC_DAPM_OUTPUT("VOUT1R"), |
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SND_SOC_DAPM_OUTPUT("VOUT2L"), |
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SND_SOC_DAPM_OUTPUT("VOUT2R"), |
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SND_SOC_DAPM_OUTPUT("VOUT3L"), |
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SND_SOC_DAPM_OUTPUT("VOUT3R"), |
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SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1), |
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SND_SOC_DAPM_INPUT("AINL"), |
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SND_SOC_DAPM_INPUT("AINR"), |
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}; |
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static const struct snd_soc_dapm_widget wm8581_dapm_widgets[] = { |
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SND_SOC_DAPM_DAC("DAC4", "Playback", WM8580_PWRDN1, 5, 1), |
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SND_SOC_DAPM_OUTPUT("VOUT4L"), |
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SND_SOC_DAPM_OUTPUT("VOUT4R"), |
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}; |
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static const struct snd_soc_dapm_route wm8580_dapm_routes[] = { |
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{ "VOUT1L", NULL, "DAC1" }, |
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{ "VOUT1R", NULL, "DAC1" }, |
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|
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{ "VOUT2L", NULL, "DAC2" }, |
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{ "VOUT2R", NULL, "DAC2" }, |
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|
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{ "VOUT3L", NULL, "DAC3" }, |
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{ "VOUT3R", NULL, "DAC3" }, |
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|
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{ "ADC", NULL, "AINL" }, |
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{ "ADC", NULL, "AINR" }, |
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}; |
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static const struct snd_soc_dapm_route wm8581_dapm_routes[] = { |
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{ "VOUT4L", NULL, "DAC4" }, |
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{ "VOUT4R", NULL, "DAC4" }, |
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}; |
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|
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/* PLL divisors */ |
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struct _pll_div { |
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u32 prescale:1; |
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u32 postscale:1; |
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u32 freqmode:2; |
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u32 n:4; |
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u32 k:24; |
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}; |
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|
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/* The size in bits of the pll divide */ |
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#define FIXED_PLL_SIZE (1 << 22) |
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|
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/* PLL rate to output rate divisions */ |
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static struct { |
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unsigned int div; |
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unsigned int freqmode; |
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unsigned int postscale; |
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} post_table[] = { |
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{ 2, 0, 0 }, |
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{ 4, 0, 1 }, |
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{ 4, 1, 0 }, |
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{ 8, 1, 1 }, |
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{ 8, 2, 0 }, |
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{ 16, 2, 1 }, |
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{ 12, 3, 0 }, |
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{ 24, 3, 1 } |
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}; |
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|
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static int pll_factors(struct _pll_div *pll_div, unsigned int target, |
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unsigned int source) |
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{ |
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u64 Kpart; |
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unsigned int K, Ndiv, Nmod; |
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int i; |
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|
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pr_debug("wm8580: PLL %uHz->%uHz\n", source, target); |
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|
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/* Scale the output frequency up; the PLL should run in the |
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* region of 90-100MHz. |
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*/ |
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for (i = 0; i < ARRAY_SIZE(post_table); i++) { |
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if (target * post_table[i].div >= 90000000 && |
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target * post_table[i].div <= 100000000) { |
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pll_div->freqmode = post_table[i].freqmode; |
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pll_div->postscale = post_table[i].postscale; |
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target *= post_table[i].div; |
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break; |
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} |
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} |
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|
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if (i == ARRAY_SIZE(post_table)) { |
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printk(KERN_ERR "wm8580: Unable to scale output frequency " |
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"%u\n", target); |
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return -EINVAL; |
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} |
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|
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Ndiv = target / source; |
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|
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if (Ndiv < 5) { |
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source /= 2; |
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pll_div->prescale = 1; |
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Ndiv = target / source; |
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} else |
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pll_div->prescale = 0; |
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|
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if ((Ndiv < 5) || (Ndiv > 13)) { |
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printk(KERN_ERR |
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"WM8580 N=%u outside supported range\n", Ndiv); |
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return -EINVAL; |
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} |
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|
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pll_div->n = Ndiv; |
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Nmod = target % source; |
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Kpart = FIXED_PLL_SIZE * (long long)Nmod; |
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|
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do_div(Kpart, source); |
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|
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K = Kpart & 0xFFFFFFFF; |
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|
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pll_div->k = K; |
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|
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pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n", |
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pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, |
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pll_div->postscale); |
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|
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return 0; |
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} |
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|
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static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
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int source, unsigned int freq_in, unsigned int freq_out) |
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{ |
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int offset; |
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struct snd_soc_component *component = codec_dai->component; |
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struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
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struct pll_state *state; |
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struct _pll_div pll_div; |
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unsigned int reg; |
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unsigned int pwr_mask; |
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int ret; |
|
|
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/* GCC isn't able to work out the ifs below for initialising/using |
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* pll_div so suppress warnings. |
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*/ |
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memset(&pll_div, 0, sizeof(pll_div)); |
|
|
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switch (pll_id) { |
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case WM8580_PLLA: |
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state = &wm8580->a; |
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offset = 0; |
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pwr_mask = WM8580_PWRDN2_PLLAPD; |
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break; |
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case WM8580_PLLB: |
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state = &wm8580->b; |
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offset = 4; |
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pwr_mask = WM8580_PWRDN2_PLLBPD; |
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break; |
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default: |
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return -ENODEV; |
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} |
|
|
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if (freq_in && freq_out) { |
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ret = pll_factors(&pll_div, freq_out, freq_in); |
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if (ret != 0) |
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return ret; |
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} |
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|
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state->in = freq_in; |
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state->out = freq_out; |
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|
|
/* Always disable the PLL - it is not safe to leave it running |
|
* while reprogramming it. |
|
*/ |
|
snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, pwr_mask); |
|
|
|
if (!freq_in || !freq_out) |
|
return 0; |
|
|
|
snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); |
|
snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff); |
|
snd_soc_component_write(component, WM8580_PLLA3 + offset, |
|
(pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); |
|
|
|
reg = snd_soc_component_read(component, WM8580_PLLA4 + offset); |
|
reg &= ~0x1b; |
|
reg |= pll_div.prescale | pll_div.postscale << 1 | |
|
pll_div.freqmode << 3; |
|
|
|
snd_soc_component_write(component, WM8580_PLLA4 + offset, reg); |
|
|
|
/* All done, turn it on */ |
|
snd_soc_component_update_bits(component, WM8580_PWRDN2, pwr_mask, 0); |
|
|
|
return 0; |
|
} |
|
|
|
static const int wm8580_sysclk_ratios[] = { |
|
128, 192, 256, 384, 512, 768, 1152, |
|
}; |
|
|
|
/* |
|
* Set PCM DAI bit size and sample rate. |
|
*/ |
|
static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, |
|
struct snd_pcm_hw_params *params, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
|
u16 paifa = 0; |
|
u16 paifb = 0; |
|
int i, ratio, osr; |
|
|
|
/* bit size */ |
|
switch (params_width(params)) { |
|
case 16: |
|
paifa |= 0x8; |
|
break; |
|
case 20: |
|
paifa |= 0x0; |
|
paifb |= WM8580_AIF_LENGTH_20; |
|
break; |
|
case 24: |
|
paifa |= 0x0; |
|
paifb |= WM8580_AIF_LENGTH_24; |
|
break; |
|
case 32: |
|
paifa |= 0x0; |
|
paifb |= WM8580_AIF_LENGTH_32; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
/* Look up the SYSCLK ratio; accept only exact matches */ |
|
ratio = wm8580->sysclk[dai->driver->id] / params_rate(params); |
|
for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++) |
|
if (ratio == wm8580_sysclk_ratios[i]) |
|
break; |
|
if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) { |
|
dev_err(component->dev, "Invalid clock ratio %d/%d\n", |
|
wm8580->sysclk[dai->driver->id], params_rate(params)); |
|
return -EINVAL; |
|
} |
|
paifa |= i; |
|
dev_dbg(component->dev, "Running at %dfs with %dHz clock\n", |
|
wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); |
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
|
switch (ratio) { |
|
case 128: |
|
case 192: |
|
osr = WM8580_DACOSR; |
|
dev_dbg(component->dev, "Selecting 64x OSR\n"); |
|
break; |
|
default: |
|
osr = 0; |
|
dev_dbg(component->dev, "Selecting 128x OSR\n"); |
|
break; |
|
} |
|
|
|
snd_soc_component_update_bits(component, WM8580_PAIF3, WM8580_DACOSR, osr); |
|
} |
|
|
|
snd_soc_component_update_bits(component, WM8580_PAIF1 + dai->driver->id, |
|
WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, |
|
paifa); |
|
snd_soc_component_update_bits(component, WM8580_PAIF3 + dai->driver->id, |
|
WM8580_AIF_LENGTH_MASK, paifb); |
|
return 0; |
|
} |
|
|
|
static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai, |
|
unsigned int fmt) |
|
{ |
|
struct snd_soc_component *component = codec_dai->component; |
|
unsigned int aifa; |
|
unsigned int aifb; |
|
int can_invert_lrclk; |
|
|
|
aifa = snd_soc_component_read(component, WM8580_PAIF1 + codec_dai->driver->id); |
|
aifb = snd_soc_component_read(component, WM8580_PAIF3 + codec_dai->driver->id); |
|
|
|
aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP); |
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
|
case SND_SOC_DAIFMT_CBS_CFS: |
|
aifa &= ~WM8580_AIF_MS; |
|
break; |
|
case SND_SOC_DAIFMT_CBM_CFM: |
|
aifa |= WM8580_AIF_MS; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
|
case SND_SOC_DAIFMT_I2S: |
|
can_invert_lrclk = 1; |
|
aifb |= WM8580_AIF_FMT_I2S; |
|
break; |
|
case SND_SOC_DAIFMT_RIGHT_J: |
|
can_invert_lrclk = 1; |
|
aifb |= WM8580_AIF_FMT_RIGHTJ; |
|
break; |
|
case SND_SOC_DAIFMT_LEFT_J: |
|
can_invert_lrclk = 1; |
|
aifb |= WM8580_AIF_FMT_LEFTJ; |
|
break; |
|
case SND_SOC_DAIFMT_DSP_A: |
|
can_invert_lrclk = 0; |
|
aifb |= WM8580_AIF_FMT_DSP; |
|
break; |
|
case SND_SOC_DAIFMT_DSP_B: |
|
can_invert_lrclk = 0; |
|
aifb |= WM8580_AIF_FMT_DSP; |
|
aifb |= WM8580_AIF_LRP; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
|
case SND_SOC_DAIFMT_NB_NF: |
|
break; |
|
|
|
case SND_SOC_DAIFMT_IB_IF: |
|
if (!can_invert_lrclk) |
|
return -EINVAL; |
|
aifb |= WM8580_AIF_BCP; |
|
aifb |= WM8580_AIF_LRP; |
|
break; |
|
|
|
case SND_SOC_DAIFMT_IB_NF: |
|
aifb |= WM8580_AIF_BCP; |
|
break; |
|
|
|
case SND_SOC_DAIFMT_NB_IF: |
|
if (!can_invert_lrclk) |
|
return -EINVAL; |
|
aifb |= WM8580_AIF_LRP; |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
snd_soc_component_write(component, WM8580_PAIF1 + codec_dai->driver->id, aifa); |
|
snd_soc_component_write(component, WM8580_PAIF3 + codec_dai->driver->id, aifb); |
|
|
|
return 0; |
|
} |
|
|
|
static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
|
int div_id, int div) |
|
{ |
|
struct snd_soc_component *component = codec_dai->component; |
|
unsigned int reg; |
|
|
|
switch (div_id) { |
|
case WM8580_MCLK: |
|
reg = snd_soc_component_read(component, WM8580_PLLB4); |
|
reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK; |
|
|
|
switch (div) { |
|
case WM8580_CLKSRC_MCLK: |
|
/* Input */ |
|
break; |
|
|
|
case WM8580_CLKSRC_PLLA: |
|
reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA; |
|
break; |
|
case WM8580_CLKSRC_PLLB: |
|
reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB; |
|
break; |
|
|
|
case WM8580_CLKSRC_OSC: |
|
reg |= WM8580_PLLB4_MCLKOUTSRC_OSC; |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
snd_soc_component_write(component, WM8580_PLLB4, reg); |
|
break; |
|
|
|
case WM8580_CLKOUTSRC: |
|
reg = snd_soc_component_read(component, WM8580_PLLB4); |
|
reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; |
|
|
|
switch (div) { |
|
case WM8580_CLKSRC_NONE: |
|
break; |
|
|
|
case WM8580_CLKSRC_PLLA: |
|
reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK; |
|
break; |
|
|
|
case WM8580_CLKSRC_PLLB: |
|
reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK; |
|
break; |
|
|
|
case WM8580_CLKSRC_OSC: |
|
reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK; |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
snd_soc_component_write(component, WM8580_PLLB4, reg); |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
|
unsigned int freq, int dir) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
|
int ret, sel, sel_mask, sel_shift; |
|
|
|
switch (dai->driver->id) { |
|
case WM8580_DAI_PAIFRX: |
|
sel_mask = 0x3; |
|
sel_shift = 0; |
|
break; |
|
|
|
case WM8580_DAI_PAIFTX: |
|
sel_mask = 0xc; |
|
sel_shift = 2; |
|
break; |
|
|
|
default: |
|
WARN(1, "Unknown DAI driver ID\n"); |
|
return -EINVAL; |
|
} |
|
|
|
switch (clk_id) { |
|
case WM8580_CLKSRC_ADCMCLK: |
|
if (dai->driver->id != WM8580_DAI_PAIFTX) |
|
return -EINVAL; |
|
sel = 0 << sel_shift; |
|
break; |
|
case WM8580_CLKSRC_PLLA: |
|
sel = 1 << sel_shift; |
|
break; |
|
case WM8580_CLKSRC_PLLB: |
|
sel = 2 << sel_shift; |
|
break; |
|
case WM8580_CLKSRC_MCLK: |
|
sel = 3 << sel_shift; |
|
break; |
|
default: |
|
dev_err(component->dev, "Unknown clock %d\n", clk_id); |
|
return -EINVAL; |
|
} |
|
|
|
/* We really should validate PLL settings but not yet */ |
|
wm8580->sysclk[dai->driver->id] = freq; |
|
|
|
ret = snd_soc_component_update_bits(component, WM8580_CLKSEL, sel_mask, sel); |
|
if (ret < 0) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int wm8580_mute(struct snd_soc_dai *codec_dai, int mute, int direction) |
|
{ |
|
struct snd_soc_component *component = codec_dai->component; |
|
unsigned int reg; |
|
|
|
reg = snd_soc_component_read(component, WM8580_DAC_CONTROL5); |
|
|
|
if (mute) |
|
reg |= WM8580_DAC_CONTROL5_MUTEALL; |
|
else |
|
reg &= ~WM8580_DAC_CONTROL5_MUTEALL; |
|
|
|
snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg); |
|
|
|
return 0; |
|
} |
|
|
|
static int wm8580_set_bias_level(struct snd_soc_component *component, |
|
enum snd_soc_bias_level level) |
|
{ |
|
switch (level) { |
|
case SND_SOC_BIAS_ON: |
|
case SND_SOC_BIAS_PREPARE: |
|
break; |
|
|
|
case SND_SOC_BIAS_STANDBY: |
|
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
|
/* Power up and get individual control of the DACs */ |
|
snd_soc_component_update_bits(component, WM8580_PWRDN1, |
|
WM8580_PWRDN1_PWDN | |
|
WM8580_PWRDN1_ALLDACPD, 0); |
|
|
|
/* Make VMID high impedance */ |
|
snd_soc_component_update_bits(component, WM8580_ADC_CONTROL1, |
|
0x100, 0); |
|
} |
|
break; |
|
|
|
case SND_SOC_BIAS_OFF: |
|
snd_soc_component_update_bits(component, WM8580_PWRDN1, |
|
WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN); |
|
break; |
|
} |
|
return 0; |
|
} |
|
|
|
static int wm8580_playback_startup(struct snd_pcm_substream *substream, |
|
struct snd_soc_dai *dai) |
|
{ |
|
struct snd_soc_component *component = dai->component; |
|
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
|
|
|
return snd_pcm_hw_constraint_minmax(substream->runtime, |
|
SNDRV_PCM_HW_PARAM_CHANNELS, 1, wm8580->drvdata->num_dacs * 2); |
|
} |
|
|
|
#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
|
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
|
|
|
static const struct snd_soc_dai_ops wm8580_dai_ops_playback = { |
|
.startup = wm8580_playback_startup, |
|
.set_sysclk = wm8580_set_sysclk, |
|
.hw_params = wm8580_paif_hw_params, |
|
.set_fmt = wm8580_set_paif_dai_fmt, |
|
.set_clkdiv = wm8580_set_dai_clkdiv, |
|
.set_pll = wm8580_set_dai_pll, |
|
.mute_stream = wm8580_mute, |
|
.no_capture_mute = 1, |
|
}; |
|
|
|
static const struct snd_soc_dai_ops wm8580_dai_ops_capture = { |
|
.set_sysclk = wm8580_set_sysclk, |
|
.hw_params = wm8580_paif_hw_params, |
|
.set_fmt = wm8580_set_paif_dai_fmt, |
|
.set_clkdiv = wm8580_set_dai_clkdiv, |
|
.set_pll = wm8580_set_dai_pll, |
|
}; |
|
|
|
static struct snd_soc_dai_driver wm8580_dai[] = { |
|
{ |
|
.name = "wm8580-hifi-playback", |
|
.id = WM8580_DAI_PAIFRX, |
|
.playback = { |
|
.stream_name = "Playback", |
|
.channels_min = 1, |
|
.rates = SNDRV_PCM_RATE_8000_192000, |
|
.formats = WM8580_FORMATS, |
|
}, |
|
.ops = &wm8580_dai_ops_playback, |
|
}, |
|
{ |
|
.name = "wm8580-hifi-capture", |
|
.id = WM8580_DAI_PAIFTX, |
|
.capture = { |
|
.stream_name = "Capture", |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.rates = SNDRV_PCM_RATE_8000_192000, |
|
.formats = WM8580_FORMATS, |
|
}, |
|
.ops = &wm8580_dai_ops_capture, |
|
}, |
|
}; |
|
|
|
static int wm8580_probe(struct snd_soc_component *component) |
|
{ |
|
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
|
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
|
int ret = 0; |
|
|
|
switch (wm8580->drvdata->num_dacs) { |
|
case 4: |
|
snd_soc_add_component_controls(component, wm8581_snd_controls, |
|
ARRAY_SIZE(wm8581_snd_controls)); |
|
snd_soc_dapm_new_controls(dapm, wm8581_dapm_widgets, |
|
ARRAY_SIZE(wm8581_dapm_widgets)); |
|
snd_soc_dapm_add_routes(dapm, wm8581_dapm_routes, |
|
ARRAY_SIZE(wm8581_dapm_routes)); |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies), |
|
wm8580->supplies); |
|
if (ret != 0) { |
|
dev_err(component->dev, "Failed to enable supplies: %d\n", ret); |
|
goto err_regulator_get; |
|
} |
|
|
|
/* Get the codec into a known state */ |
|
ret = snd_soc_component_write(component, WM8580_RESET, 0); |
|
if (ret != 0) { |
|
dev_err(component->dev, "Failed to reset component: %d\n", ret); |
|
goto err_regulator_enable; |
|
} |
|
|
|
return 0; |
|
|
|
err_regulator_enable: |
|
regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); |
|
err_regulator_get: |
|
return ret; |
|
} |
|
|
|
/* power down chip */ |
|
static void wm8580_remove(struct snd_soc_component *component) |
|
{ |
|
struct wm8580_priv *wm8580 = snd_soc_component_get_drvdata(component); |
|
|
|
regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); |
|
} |
|
|
|
static const struct snd_soc_component_driver soc_component_dev_wm8580 = { |
|
.probe = wm8580_probe, |
|
.remove = wm8580_remove, |
|
.set_bias_level = wm8580_set_bias_level, |
|
.controls = wm8580_snd_controls, |
|
.num_controls = ARRAY_SIZE(wm8580_snd_controls), |
|
.dapm_widgets = wm8580_dapm_widgets, |
|
.num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets), |
|
.dapm_routes = wm8580_dapm_routes, |
|
.num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes), |
|
.idle_bias_on = 1, |
|
.use_pmdown_time = 1, |
|
.endianness = 1, |
|
.non_legacy_dai_naming = 1, |
|
}; |
|
|
|
static const struct regmap_config wm8580_regmap = { |
|
.reg_bits = 7, |
|
.val_bits = 9, |
|
.max_register = WM8580_MAX_REGISTER, |
|
|
|
.reg_defaults = wm8580_reg_defaults, |
|
.num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults), |
|
.cache_type = REGCACHE_RBTREE, |
|
|
|
.volatile_reg = wm8580_volatile, |
|
}; |
|
|
|
static const struct wm8580_driver_data wm8580_data = { |
|
.num_dacs = 3, |
|
}; |
|
|
|
static const struct wm8580_driver_data wm8581_data = { |
|
.num_dacs = 4, |
|
}; |
|
|
|
static const struct of_device_id wm8580_of_match[] = { |
|
{ .compatible = "wlf,wm8580", .data = &wm8580_data }, |
|
{ .compatible = "wlf,wm8581", .data = &wm8581_data }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, wm8580_of_match); |
|
|
|
static int wm8580_i2c_probe(struct i2c_client *i2c, |
|
const struct i2c_device_id *id) |
|
{ |
|
const struct of_device_id *of_id; |
|
struct wm8580_priv *wm8580; |
|
int ret, i; |
|
|
|
wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv), |
|
GFP_KERNEL); |
|
if (wm8580 == NULL) |
|
return -ENOMEM; |
|
|
|
wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap); |
|
if (IS_ERR(wm8580->regmap)) |
|
return PTR_ERR(wm8580->regmap); |
|
|
|
for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++) |
|
wm8580->supplies[i].supply = wm8580_supply_names[i]; |
|
|
|
ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies), |
|
wm8580->supplies); |
|
if (ret != 0) { |
|
dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
i2c_set_clientdata(i2c, wm8580); |
|
|
|
of_id = of_match_device(wm8580_of_match, &i2c->dev); |
|
if (of_id) |
|
wm8580->drvdata = of_id->data; |
|
|
|
if (!wm8580->drvdata) { |
|
dev_err(&i2c->dev, "failed to find driver data\n"); |
|
return -EINVAL; |
|
} |
|
|
|
ret = devm_snd_soc_register_component(&i2c->dev, |
|
&soc_component_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai)); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct i2c_device_id wm8580_i2c_id[] = { |
|
{ "wm8580", (kernel_ulong_t)&wm8580_data }, |
|
{ "wm8581", (kernel_ulong_t)&wm8581_data }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id); |
|
|
|
static struct i2c_driver wm8580_i2c_driver = { |
|
.driver = { |
|
.name = "wm8580", |
|
.of_match_table = wm8580_of_match, |
|
}, |
|
.probe = wm8580_i2c_probe, |
|
.id_table = wm8580_i2c_id, |
|
}; |
|
|
|
module_i2c_driver(wm8580_i2c_driver); |
|
|
|
MODULE_DESCRIPTION("ASoC WM8580 driver"); |
|
MODULE_AUTHOR("Mark Brown <[email protected]>"); |
|
MODULE_AUTHOR("Matt Flax <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|