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585 lines
14 KiB
585 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* rt715-sdw.c -- rt715 ALSA SoC audio driver |
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* |
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* Copyright(c) 2019 Realtek Semiconductor Corp. |
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* |
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* ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver |
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* |
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*/ |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/soundwire/sdw.h> |
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#include <linux/soundwire/sdw_type.h> |
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#include <linux/soundwire/sdw_registers.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include <sound/soc.h> |
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#include "rt715.h" |
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#include "rt715-sdw.h" |
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|
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static bool rt715_readable_register(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case 0x00e0 ... 0x00e5: |
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case 0x00ee ... 0x00ef: |
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case 0x00f0 ... 0x00f5: |
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case 0x00fe ... 0x00ff: |
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case 0x02e0: |
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case 0x02f0: |
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case 0x04e0: |
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case 0x04f0: |
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case 0x06e0: |
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case 0x06f0: |
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case 0x2000 ... 0x2016: |
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case 0x201a ... 0x2027: |
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case 0x2029 ... 0x202a: |
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case 0x202d ... 0x2034: |
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case 0x2200 ... 0x2204: |
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case 0x2206 ... 0x2212: |
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case 0x2220 ... 0x2223: |
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case 0x2230 ... 0x2239: |
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case 0x22f0 ... 0x22f3: |
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case 0x3122: |
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case 0x3123: |
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case 0x3124: |
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case 0x3125: |
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case 0x3607: |
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case 0x3608: |
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case 0x3609: |
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case 0x3610: |
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case 0x3611: |
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case 0x3627: |
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case 0x3712: |
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case 0x3713: |
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case 0x3718: |
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case 0x3719: |
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case 0x371a: |
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case 0x371b: |
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case 0x371d: |
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case 0x3729: |
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case 0x385e: |
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case 0x3859: |
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case 0x4c12: |
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case 0x4c13: |
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case 0x4c1d: |
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case 0x4c29: |
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case 0x4d12: |
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case 0x4d13: |
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case 0x4d1d: |
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case 0x4d29: |
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case 0x4e12: |
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case 0x4e13: |
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case 0x4e1d: |
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case 0x4e29: |
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case 0x4f12: |
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case 0x4f13: |
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case 0x4f1d: |
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case 0x4f29: |
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case 0x7207: |
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case 0x7208: |
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case 0x7209: |
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case 0x7227: |
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case 0x7307: |
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case 0x7308: |
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case 0x7309: |
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case 0x7312: |
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case 0x7313: |
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case 0x7318: |
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case 0x7319: |
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case 0x731a: |
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case 0x731b: |
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case 0x731d: |
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case 0x7327: |
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case 0x7329: |
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case 0x8287: |
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case 0x8288: |
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case 0x8289: |
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case 0x82a7: |
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case 0x8387: |
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case 0x8388: |
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case 0x8389: |
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case 0x8392: |
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case 0x8393: |
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case 0x8398: |
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case 0x8399: |
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case 0x839a: |
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case 0x839b: |
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case 0x839d: |
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case 0x83a7: |
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case 0x83a9: |
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case 0x752039: |
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return true; |
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default: |
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return false; |
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} |
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} |
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static bool rt715_volatile_register(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case 0x00e5: |
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case 0x00f0: |
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case 0x00f3: |
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case 0x00f5: |
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case 0x2009: |
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case 0x2016: |
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case 0x201b: |
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case 0x201c: |
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case 0x201d: |
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case 0x201f: |
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case 0x2023: |
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case 0x2230: |
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case 0x200b ... 0x200e: /* i2c read */ |
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case 0x2012 ... 0x2015: /* HD-A read */ |
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case 0x202d ... 0x202f: /* BRA */ |
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case 0x2201 ... 0x2212: /* i2c debug */ |
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case 0x2220 ... 0x2223: /* decoded HD-A */ |
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return true; |
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default: |
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return false; |
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} |
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} |
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static int rt715_sdw_read(void *context, unsigned int reg, unsigned int *val) |
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{ |
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struct device *dev = context; |
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struct rt715_priv *rt715 = dev_get_drvdata(dev); |
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unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0; |
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unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; |
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unsigned int is_hda_reg = 1, is_index_reg = 0; |
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int ret; |
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if (reg > 0xffff) |
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is_index_reg = 1; |
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mask = reg & 0xf000; |
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if (is_index_reg) { /* index registers */ |
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val2 = reg & 0xff; |
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reg = reg >> 8; |
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nid = reg & 0xff; |
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ret = regmap_write(rt715->sdw_regmap, reg, 0); |
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if (ret < 0) |
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return ret; |
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reg2 = reg + 0x1000; |
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reg2 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, val2); |
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if (ret < 0) |
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return ret; |
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reg3 = RT715_PRIV_DATA_R_H | nid; |
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ret = regmap_write(rt715->sdw_regmap, reg3, |
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((*val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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reg4 = reg3 + 0x1000; |
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reg4 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg4, (*val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} else if (mask == 0x3000) { |
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reg += 0x8000; |
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ret = regmap_write(rt715->sdw_regmap, reg, *val); |
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if (ret < 0) |
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return ret; |
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} else if (mask == 0x7000) { |
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reg += 0x2000; |
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reg |= 0x800; |
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ret = regmap_write(rt715->sdw_regmap, reg, |
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((*val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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reg2 = reg + 0x1000; |
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reg2 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} else if ((reg & 0xff00) == 0x8300) { /* for R channel */ |
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reg2 = reg - 0x1000; |
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reg2 &= ~0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, |
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((*val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(rt715->sdw_regmap, reg, (*val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} else if (mask == 0x9000) { |
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ret = regmap_write(rt715->sdw_regmap, reg, |
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((*val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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reg2 = reg + 0x1000; |
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reg2 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} else if (mask == 0xb000) { |
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ret = regmap_write(rt715->sdw_regmap, reg, *val); |
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if (ret < 0) |
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return ret; |
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} else { |
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ret = regmap_read(rt715->sdw_regmap, reg, val); |
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if (ret < 0) |
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return ret; |
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is_hda_reg = 0; |
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} |
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if (is_hda_reg || is_index_reg) { |
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sdw_data_3 = 0; |
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sdw_data_2 = 0; |
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sdw_data_1 = 0; |
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sdw_data_0 = 0; |
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ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_3, |
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&sdw_data_3); |
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if (ret < 0) |
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return ret; |
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ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_2, |
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&sdw_data_2); |
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if (ret < 0) |
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return ret; |
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ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_1, |
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&sdw_data_1); |
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if (ret < 0) |
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return ret; |
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ret = regmap_read(rt715->sdw_regmap, RT715_READ_HDA_0, |
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&sdw_data_0); |
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if (ret < 0) |
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return ret; |
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*val = ((sdw_data_3 & 0xff) << 24) | |
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((sdw_data_2 & 0xff) << 16) | |
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((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff); |
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} |
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if (is_hda_reg == 0) |
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dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val); |
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else if (is_index_reg) |
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dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n", __func__, |
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reg, reg2, reg3, reg4, *val); |
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else |
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dev_dbg(dev, "[%s] %04x %04x => %08x\n", |
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__func__, reg, reg2, *val); |
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return 0; |
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} |
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static int rt715_sdw_write(void *context, unsigned int reg, unsigned int val) |
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{ |
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struct device *dev = context; |
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struct rt715_priv *rt715 = dev_get_drvdata(dev); |
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unsigned int reg2 = 0, reg3, reg4, nid, mask, val2; |
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unsigned int is_index_reg = 0; |
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int ret; |
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if (reg > 0xffff) |
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is_index_reg = 1; |
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mask = reg & 0xf000; |
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if (is_index_reg) { /* index registers */ |
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val2 = reg & 0xff; |
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reg = reg >> 8; |
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nid = reg & 0xff; |
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ret = regmap_write(rt715->sdw_regmap, reg, 0); |
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if (ret < 0) |
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return ret; |
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reg2 = reg + 0x1000; |
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reg2 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, val2); |
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if (ret < 0) |
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return ret; |
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reg3 = RT715_PRIV_DATA_W_H | nid; |
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ret = regmap_write(rt715->sdw_regmap, reg3, |
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((val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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reg4 = reg3 + 0x1000; |
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reg4 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg4, (val & 0xff)); |
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if (ret < 0) |
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return ret; |
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is_index_reg = 1; |
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} else if (reg < 0x4fff) { |
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ret = regmap_write(rt715->sdw_regmap, reg, val); |
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if (ret < 0) |
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return ret; |
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} else if (reg == RT715_FUNC_RESET) { |
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ret = regmap_write(rt715->sdw_regmap, reg, val); |
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if (ret < 0) |
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return ret; |
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} else if (mask == 0x7000) { |
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ret = regmap_write(rt715->sdw_regmap, reg, |
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((val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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reg2 = reg + 0x1000; |
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reg2 |= 0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, (val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} else if ((reg & 0xff00) == 0x8300) { /* for R channel */ |
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reg2 = reg - 0x1000; |
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reg2 &= ~0x80; |
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ret = regmap_write(rt715->sdw_regmap, reg2, |
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((val >> 8) & 0xff)); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(rt715->sdw_regmap, reg, (val & 0xff)); |
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if (ret < 0) |
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return ret; |
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} |
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if (reg2 == 0) |
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dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val); |
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else if (is_index_reg) |
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dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n", |
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__func__, reg, reg2, reg3, reg4, val2, val); |
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else |
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dev_dbg(dev, "[%s] %04x %04x <= %04x\n", |
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__func__, reg, reg2, val); |
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return 0; |
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} |
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static const struct regmap_config rt715_regmap = { |
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.reg_bits = 24, |
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.val_bits = 32, |
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.readable_reg = rt715_readable_register, /* Readable registers */ |
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.volatile_reg = rt715_volatile_register, /* volatile register */ |
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.max_register = 0x752039, /* Maximum number of register */ |
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.reg_defaults = rt715_reg_defaults, /* Defaults */ |
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.num_reg_defaults = ARRAY_SIZE(rt715_reg_defaults), |
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.cache_type = REGCACHE_RBTREE, |
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.use_single_read = true, |
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.use_single_write = true, |
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.reg_read = rt715_sdw_read, |
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.reg_write = rt715_sdw_write, |
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}; |
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static const struct regmap_config rt715_sdw_regmap = { |
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.name = "sdw", |
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.reg_bits = 32, /* Total register space for SDW */ |
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.val_bits = 8, /* Total number of bits in register */ |
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.max_register = 0xff01, /* Maximum number of register */ |
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.cache_type = REGCACHE_NONE, |
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.use_single_read = true, |
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.use_single_write = true, |
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}; |
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int hda_to_sdw(unsigned int nid, unsigned int verb, unsigned int payload, |
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unsigned int *sdw_addr_h, unsigned int *sdw_data_h, |
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unsigned int *sdw_addr_l, unsigned int *sdw_data_l) |
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{ |
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unsigned int offset_h, offset_l, e_verb; |
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if (((verb & 0xff) != 0) || verb == 0xf00) { /* 12 bits command */ |
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if (verb == 0x7ff) /* special case */ |
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offset_h = 0; |
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else |
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offset_h = 0x3000; |
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if (verb & 0x800) /* get command */ |
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e_verb = (verb - 0xf00) | 0x80; |
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else /* set command */ |
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e_verb = (verb - 0x700); |
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*sdw_data_h = payload; /* 7 bits payload */ |
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*sdw_addr_l = *sdw_data_l = 0; |
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} else { /* 4 bits command */ |
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if ((verb & 0x800) == 0x800) { /* read */ |
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offset_h = 0x9000; |
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offset_l = 0xa000; |
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} else { /* write */ |
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offset_h = 0x7000; |
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offset_l = 0x8000; |
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} |
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e_verb = verb >> 8; |
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*sdw_data_h = (payload >> 8); /* 16 bits payload [15:8] */ |
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*sdw_addr_l = (e_verb << 8) | nid | 0x80; /* 0x80: valid bit */ |
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*sdw_addr_l += offset_l; |
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*sdw_data_l = payload & 0xff; |
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} |
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*sdw_addr_h = (e_verb << 8) | nid; |
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*sdw_addr_h += offset_h; |
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return 0; |
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} |
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EXPORT_SYMBOL(hda_to_sdw); |
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static int rt715_update_status(struct sdw_slave *slave, |
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enum sdw_slave_status status) |
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{ |
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struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev); |
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/* Update the status */ |
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rt715->status = status; |
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/* |
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* Perform initialization only if slave status is present and |
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* hw_init flag is false |
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*/ |
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if (rt715->hw_init || rt715->status != SDW_SLAVE_ATTACHED) |
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return 0; |
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/* perform I/O transfers required for Slave initialization */ |
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return rt715_io_init(&slave->dev, slave); |
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} |
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static int rt715_read_prop(struct sdw_slave *slave) |
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{ |
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struct sdw_slave_prop *prop = &slave->prop; |
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int nval, i; |
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u32 bit; |
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unsigned long addr; |
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struct sdw_dpn_prop *dpn; |
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prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH | |
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SDW_SCP_INT1_PARITY; |
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prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; |
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prop->paging_support = false; |
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/* first we need to allocate memory for set bits in port lists */ |
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prop->source_ports = 0x50;/* BITMAP: 01010000 */ |
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prop->sink_ports = 0x0; /* BITMAP: 00000000 */ |
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nval = hweight32(prop->source_ports); |
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prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, |
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sizeof(*prop->src_dpn_prop), |
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GFP_KERNEL); |
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if (!prop->src_dpn_prop) |
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return -ENOMEM; |
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dpn = prop->src_dpn_prop; |
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i = 0; |
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addr = prop->source_ports; |
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for_each_set_bit(bit, &addr, 32) { |
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dpn[i].num = bit; |
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dpn[i].simple_ch_prep_sm = true; |
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dpn[i].ch_prep_timeout = 10; |
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i++; |
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} |
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|
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/* set the timeout values */ |
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prop->clk_stop_timeout = 20; |
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/* wake-up event */ |
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prop->wake_capable = 1; |
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return 0; |
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} |
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static int rt715_bus_config(struct sdw_slave *slave, |
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struct sdw_bus_params *params) |
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{ |
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struct rt715_priv *rt715 = dev_get_drvdata(&slave->dev); |
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int ret; |
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memcpy(&rt715->params, params, sizeof(*params)); |
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ret = rt715_clock_config(&slave->dev); |
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if (ret < 0) |
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dev_err(&slave->dev, "Invalid clk config"); |
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return 0; |
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} |
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static struct sdw_slave_ops rt715_slave_ops = { |
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.read_prop = rt715_read_prop, |
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.update_status = rt715_update_status, |
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.bus_config = rt715_bus_config, |
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}; |
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static int rt715_sdw_probe(struct sdw_slave *slave, |
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const struct sdw_device_id *id) |
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{ |
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struct regmap *sdw_regmap, *regmap; |
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|
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/* Regmap Initialization */ |
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sdw_regmap = devm_regmap_init_sdw(slave, &rt715_sdw_regmap); |
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if (IS_ERR(sdw_regmap)) |
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return PTR_ERR(sdw_regmap); |
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regmap = devm_regmap_init(&slave->dev, NULL, &slave->dev, |
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&rt715_regmap); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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rt715_init(&slave->dev, sdw_regmap, regmap, slave); |
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return 0; |
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} |
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static const struct sdw_device_id rt715_id[] = { |
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SDW_SLAVE_ENTRY_EXT(0x025d, 0x714, 0x2, 0, 0), |
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SDW_SLAVE_ENTRY_EXT(0x025d, 0x715, 0x2, 0, 0), |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(sdw, rt715_id); |
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static int __maybe_unused rt715_dev_suspend(struct device *dev) |
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{ |
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struct rt715_priv *rt715 = dev_get_drvdata(dev); |
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|
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if (!rt715->hw_init) |
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return 0; |
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regcache_cache_only(rt715->regmap, true); |
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return 0; |
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} |
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#define RT715_PROBE_TIMEOUT 5000 |
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static int __maybe_unused rt715_dev_resume(struct device *dev) |
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{ |
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struct sdw_slave *slave = dev_to_sdw_dev(dev); |
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struct rt715_priv *rt715 = dev_get_drvdata(dev); |
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unsigned long time; |
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|
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if (!rt715->hw_init) |
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return 0; |
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|
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if (!slave->unattach_request) |
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goto regmap_sync; |
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|
|
time = wait_for_completion_timeout(&slave->initialization_complete, |
|
msecs_to_jiffies(RT715_PROBE_TIMEOUT)); |
|
if (!time) { |
|
dev_err(&slave->dev, "Initialization not complete, timed out\n"); |
|
return -ETIMEDOUT; |
|
} |
|
|
|
regmap_sync: |
|
slave->unattach_request = 0; |
|
regcache_cache_only(rt715->regmap, false); |
|
regcache_sync_region(rt715->regmap, 0x3000, 0x8fff); |
|
regcache_sync_region(rt715->regmap, 0x752039, 0x752039); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops rt715_pm = { |
|
SET_SYSTEM_SLEEP_PM_OPS(rt715_dev_suspend, rt715_dev_resume) |
|
SET_RUNTIME_PM_OPS(rt715_dev_suspend, rt715_dev_resume, NULL) |
|
}; |
|
|
|
static struct sdw_driver rt715_sdw_driver = { |
|
.driver = { |
|
.name = "rt715", |
|
.owner = THIS_MODULE, |
|
.pm = &rt715_pm, |
|
}, |
|
.probe = rt715_sdw_probe, |
|
.ops = &rt715_slave_ops, |
|
.id_table = rt715_id, |
|
}; |
|
module_sdw_driver(rt715_sdw_driver); |
|
|
|
MODULE_DESCRIPTION("ASoC RT715 driver SDW"); |
|
MODULE_AUTHOR("Jack Yu <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|