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232 lines
6.4 KiB
232 lines
6.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* rt1016.h -- RT1016 ALSA SoC audio amplifier driver |
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* |
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* Copyright 2020 Realtek Semiconductor Corp. |
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* Author: Oder Chiou <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __RT1016_H__ |
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#define __RT1016_H__ |
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#define RT1016_DEVICE_ID_VAL 0x6595 |
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#define RT1016_RESET 0x00 |
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#define RT1016_PADS_CTRL_1 0x01 |
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#define RT1016_PADS_CTRL_2 0x02 |
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#define RT1016_I2C_CTRL 0x03 |
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#define RT1016_VOL_CTRL_1 0x04 |
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#define RT1016_VOL_CTRL_2 0x05 |
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#define RT1016_VOL_CTRL_3 0x06 |
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#define RT1016_ANA_CTRL_1 0x07 |
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#define RT1016_MUX_SEL 0x08 |
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#define RT1016_RX_I2S_CTRL 0x09 |
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#define RT1016_ANA_FLAG 0x0a |
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#define RT1016_VERSION2_ID 0x0c |
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#define RT1016_VERSION1_ID 0x0d |
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#define RT1016_VENDER_ID 0x0e |
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#define RT1016_DEVICE_ID 0x0f |
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#define RT1016_ANA_CTRL_2 0x11 |
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#define RT1016_TEST_SIGNAL 0x1c |
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#define RT1016_TEST_CTRL_1 0x1d |
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#define RT1016_TEST_CTRL_2 0x1e |
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#define RT1016_TEST_CTRL_3 0x1f |
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#define RT1016_CLOCK_1 0x20 |
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#define RT1016_CLOCK_2 0x21 |
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#define RT1016_CLOCK_3 0x22 |
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#define RT1016_CLOCK_4 0x23 |
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#define RT1016_CLOCK_5 0x24 |
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#define RT1016_CLOCK_6 0x25 |
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#define RT1016_CLOCK_7 0x26 |
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#define RT1016_I2S_CTRL 0x40 |
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#define RT1016_DAC_CTRL_1 0x60 |
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#define RT1016_SC_CTRL_1 0x80 |
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#define RT1016_SC_CTRL_2 0x81 |
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#define RT1016_SC_CTRL_3 0x82 |
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#define RT1016_SC_CTRL_4 0x83 |
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#define RT1016_SIL_DET 0xa0 |
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#define RT1016_SYS_CLK 0xc0 |
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#define RT1016_BIAS_CUR 0xc1 |
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#define RT1016_DAC_CTRL_2 0xc2 |
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#define RT1016_LDO_CTRL 0xc3 |
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#define RT1016_CLASSD_1 0xc4 |
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#define RT1016_PLL1 0xc5 |
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#define RT1016_PLL2 0xc6 |
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#define RT1016_PLL3 0xc7 |
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#define RT1016_CLASSD_2 0xc8 |
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#define RT1016_CLASSD_OUT 0xc9 |
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#define RT1016_CLASSD_3 0xca |
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#define RT1016_CLASSD_4 0xcb |
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#define RT1016_CLASSD_5 0xcc |
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#define RT1016_PWR_CTRL 0xcf |
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/* global definition */ |
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#define RT1016_L_VOL_MASK (0xff << 8) |
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#define RT1016_L_VOL_SFT 8 |
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#define RT1016_R_VOL_MASK (0xff) |
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#define RT1016_R_VOL_SFT 0 |
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/* 0x04 */ |
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#define RT1016_DA_MUTE_L_SFT 7 |
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#define RT1016_DA_MUTE_R_SFT 6 |
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/* 0x20 */ |
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#define RT1016_CLK_SYS_SEL_MASK (0x1 << 15) |
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#define RT1016_CLK_SYS_SEL_SFT 15 |
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#define RT1016_CLK_SYS_SEL_MCLK (0x0 << 15) |
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#define RT1016_CLK_SYS_SEL_PLL (0x1 << 15) |
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#define RT1016_PLL_SEL_MASK (0x1 << 13) |
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#define RT1016_PLL_SEL_SFT 13 |
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#define RT1016_PLL_SEL_MCLK (0x0 << 13) |
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#define RT1016_PLL_SEL_BCLK (0x1 << 13) |
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/* 0x21 */ |
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#define RT1016_FS_PD_MASK (0x7 << 13) |
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#define RT1016_FS_PD_SFT 13 |
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#define RT1016_OSR_PD_MASK (0x3 << 10) |
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#define RT1016_OSR_PD_SFT 10 |
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/* 0x22 */ |
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#define RT1016_PWR_DAC_FILTER (0x1 << 11) |
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#define RT1016_PWR_DAC_FILTER_BIT 11 |
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#define RT1016_PWR_DACMOD (0x1 << 10) |
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#define RT1016_PWR_DACMOD_BIT 10 |
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#define RT1016_PWR_CLK_FIFO (0x1 << 9) |
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#define RT1016_PWR_CLK_FIFO_BIT 9 |
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#define RT1016_PWR_CLK_PUREDC (0x1 << 8) |
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#define RT1016_PWR_CLK_PUREDC_BIT 8 |
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#define RT1016_PWR_SIL_DET (0x1 << 7) |
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#define RT1016_PWR_SIL_DET_BIT 7 |
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#define RT1016_PWR_RC_25M (0x1 << 6) |
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#define RT1016_PWR_RC_25M_BIT 6 |
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#define RT1016_PWR_PLL1 (0x1 << 5) |
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#define RT1016_PWR_PLL1_BIT 5 |
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#define RT1016_PWR_ANA_CTRL (0x1 << 4) |
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#define RT1016_PWR_ANA_CTRL_BIT 4 |
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#define RT1016_PWR_CLK_SYS (0x1 << 3) |
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#define RT1016_PWR_CLK_SYS_BIT 3 |
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/* 0x23 */ |
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#define RT1016_PWR_LRCK_DET (0x1 << 15) |
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#define RT1016_PWR_LRCK_DET_BIT 15 |
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#define RT1016_PWR_BCLK_DET (0x1 << 11) |
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#define RT1016_PWR_BCLK_DET_BIT 11 |
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/* 0x40 */ |
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#define RT1016_I2S_BCLK_MS_MASK (0x1 << 15) |
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#define RT1016_I2S_BCLK_MS_SFT 15 |
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#define RT1016_I2S_BCLK_MS_32 (0x0 << 15) |
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#define RT1016_I2S_BCLK_MS_64 (0x1 << 15) |
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#define RT1016_I2S_BCLK_POL_MASK (0x1 << 13) |
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#define RT1016_I2S_BCLK_POL_SFT 13 |
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#define RT1016_I2S_BCLK_POL_NOR (0x0 << 13) |
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#define RT1016_I2S_BCLK_POL_INV (0x1 << 13) |
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#define RT1016_I2S_DATA_SWAP_MASK (0x1 << 10) |
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#define RT1016_I2S_DATA_SWAP_SFT 10 |
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#define RT1016_I2S_DL_MASK (0x7 << 4) |
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#define RT1016_I2S_DL_SFT 4 |
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#define RT1016_I2S_DL_16 (0x1 << 4) |
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#define RT1016_I2S_DL_20 (0x2 << 4) |
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#define RT1016_I2S_DL_24 (0x3 << 4) |
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#define RT1016_I2S_DL_32 (0x4 << 4) |
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#define RT1016_I2S_MS_MASK (0x1 << 3) |
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#define RT1016_I2S_MS_SFT 3 |
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#define RT1016_I2S_MS_M (0x0 << 3) |
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#define RT1016_I2S_MS_S (0x1 << 3) |
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#define RT1016_I2S_DF_MASK (0x7 << 0) |
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#define RT1016_I2S_DF_SFT 0 |
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#define RT1016_I2S_DF_I2S (0x0) |
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#define RT1016_I2S_DF_LEFT (0x1) |
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#define RT1016_I2S_DF_PCM_A (0x2) |
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#define RT1016_I2S_DF_PCM_B (0x3) |
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/* 0xa0 */ |
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#define RT1016_SIL_DET_EN (0x1 << 15) |
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#define RT1016_SIL_DET_EN_BIT 15 |
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/* 0xc2 */ |
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#define RT1016_CKGEN_DAC (0x1 << 13) |
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#define RT1016_CKGEN_DAC_BIT 13 |
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/* 0xc4 */ |
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#define RT1016_VCM_SLOW (0x1 << 6) |
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#define RT1016_VCM_SLOW_BIT 6 |
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/* 0xc5 */ |
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#define RT1016_PLL_M_MAX 0xf |
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#define RT1016_PLL_M_MASK (RT1016_PLL_M_MAX << 12) |
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#define RT1016_PLL_M_SFT 12 |
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#define RT1016_PLL_M_BP (0x1 << 11) |
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#define RT1016_PLL_M_BP_SFT 11 |
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#define RT1016_PLL_N_MAX 0x1ff |
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#define RT1016_PLL_N_MASK (RT1016_PLL_N_MAX << 0) |
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#define RT1016_PLL_N_SFT 0 |
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/* 0xc6 */ |
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#define RT1016_PLL2_EN (0x1 << 15) |
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#define RT1016_PLL2_EN_BIT 15 |
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#define RT1016_PLL_K_BP (0x1 << 5) |
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#define RT1016_PLL_K_BP_SFT 5 |
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#define RT1016_PLL_K_MAX 0x1f |
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#define RT1016_PLL_K_MASK (RT1016_PLL_K_MAX) |
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#define RT1016_PLL_K_SFT 0 |
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/* 0xcf */ |
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#define RT1016_PWR_BG_1_2 (0x1 << 12) |
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#define RT1016_PWR_BG_1_2_BIT 12 |
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#define RT1016_PWR_MBIAS_BG (0x1 << 11) |
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#define RT1016_PWR_MBIAS_BG_BIT 11 |
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#define RT1016_PWR_PLL (0x1 << 9) |
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#define RT1016_PWR_PLL_BIT 9 |
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#define RT1016_PWR_BASIC (0x1 << 8) |
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#define RT1016_PWR_BASIC_BIT 8 |
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#define RT1016_PWR_CLSD (0x1 << 7) |
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#define RT1016_PWR_CLSD_BIT 7 |
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#define RT1016_PWR_25M (0x1 << 6) |
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#define RT1016_PWR_25M_BIT 6 |
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#define RT1016_PWR_DACL (0x1 << 4) |
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#define RT1016_PWR_DACL_BIT 4 |
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#define RT1016_PWR_DACR (0x1 << 3) |
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#define RT1016_PWR_DACR_BIT 3 |
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#define RT1016_PWR_LDO2 (0x1 << 2) |
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#define RT1016_PWR_LDO2_BIT 2 |
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#define RT1016_PWR_VREF (0x1 << 1) |
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#define RT1016_PWR_VREF_BIT 1 |
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#define RT1016_PWR_MBIAS (0x1 << 0) |
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#define RT1016_PWR_MBIAS_BIT 0 |
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/* System Clock Source */ |
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enum { |
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RT1016_SCLK_S_MCLK, |
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RT1016_SCLK_S_PLL, |
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}; |
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/* PLL1 Source */ |
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enum { |
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RT1016_PLL_S_MCLK, |
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RT1016_PLL_S_BCLK, |
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}; |
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enum { |
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RT1016_AIF1, |
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RT1016_AIFS, |
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}; |
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struct rt1016_priv { |
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struct snd_soc_component *component; |
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struct regmap *regmap; |
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int sysclk; |
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int sysclk_src; |
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int lrck; |
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int bclk; |
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int master; |
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int pll_src; |
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int pll_in; |
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int pll_out; |
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}; |
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#endif /* __RT1016_H__ */
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