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207 lines
5.6 KiB
207 lines
5.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ACP_HW_H |
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#define __ACP_HW_H |
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#include "include/acp_2_2_d.h" |
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#include "include/acp_2_2_sh_mask.h" |
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#define ACP_PAGE_SIZE_4K_ENABLE 0x02 |
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#define ACP_PLAYBACK_PTE_OFFSET 10 |
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#define ACP_CAPTURE_PTE_OFFSET 0 |
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/* Playback and Capture Offset for Stoney */ |
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#define ACP_ST_PLAYBACK_PTE_OFFSET 0x04 |
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#define ACP_ST_CAPTURE_PTE_OFFSET 0x00 |
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#define ACP_ST_BT_PLAYBACK_PTE_OFFSET 0x08 |
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#define ACP_ST_BT_CAPTURE_PTE_OFFSET 0x0c |
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#define ACP_GARLIC_CNTL_DEFAULT 0x00000FB4 |
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#define ACP_ONION_CNTL_DEFAULT 0x00000FB4 |
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#define ACP_PHYSICAL_BASE 0x14000 |
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/* |
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* In case of I2S SP controller instance, Stoney uses SRAM bank 1 for |
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* playback and SRAM Bank 2 for capture where as in case of BT I2S |
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* Instance, Stoney uses SRAM Bank 3 for playback & SRAM Bank 4 will |
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* be used for capture. Carrizo uses I2S SP controller instance. SRAM Banks |
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* 1, 2, 3, 4 will be used for playback & SRAM Banks 5, 6, 7, 8 will be used |
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* for capture scenario. |
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*/ |
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#define ACP_SRAM_BANK_1_ADDRESS 0x4002000 |
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#define ACP_SRAM_BANK_2_ADDRESS 0x4004000 |
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#define ACP_SRAM_BANK_3_ADDRESS 0x4006000 |
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#define ACP_SRAM_BANK_4_ADDRESS 0x4008000 |
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#define ACP_SRAM_BANK_5_ADDRESS 0x400A000 |
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#define ACP_DMA_RESET_TIME 10000 |
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#define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF |
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#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF |
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#define ACP_DMA_COMPLETE_TIME_OUT_VALUE 0x000000FF |
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#define ACP_SRAM_BASE_ADDRESS 0x4000000 |
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#define ACP_DAGB_GRP_SRAM_BASE_ADDRESS 0x4001000 |
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#define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET 0x1000 |
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#define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 0x00000000 |
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#define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS 0x01800000 |
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#define TO_ACP_I2S_1 0x2 |
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#define TO_ACP_I2S_2 0x4 |
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#define TO_BLUETOOTH 0x3 |
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#define FROM_ACP_I2S_1 0xa |
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#define FROM_ACP_I2S_2 0xb |
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#define FROM_BLUETOOTH 0xb |
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#define I2S_SP_INSTANCE 0x01 |
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#define I2S_BT_INSTANCE 0x02 |
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#define CAP_CHANNEL0 0x00 |
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#define CAP_CHANNEL1 0x01 |
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#define ACP_TILE_ON_MASK 0x03 |
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#define ACP_TILE_OFF_MASK 0x02 |
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#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f |
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#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 |
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#define ACP_TILE_P1_MASK 0x3e |
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#define ACP_TILE_P2_MASK 0x3d |
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#define ACP_TILE_DSP0_MASK 0x3b |
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#define ACP_TILE_DSP1_MASK 0x37 |
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#define ACP_TILE_DSP2_MASK 0x2f |
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/* Playback DMA channels */ |
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#define SYSRAM_TO_ACP_CH_NUM 12 |
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#define ACP_TO_I2S_DMA_CH_NUM 13 |
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/* Capture DMA channels */ |
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#define I2S_TO_ACP_DMA_CH_NUM 14 |
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#define ACP_TO_SYSRAM_CH_NUM 15 |
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/* Playback DMA Channels for I2S BT instance */ |
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#define SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM 8 |
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#define ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM 9 |
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/* Capture DMA Channels for I2S BT Instance */ |
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#define I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM 10 |
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#define ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM 11 |
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#define NUM_DSCRS_PER_CHANNEL 2 |
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#define PLAYBACK_START_DMA_DESCR_CH12 0 |
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#define PLAYBACK_END_DMA_DESCR_CH12 1 |
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#define PLAYBACK_START_DMA_DESCR_CH13 2 |
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#define PLAYBACK_END_DMA_DESCR_CH13 3 |
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#define CAPTURE_START_DMA_DESCR_CH14 4 |
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#define CAPTURE_END_DMA_DESCR_CH14 5 |
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#define CAPTURE_START_DMA_DESCR_CH15 6 |
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#define CAPTURE_END_DMA_DESCR_CH15 7 |
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/* I2S BT Instance DMA Descriptors */ |
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#define PLAYBACK_START_DMA_DESCR_CH8 8 |
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#define PLAYBACK_END_DMA_DESCR_CH8 9 |
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#define PLAYBACK_START_DMA_DESCR_CH9 10 |
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#define PLAYBACK_END_DMA_DESCR_CH9 11 |
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#define CAPTURE_START_DMA_DESCR_CH10 12 |
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#define CAPTURE_END_DMA_DESCR_CH10 13 |
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#define CAPTURE_START_DMA_DESCR_CH11 14 |
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#define CAPTURE_END_DMA_DESCR_CH11 15 |
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#define mmACP_I2S_16BIT_RESOLUTION_EN 0x5209 |
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#define ACP_I2S_MIC_16BIT_RESOLUTION_EN 0x01 |
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#define ACP_I2S_SP_16BIT_RESOLUTION_EN 0x02 |
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#define ACP_I2S_BT_16BIT_RESOLUTION_EN 0x04 |
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#define ACP_BT_UART_PAD_SELECT_MASK 0x1 |
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enum acp_dma_priority_level { |
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/* 0x0 Specifies the DMA channel is given normal priority */ |
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ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0, |
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/* 0x1 Specifies the DMA channel is given high priority */ |
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ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1, |
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ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF |
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}; |
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struct audio_substream_data { |
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dma_addr_t dma_addr; |
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unsigned int order; |
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u16 num_of_pages; |
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u16 i2s_instance; |
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u16 capture_channel; |
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u16 direction; |
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u16 ch1; |
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u16 ch2; |
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u16 destination; |
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u16 dma_dscr_idx_1; |
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u16 dma_dscr_idx_2; |
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u32 pte_offset; |
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u32 sram_bank; |
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u32 byte_cnt_high_reg_offset; |
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u32 byte_cnt_low_reg_offset; |
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u32 dma_curr_dscr; |
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uint64_t size; |
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u64 bytescount; |
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void __iomem *acp_mmio; |
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}; |
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struct audio_drv_data { |
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struct snd_pcm_substream *play_i2ssp_stream; |
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struct snd_pcm_substream *capture_i2ssp_stream; |
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struct snd_pcm_substream *play_i2sbt_stream; |
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struct snd_pcm_substream *capture_i2sbt_stream; |
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void __iomem *acp_mmio; |
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u32 asic_type; |
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}; |
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/* |
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* this structure used for platform data transfer between machine driver |
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* and dma driver |
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*/ |
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struct acp_platform_info { |
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u16 play_i2s_instance; |
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u16 cap_i2s_instance; |
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u16 capture_channel; |
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}; |
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union acp_dma_count { |
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struct { |
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u32 low; |
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u32 high; |
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} bcount; |
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u64 bytescount; |
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}; |
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enum { |
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ACP_TILE_P1 = 0, |
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ACP_TILE_P2, |
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ACP_TILE_DSP0, |
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ACP_TILE_DSP1, |
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ACP_TILE_DSP2, |
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}; |
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enum { |
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ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION = 0x0, |
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ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC = 0x1, |
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ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM = 0x8, |
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ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM = 0x9, |
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ACP_DMA_ATTR_FORCE_SIZE = 0xF |
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}; |
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typedef struct acp_dma_dscr_transfer { |
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/* Specifies the source memory location for the DMA data transfer. */ |
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u32 src; |
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/* |
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* Specifies the destination memory location to where the data will |
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* be transferred. |
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*/ |
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u32 dest; |
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/* |
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* Specifies the number of bytes need to be transferred |
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* from source to destination memory.Transfer direction & IOC enable |
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*/ |
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u32 xfer_val; |
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/* Reserved for future use */ |
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u32 reserved; |
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} acp_dma_dscr_transfer_t; |
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#endif /*__ACP_HW_H */
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