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381 lines
9.0 KiB
381 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Spreadtrum watchdog driver |
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* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/watchdog.h> |
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#define SPRD_WDT_LOAD_LOW 0x0 |
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#define SPRD_WDT_LOAD_HIGH 0x4 |
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#define SPRD_WDT_CTRL 0x8 |
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#define SPRD_WDT_INT_CLR 0xc |
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#define SPRD_WDT_INT_RAW 0x10 |
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#define SPRD_WDT_INT_MSK 0x14 |
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#define SPRD_WDT_CNT_LOW 0x18 |
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#define SPRD_WDT_CNT_HIGH 0x1c |
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#define SPRD_WDT_LOCK 0x20 |
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#define SPRD_WDT_IRQ_LOAD_LOW 0x2c |
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#define SPRD_WDT_IRQ_LOAD_HIGH 0x30 |
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/* WDT_CTRL */ |
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#define SPRD_WDT_INT_EN_BIT BIT(0) |
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#define SPRD_WDT_CNT_EN_BIT BIT(1) |
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#define SPRD_WDT_NEW_VER_EN BIT(2) |
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#define SPRD_WDT_RST_EN_BIT BIT(3) |
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/* WDT_INT_CLR */ |
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#define SPRD_WDT_INT_CLEAR_BIT BIT(0) |
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#define SPRD_WDT_RST_CLEAR_BIT BIT(3) |
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/* WDT_INT_RAW */ |
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#define SPRD_WDT_INT_RAW_BIT BIT(0) |
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#define SPRD_WDT_RST_RAW_BIT BIT(3) |
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#define SPRD_WDT_LD_BUSY_BIT BIT(4) |
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/* 1s equal to 32768 counter steps */ |
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#define SPRD_WDT_CNT_STEP 32768 |
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#define SPRD_WDT_UNLOCK_KEY 0xe551 |
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#define SPRD_WDT_MIN_TIMEOUT 3 |
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#define SPRD_WDT_MAX_TIMEOUT 60 |
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#define SPRD_WDT_CNT_HIGH_SHIFT 16 |
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#define SPRD_WDT_LOW_VALUE_MASK GENMASK(15, 0) |
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#define SPRD_WDT_LOAD_TIMEOUT 11 |
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struct sprd_wdt { |
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void __iomem *base; |
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struct watchdog_device wdd; |
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struct clk *enable; |
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struct clk *rtc_enable; |
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int irq; |
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}; |
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static inline struct sprd_wdt *to_sprd_wdt(struct watchdog_device *wdd) |
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{ |
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return container_of(wdd, struct sprd_wdt, wdd); |
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} |
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static inline void sprd_wdt_lock(void __iomem *addr) |
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{ |
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writel_relaxed(0x0, addr + SPRD_WDT_LOCK); |
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} |
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static inline void sprd_wdt_unlock(void __iomem *addr) |
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{ |
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writel_relaxed(SPRD_WDT_UNLOCK_KEY, addr + SPRD_WDT_LOCK); |
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} |
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static irqreturn_t sprd_wdt_isr(int irq, void *dev_id) |
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{ |
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struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id; |
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sprd_wdt_unlock(wdt->base); |
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writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR); |
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sprd_wdt_lock(wdt->base); |
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watchdog_notify_pretimeout(&wdt->wdd); |
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return IRQ_HANDLED; |
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} |
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static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt) |
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{ |
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u32 val; |
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val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) << |
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SPRD_WDT_CNT_HIGH_SHIFT; |
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val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) & |
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SPRD_WDT_LOW_VALUE_MASK; |
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return val; |
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} |
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static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout, |
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u32 pretimeout) |
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{ |
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u32 val, delay_cnt = 0; |
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u32 tmr_step = timeout * SPRD_WDT_CNT_STEP; |
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u32 prtmr_step = pretimeout * SPRD_WDT_CNT_STEP; |
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/* |
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* Checking busy bit to make sure the previous loading operation is |
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* done. According to the specification, the busy bit would be set |
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* after a new loading operation and last 2 or 3 RTC clock |
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* cycles (about 60us~92us). |
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*/ |
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do { |
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val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW); |
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if (!(val & SPRD_WDT_LD_BUSY_BIT)) |
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break; |
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usleep_range(10, 100); |
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} while (delay_cnt++ < SPRD_WDT_LOAD_TIMEOUT); |
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if (delay_cnt >= SPRD_WDT_LOAD_TIMEOUT) |
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return -EBUSY; |
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sprd_wdt_unlock(wdt->base); |
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writel_relaxed((tmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) & |
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SPRD_WDT_LOW_VALUE_MASK, wdt->base + SPRD_WDT_LOAD_HIGH); |
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writel_relaxed((tmr_step & SPRD_WDT_LOW_VALUE_MASK), |
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wdt->base + SPRD_WDT_LOAD_LOW); |
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writel_relaxed((prtmr_step >> SPRD_WDT_CNT_HIGH_SHIFT) & |
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SPRD_WDT_LOW_VALUE_MASK, |
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wdt->base + SPRD_WDT_IRQ_LOAD_HIGH); |
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writel_relaxed(prtmr_step & SPRD_WDT_LOW_VALUE_MASK, |
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wdt->base + SPRD_WDT_IRQ_LOAD_LOW); |
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sprd_wdt_lock(wdt->base); |
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return 0; |
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} |
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static int sprd_wdt_enable(struct sprd_wdt *wdt) |
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{ |
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u32 val; |
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int ret; |
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ret = clk_prepare_enable(wdt->enable); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(wdt->rtc_enable); |
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if (ret) { |
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clk_disable_unprepare(wdt->enable); |
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return ret; |
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} |
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sprd_wdt_unlock(wdt->base); |
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val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); |
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val |= SPRD_WDT_NEW_VER_EN; |
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writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); |
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sprd_wdt_lock(wdt->base); |
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return 0; |
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} |
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static void sprd_wdt_disable(void *_data) |
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{ |
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struct sprd_wdt *wdt = _data; |
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sprd_wdt_unlock(wdt->base); |
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writel_relaxed(0x0, wdt->base + SPRD_WDT_CTRL); |
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sprd_wdt_lock(wdt->base); |
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clk_disable_unprepare(wdt->rtc_enable); |
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clk_disable_unprepare(wdt->enable); |
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} |
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static int sprd_wdt_start(struct watchdog_device *wdd) |
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{ |
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struct sprd_wdt *wdt = to_sprd_wdt(wdd); |
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u32 val; |
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int ret; |
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ret = sprd_wdt_load_value(wdt, wdd->timeout, wdd->pretimeout); |
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if (ret) |
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return ret; |
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sprd_wdt_unlock(wdt->base); |
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val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); |
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val |= SPRD_WDT_CNT_EN_BIT | SPRD_WDT_INT_EN_BIT | SPRD_WDT_RST_EN_BIT; |
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writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); |
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sprd_wdt_lock(wdt->base); |
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set_bit(WDOG_HW_RUNNING, &wdd->status); |
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return 0; |
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} |
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static int sprd_wdt_stop(struct watchdog_device *wdd) |
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{ |
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struct sprd_wdt *wdt = to_sprd_wdt(wdd); |
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u32 val; |
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sprd_wdt_unlock(wdt->base); |
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val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); |
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val &= ~(SPRD_WDT_CNT_EN_BIT | SPRD_WDT_RST_EN_BIT | |
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SPRD_WDT_INT_EN_BIT); |
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writel_relaxed(val, wdt->base + SPRD_WDT_CTRL); |
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sprd_wdt_lock(wdt->base); |
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return 0; |
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} |
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static int sprd_wdt_set_timeout(struct watchdog_device *wdd, |
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u32 timeout) |
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{ |
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struct sprd_wdt *wdt = to_sprd_wdt(wdd); |
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if (timeout == wdd->timeout) |
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return 0; |
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wdd->timeout = timeout; |
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return sprd_wdt_load_value(wdt, timeout, wdd->pretimeout); |
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} |
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static int sprd_wdt_set_pretimeout(struct watchdog_device *wdd, |
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u32 new_pretimeout) |
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{ |
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struct sprd_wdt *wdt = to_sprd_wdt(wdd); |
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if (new_pretimeout < wdd->min_timeout) |
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return -EINVAL; |
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wdd->pretimeout = new_pretimeout; |
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return sprd_wdt_load_value(wdt, wdd->timeout, new_pretimeout); |
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} |
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static u32 sprd_wdt_get_timeleft(struct watchdog_device *wdd) |
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{ |
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struct sprd_wdt *wdt = to_sprd_wdt(wdd); |
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u32 val; |
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val = sprd_wdt_get_cnt_value(wdt); |
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return val / SPRD_WDT_CNT_STEP; |
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} |
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static const struct watchdog_ops sprd_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = sprd_wdt_start, |
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.stop = sprd_wdt_stop, |
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.set_timeout = sprd_wdt_set_timeout, |
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.set_pretimeout = sprd_wdt_set_pretimeout, |
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.get_timeleft = sprd_wdt_get_timeleft, |
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}; |
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static const struct watchdog_info sprd_wdt_info = { |
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.options = WDIOF_SETTIMEOUT | |
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WDIOF_PRETIMEOUT | |
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WDIOF_MAGICCLOSE | |
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WDIOF_KEEPALIVEPING, |
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.identity = "Spreadtrum Watchdog Timer", |
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}; |
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static int sprd_wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct sprd_wdt *wdt; |
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int ret; |
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) |
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return -ENOMEM; |
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wdt->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(wdt->base)) |
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return PTR_ERR(wdt->base); |
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wdt->enable = devm_clk_get(dev, "enable"); |
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if (IS_ERR(wdt->enable)) { |
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dev_err(dev, "can't get the enable clock\n"); |
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return PTR_ERR(wdt->enable); |
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} |
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wdt->rtc_enable = devm_clk_get(dev, "rtc_enable"); |
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if (IS_ERR(wdt->rtc_enable)) { |
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dev_err(dev, "can't get the rtc enable clock\n"); |
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return PTR_ERR(wdt->rtc_enable); |
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} |
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wdt->irq = platform_get_irq(pdev, 0); |
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if (wdt->irq < 0) |
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return wdt->irq; |
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ret = devm_request_irq(dev, wdt->irq, sprd_wdt_isr, IRQF_NO_SUSPEND, |
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"sprd-wdt", (void *)wdt); |
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if (ret) { |
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dev_err(dev, "failed to register irq\n"); |
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return ret; |
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} |
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wdt->wdd.info = &sprd_wdt_info; |
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wdt->wdd.ops = &sprd_wdt_ops; |
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wdt->wdd.parent = dev; |
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wdt->wdd.min_timeout = SPRD_WDT_MIN_TIMEOUT; |
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wdt->wdd.max_timeout = SPRD_WDT_MAX_TIMEOUT; |
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wdt->wdd.timeout = SPRD_WDT_MAX_TIMEOUT; |
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ret = sprd_wdt_enable(wdt); |
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if (ret) { |
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dev_err(dev, "failed to enable wdt\n"); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(dev, sprd_wdt_disable, wdt); |
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if (ret) { |
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dev_err(dev, "Failed to add wdt disable action\n"); |
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return ret; |
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} |
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watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT); |
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watchdog_init_timeout(&wdt->wdd, 0, dev); |
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ret = devm_watchdog_register_device(dev, &wdt->wdd); |
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if (ret) { |
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sprd_wdt_disable(wdt); |
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return ret; |
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} |
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platform_set_drvdata(pdev, wdt); |
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return 0; |
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} |
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static int __maybe_unused sprd_wdt_pm_suspend(struct device *dev) |
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{ |
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struct sprd_wdt *wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&wdt->wdd)) |
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sprd_wdt_stop(&wdt->wdd); |
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sprd_wdt_disable(wdt); |
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return 0; |
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} |
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static int __maybe_unused sprd_wdt_pm_resume(struct device *dev) |
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{ |
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struct sprd_wdt *wdt = dev_get_drvdata(dev); |
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int ret; |
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ret = sprd_wdt_enable(wdt); |
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if (ret) |
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return ret; |
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if (watchdog_active(&wdt->wdd)) |
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ret = sprd_wdt_start(&wdt->wdd); |
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return ret; |
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} |
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static const struct dev_pm_ops sprd_wdt_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(sprd_wdt_pm_suspend, |
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sprd_wdt_pm_resume) |
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}; |
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static const struct of_device_id sprd_wdt_match_table[] = { |
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{ .compatible = "sprd,sp9860-wdt", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, sprd_wdt_match_table); |
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static struct platform_driver sprd_watchdog_driver = { |
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.probe = sprd_wdt_probe, |
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.driver = { |
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.name = "sprd-wdt", |
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.of_match_table = sprd_wdt_match_table, |
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.pm = &sprd_wdt_pm_ops, |
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}, |
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}; |
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module_platform_driver(sprd_watchdog_driver); |
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MODULE_AUTHOR("Eric Long <[email protected]>"); |
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MODULE_DESCRIPTION("Spreadtrum Watchdog Timer Controller Driver"); |
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MODULE_LICENSE("GPL v2");
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