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524 lines
12 KiB
524 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/kobject.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/nvmem-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/sys_soc.h> |
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#include <soc/tegra/common.h> |
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#include <soc/tegra/fuse.h> |
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#include "fuse.h" |
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struct tegra_sku_info tegra_sku_info; |
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EXPORT_SYMBOL(tegra_sku_info); |
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static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { |
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[TEGRA_REVISION_UNKNOWN] = "unknown", |
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[TEGRA_REVISION_A01] = "A01", |
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[TEGRA_REVISION_A02] = "A02", |
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[TEGRA_REVISION_A03] = "A03", |
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[TEGRA_REVISION_A03p] = "A03 prime", |
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[TEGRA_REVISION_A04] = "A04", |
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}; |
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static const struct of_device_id car_match[] __initconst = { |
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{ .compatible = "nvidia,tegra20-car", }, |
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{ .compatible = "nvidia,tegra30-car", }, |
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{ .compatible = "nvidia,tegra114-car", }, |
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{ .compatible = "nvidia,tegra124-car", }, |
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{ .compatible = "nvidia,tegra132-car", }, |
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{ .compatible = "nvidia,tegra210-car", }, |
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{}, |
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}; |
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static struct tegra_fuse *fuse = &(struct tegra_fuse) { |
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.base = NULL, |
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.soc = NULL, |
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}; |
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static const struct of_device_id tegra_fuse_match[] = { |
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#ifdef CONFIG_ARCH_TEGRA_234_SOC |
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{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_194_SOC |
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{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_186_SOC |
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{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_210_SOC |
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{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_132_SOC |
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{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_124_SOC |
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{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_114_SOC |
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{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC |
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{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
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{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc }, |
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#endif |
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{ /* sentinel */ } |
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}; |
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static int tegra_fuse_read(void *priv, unsigned int offset, void *value, |
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size_t bytes) |
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{ |
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unsigned int count = bytes / 4, i; |
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struct tegra_fuse *fuse = priv; |
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u32 *buffer = value; |
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for (i = 0; i < count; i++) |
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buffer[i] = fuse->read(fuse, offset + i * 4); |
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return 0; |
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} |
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static const struct nvmem_cell_info tegra_fuse_cells[] = { |
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{ |
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.name = "tsensor-cpu1", |
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.offset = 0x084, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-cpu2", |
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.offset = 0x088, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-cpu0", |
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.offset = 0x098, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "xusb-pad-calibration", |
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.offset = 0x0f0, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-cpu3", |
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.offset = 0x12c, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "sata-calibration", |
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.offset = 0x124, |
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.bytes = 1, |
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.bit_offset = 0, |
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.nbits = 2, |
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}, { |
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.name = "tsensor-gpu", |
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.offset = 0x154, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-mem0", |
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.offset = 0x158, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-mem1", |
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.offset = 0x15c, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-pllx", |
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.offset = 0x160, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-common", |
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.offset = 0x180, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "tsensor-realignment", |
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.offset = 0x1fc, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "gpu-calibration", |
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.offset = 0x204, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, { |
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.name = "xusb-pad-calibration-ext", |
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.offset = 0x250, |
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.bytes = 4, |
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.bit_offset = 0, |
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.nbits = 32, |
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}, |
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}; |
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static int tegra_fuse_probe(struct platform_device *pdev) |
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{ |
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void __iomem *base = fuse->base; |
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struct nvmem_config nvmem; |
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struct resource *res; |
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int err; |
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/* take over the memory region from the early initialization */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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fuse->phys = res->start; |
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fuse->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(fuse->base)) { |
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err = PTR_ERR(fuse->base); |
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fuse->base = base; |
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return err; |
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} |
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fuse->clk = devm_clk_get(&pdev->dev, "fuse"); |
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if (IS_ERR(fuse->clk)) { |
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if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) |
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dev_err(&pdev->dev, "failed to get FUSE clock: %ld", |
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PTR_ERR(fuse->clk)); |
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fuse->base = base; |
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return PTR_ERR(fuse->clk); |
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} |
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platform_set_drvdata(pdev, fuse); |
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fuse->dev = &pdev->dev; |
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if (fuse->soc->probe) { |
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err = fuse->soc->probe(fuse); |
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if (err < 0) |
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goto restore; |
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} |
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memset(&nvmem, 0, sizeof(nvmem)); |
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nvmem.dev = &pdev->dev; |
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nvmem.name = "fuse"; |
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nvmem.id = -1; |
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nvmem.owner = THIS_MODULE; |
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nvmem.cells = tegra_fuse_cells; |
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nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); |
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nvmem.type = NVMEM_TYPE_OTP; |
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nvmem.read_only = true; |
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nvmem.root_only = true; |
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nvmem.reg_read = tegra_fuse_read; |
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nvmem.size = fuse->soc->info->size; |
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nvmem.word_size = 4; |
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nvmem.stride = 4; |
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nvmem.priv = fuse; |
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fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem); |
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if (IS_ERR(fuse->nvmem)) { |
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err = PTR_ERR(fuse->nvmem); |
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dev_err(&pdev->dev, "failed to register NVMEM device: %d\n", |
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err); |
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goto restore; |
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} |
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/* release the early I/O memory mapping */ |
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iounmap(base); |
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return 0; |
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restore: |
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fuse->base = base; |
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return err; |
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} |
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static struct platform_driver tegra_fuse_driver = { |
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.driver = { |
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.name = "tegra-fuse", |
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.of_match_table = tegra_fuse_match, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = tegra_fuse_probe, |
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}; |
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builtin_platform_driver(tegra_fuse_driver); |
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bool __init tegra_fuse_read_spare(unsigned int spare) |
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{ |
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unsigned int offset = fuse->soc->info->spare + spare * 4; |
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return fuse->read_early(fuse, offset) & 1; |
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} |
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u32 __init tegra_fuse_read_early(unsigned int offset) |
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{ |
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return fuse->read_early(fuse, offset); |
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} |
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int tegra_fuse_readl(unsigned long offset, u32 *value) |
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{ |
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if (!fuse->read || !fuse->clk) |
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return -EPROBE_DEFER; |
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if (IS_ERR(fuse->clk)) |
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return PTR_ERR(fuse->clk); |
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*value = fuse->read(fuse, offset); |
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return 0; |
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} |
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EXPORT_SYMBOL(tegra_fuse_readl); |
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static void tegra_enable_fuse_clk(void __iomem *base) |
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{ |
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u32 reg; |
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reg = readl_relaxed(base + 0x48); |
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reg |= 1 << 28; |
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writel(reg, base + 0x48); |
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/* |
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* Enable FUSE clock. This needs to be hardcoded because the clock |
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* subsystem is not active during early boot. |
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*/ |
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reg = readl(base + 0x14); |
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reg |= 1 << 7; |
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writel(reg, base + 0x14); |
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} |
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static ssize_t major_show(struct device *dev, struct device_attribute *attr, |
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char *buf) |
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{ |
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return sprintf(buf, "%d\n", tegra_get_major_rev()); |
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} |
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static DEVICE_ATTR_RO(major); |
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static ssize_t minor_show(struct device *dev, struct device_attribute *attr, |
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char *buf) |
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{ |
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return sprintf(buf, "%d\n", tegra_get_minor_rev()); |
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} |
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static DEVICE_ATTR_RO(minor); |
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static struct attribute *tegra_soc_attr[] = { |
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&dev_attr_major.attr, |
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&dev_attr_minor.attr, |
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NULL, |
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}; |
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const struct attribute_group tegra_soc_attr_group = { |
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.attrs = tegra_soc_attr, |
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}; |
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ |
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IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) |
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static ssize_t platform_show(struct device *dev, struct device_attribute *attr, |
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char *buf) |
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{ |
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/* |
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* Displays the value in the 'pre_si_platform' field of the HIDREV |
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* register for Tegra194 devices. A value of 0 indicates that the |
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* platform type is silicon and all other non-zero values indicate |
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* the type of simulation platform is being used. |
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*/ |
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return sprintf(buf, "%d\n", tegra_get_platform()); |
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} |
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static DEVICE_ATTR_RO(platform); |
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static struct attribute *tegra194_soc_attr[] = { |
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&dev_attr_major.attr, |
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&dev_attr_minor.attr, |
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&dev_attr_platform.attr, |
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NULL, |
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}; |
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const struct attribute_group tegra194_soc_attr_group = { |
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.attrs = tegra194_soc_attr, |
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}; |
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#endif |
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struct device * __init tegra_soc_device_register(void) |
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{ |
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struct soc_device_attribute *attr; |
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struct soc_device *dev; |
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attr = kzalloc(sizeof(*attr), GFP_KERNEL); |
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if (!attr) |
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return NULL; |
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attr->family = kasprintf(GFP_KERNEL, "Tegra"); |
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attr->revision = kasprintf(GFP_KERNEL, "%s", |
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tegra_revision_name[tegra_sku_info.revision]); |
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attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); |
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attr->custom_attr_group = fuse->soc->soc_attr_group; |
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dev = soc_device_register(attr); |
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if (IS_ERR(dev)) { |
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kfree(attr->soc_id); |
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kfree(attr->revision); |
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kfree(attr->family); |
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kfree(attr); |
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return ERR_CAST(dev); |
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} |
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return soc_device_to_device(dev); |
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} |
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static int __init tegra_init_fuse(void) |
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{ |
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const struct of_device_id *match; |
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struct device_node *np; |
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struct resource regs; |
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tegra_init_apbmisc(); |
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np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match); |
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if (!np) { |
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/* |
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* Fall back to legacy initialization for 32-bit ARM only. All |
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* 64-bit ARM device tree files for Tegra are required to have |
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* a FUSE node. |
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* |
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* This is for backwards-compatibility with old device trees |
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* that didn't contain a FUSE node. |
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*/ |
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if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { |
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u8 chip = tegra_get_chip_id(); |
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regs.start = 0x7000f800; |
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regs.end = 0x7000fbff; |
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regs.flags = IORESOURCE_MEM; |
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switch (chip) { |
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
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case TEGRA20: |
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fuse->soc = &tegra20_fuse_soc; |
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break; |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC |
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case TEGRA30: |
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fuse->soc = &tegra30_fuse_soc; |
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break; |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_114_SOC |
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case TEGRA114: |
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fuse->soc = &tegra114_fuse_soc; |
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break; |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_124_SOC |
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case TEGRA124: |
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fuse->soc = &tegra124_fuse_soc; |
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break; |
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#endif |
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default: |
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pr_warn("Unsupported SoC: %02x\n", chip); |
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break; |
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} |
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} else { |
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/* |
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* At this point we're not running on Tegra, so play |
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* nice with multi-platform kernels. |
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*/ |
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return 0; |
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} |
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} else { |
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/* |
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* Extract information from the device tree if we've found a |
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* matching node. |
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*/ |
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if (of_address_to_resource(np, 0, ®s) < 0) { |
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pr_err("failed to get FUSE register\n"); |
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return -ENXIO; |
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} |
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fuse->soc = match->data; |
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} |
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np = of_find_matching_node(NULL, car_match); |
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if (np) { |
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void __iomem *base = of_iomap(np, 0); |
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if (base) { |
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tegra_enable_fuse_clk(base); |
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iounmap(base); |
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} else { |
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pr_err("failed to map clock registers\n"); |
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return -ENXIO; |
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} |
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} |
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fuse->base = ioremap(regs.start, resource_size(®s)); |
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if (!fuse->base) { |
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pr_err("failed to map FUSE registers\n"); |
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return -ENXIO; |
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} |
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fuse->soc->init(fuse); |
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n", |
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tegra_revision_name[tegra_sku_info.revision], |
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tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id, |
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tegra_sku_info.soc_process_id); |
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pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n", |
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tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id); |
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if (fuse->soc->lookups) { |
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size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups; |
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fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL); |
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if (!fuse->lookups) |
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return -ENOMEM; |
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nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups); |
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} |
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return 0; |
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} |
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early_initcall(tegra_init_fuse); |
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#ifdef CONFIG_ARM64 |
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static int __init tegra_init_soc(void) |
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{ |
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struct device_node *np; |
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struct device *soc; |
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/* make sure we're running on Tegra */ |
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np = of_find_matching_node(NULL, tegra_fuse_match); |
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if (!np) |
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return 0; |
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of_node_put(np); |
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soc = tegra_soc_device_register(); |
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if (IS_ERR(soc)) { |
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pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc)); |
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return PTR_ERR(soc); |
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} |
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return 0; |
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} |
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device_initcall(tegra_init_soc); |
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#endif
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