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1147 lines
28 KiB
1147 lines
28 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2015 Pengutronix, Sascha Hauer <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/soc/mediatek/infracfg.h> |
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|
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#include <dt-bindings/power/mt2701-power.h> |
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#include <dt-bindings/power/mt2712-power.h> |
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#include <dt-bindings/power/mt6797-power.h> |
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#include <dt-bindings/power/mt7622-power.h> |
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#include <dt-bindings/power/mt7623a-power.h> |
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#include <dt-bindings/power/mt8173-power.h> |
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|
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#define MTK_POLL_DELAY_US 10 |
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#define MTK_POLL_TIMEOUT USEC_PER_SEC |
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|
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#define MTK_SCPD_ACTIVE_WAKEUP BIT(0) |
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#define MTK_SCPD_FWAIT_SRAM BIT(1) |
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#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) |
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|
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#define SPM_VDE_PWR_CON 0x0210 |
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#define SPM_MFG_PWR_CON 0x0214 |
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#define SPM_VEN_PWR_CON 0x0230 |
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#define SPM_ISP_PWR_CON 0x0238 |
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#define SPM_DIS_PWR_CON 0x023c |
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#define SPM_CONN_PWR_CON 0x0280 |
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#define SPM_VEN2_PWR_CON 0x0298 |
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#define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */ |
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#define SPM_BDP_PWR_CON 0x029c /* MT2701 */ |
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#define SPM_ETH_PWR_CON 0x02a0 |
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#define SPM_HIF_PWR_CON 0x02a4 |
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#define SPM_IFR_MSC_PWR_CON 0x02a8 |
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#define SPM_MFG_2D_PWR_CON 0x02c0 |
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4 |
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#define SPM_USB_PWR_CON 0x02cc |
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#define SPM_USB2_PWR_CON 0x02d4 /* MT2712 */ |
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#define SPM_ETHSYS_PWR_CON 0x02e0 /* MT7622 */ |
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#define SPM_HIF0_PWR_CON 0x02e4 /* MT7622 */ |
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#define SPM_HIF1_PWR_CON 0x02e8 /* MT7622 */ |
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#define SPM_WB_PWR_CON 0x02ec /* MT7622 */ |
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|
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#define SPM_PWR_STATUS 0x060c |
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#define SPM_PWR_STATUS_2ND 0x0610 |
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|
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#define PWR_RST_B_BIT BIT(0) |
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#define PWR_ISO_BIT BIT(1) |
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#define PWR_ON_BIT BIT(2) |
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#define PWR_ON_2ND_BIT BIT(3) |
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#define PWR_CLK_DIS_BIT BIT(4) |
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|
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#define PWR_STATUS_CONN BIT(1) |
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#define PWR_STATUS_DISP BIT(3) |
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#define PWR_STATUS_MFG BIT(4) |
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#define PWR_STATUS_ISP BIT(5) |
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#define PWR_STATUS_VDEC BIT(7) |
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#define PWR_STATUS_BDP BIT(14) |
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#define PWR_STATUS_ETH BIT(15) |
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#define PWR_STATUS_HIF BIT(16) |
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#define PWR_STATUS_IFR_MSC BIT(17) |
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#define PWR_STATUS_USB2 BIT(19) /* MT2712 */ |
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#define PWR_STATUS_VENC_LT BIT(20) |
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#define PWR_STATUS_VENC BIT(21) |
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#define PWR_STATUS_MFG_2D BIT(22) /* MT8173 */ |
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#define PWR_STATUS_MFG_ASYNC BIT(23) /* MT8173 */ |
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#define PWR_STATUS_AUDIO BIT(24) /* MT8173, MT2712 */ |
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#define PWR_STATUS_USB BIT(25) /* MT8173, MT2712 */ |
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#define PWR_STATUS_ETHSYS BIT(24) /* MT7622 */ |
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#define PWR_STATUS_HIF0 BIT(25) /* MT7622 */ |
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#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ |
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#define PWR_STATUS_WB BIT(27) /* MT7622 */ |
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|
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enum clk_id { |
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CLK_NONE, |
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CLK_MM, |
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CLK_MFG, |
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CLK_VENC, |
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CLK_VENC_LT, |
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CLK_ETHIF, |
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CLK_VDEC, |
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CLK_HIFSEL, |
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CLK_JPGDEC, |
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CLK_AUDIO, |
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CLK_MAX, |
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}; |
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|
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static const char * const clk_names[] = { |
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NULL, |
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"mm", |
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"mfg", |
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"venc", |
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"venc_lt", |
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"ethif", |
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"vdec", |
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"hif_sel", |
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"jpgdec", |
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"audio", |
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NULL, |
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}; |
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|
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#define MAX_CLKS 3 |
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|
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/** |
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* struct scp_domain_data - scp domain data for power on/off flow |
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* @name: The domain name. |
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* @sta_mask: The mask for power on/off status bit. |
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* @ctl_offs: The offset for main power control register. |
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* @sram_pdn_bits: The mask for sram power control bits. |
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* @sram_pdn_ack_bits: The mask for sram power control acked bits. |
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* @bus_prot_mask: The mask for single step bus protection. |
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* @clk_id: The basic clocks required by this power domain. |
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* @caps: The flag for active wake-up action. |
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*/ |
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struct scp_domain_data { |
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const char *name; |
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u32 sta_mask; |
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int ctl_offs; |
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u32 sram_pdn_bits; |
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u32 sram_pdn_ack_bits; |
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u32 bus_prot_mask; |
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enum clk_id clk_id[MAX_CLKS]; |
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u8 caps; |
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}; |
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|
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struct scp; |
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|
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struct scp_domain { |
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struct generic_pm_domain genpd; |
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struct scp *scp; |
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struct clk *clk[MAX_CLKS]; |
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const struct scp_domain_data *data; |
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struct regulator *supply; |
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}; |
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|
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struct scp_ctrl_reg { |
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int pwr_sta_offs; |
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int pwr_sta2nd_offs; |
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}; |
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|
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struct scp { |
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struct scp_domain *domains; |
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struct genpd_onecell_data pd_data; |
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struct device *dev; |
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void __iomem *base; |
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struct regmap *infracfg; |
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struct scp_ctrl_reg ctrl_reg; |
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bool bus_prot_reg_update; |
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}; |
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|
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struct scp_subdomain { |
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int origin; |
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int subdomain; |
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}; |
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|
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struct scp_soc_data { |
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const struct scp_domain_data *domains; |
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int num_domains; |
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const struct scp_subdomain *subdomains; |
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int num_subdomains; |
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const struct scp_ctrl_reg regs; |
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bool bus_prot_reg_update; |
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}; |
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|
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static int scpsys_domain_is_on(struct scp_domain *scpd) |
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{ |
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struct scp *scp = scpd->scp; |
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|
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u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) & |
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scpd->data->sta_mask; |
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u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) & |
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scpd->data->sta_mask; |
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|
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/* |
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* A domain is on when both status bits are set. If only one is set |
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* return an error. This happens while powering up a domain |
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*/ |
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|
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if (status && status2) |
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return true; |
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if (!status && !status2) |
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return false; |
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|
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return -EINVAL; |
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} |
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|
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static int scpsys_regulator_enable(struct scp_domain *scpd) |
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{ |
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if (!scpd->supply) |
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return 0; |
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|
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return regulator_enable(scpd->supply); |
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} |
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|
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static int scpsys_regulator_disable(struct scp_domain *scpd) |
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{ |
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if (!scpd->supply) |
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return 0; |
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|
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return regulator_disable(scpd->supply); |
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} |
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|
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static void scpsys_clk_disable(struct clk *clk[], int max_num) |
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{ |
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int i; |
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|
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for (i = max_num - 1; i >= 0; i--) |
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clk_disable_unprepare(clk[i]); |
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} |
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|
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static int scpsys_clk_enable(struct clk *clk[], int max_num) |
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{ |
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int i, ret = 0; |
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|
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for (i = 0; i < max_num && clk[i]; i++) { |
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ret = clk_prepare_enable(clk[i]); |
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if (ret) { |
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scpsys_clk_disable(clk, i); |
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break; |
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} |
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} |
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return ret; |
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} |
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static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr) |
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{ |
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u32 val; |
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u32 pdn_ack = scpd->data->sram_pdn_ack_bits; |
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int tmp; |
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val = readl(ctl_addr); |
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val &= ~scpd->data->sram_pdn_bits; |
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writel(val, ctl_addr); |
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/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */ |
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if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) { |
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/* |
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* Currently, MTK_SCPD_FWAIT_SRAM is necessary only for |
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* MT7622_POWER_DOMAIN_WB and thus just a trivial setup |
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* is applied here. |
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*/ |
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usleep_range(12000, 12100); |
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} else { |
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/* Either wait until SRAM_PDN_ACK all 1 or 0 */ |
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int ret = readl_poll_timeout(ctl_addr, tmp, |
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(tmp & pdn_ack) == 0, |
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
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if (ret < 0) |
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return ret; |
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} |
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return 0; |
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} |
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static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) |
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{ |
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u32 val; |
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u32 pdn_ack = scpd->data->sram_pdn_ack_bits; |
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int tmp; |
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val = readl(ctl_addr); |
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val |= scpd->data->sram_pdn_bits; |
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writel(val, ctl_addr); |
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|
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/* Either wait until SRAM_PDN_ACK all 1 or 0 */ |
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return readl_poll_timeout(ctl_addr, tmp, |
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(tmp & pdn_ack) == pdn_ack, |
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
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} |
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static int scpsys_bus_protect_enable(struct scp_domain *scpd) |
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{ |
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struct scp *scp = scpd->scp; |
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if (!scpd->data->bus_prot_mask) |
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return 0; |
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return mtk_infracfg_set_bus_protection(scp->infracfg, |
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scpd->data->bus_prot_mask, |
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scp->bus_prot_reg_update); |
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} |
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static int scpsys_bus_protect_disable(struct scp_domain *scpd) |
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{ |
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struct scp *scp = scpd->scp; |
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|
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if (!scpd->data->bus_prot_mask) |
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return 0; |
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return mtk_infracfg_clear_bus_protection(scp->infracfg, |
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scpd->data->bus_prot_mask, |
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scp->bus_prot_reg_update); |
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} |
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static int scpsys_power_on(struct generic_pm_domain *genpd) |
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{ |
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struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd); |
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struct scp *scp = scpd->scp; |
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void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs; |
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u32 val; |
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int ret, tmp; |
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ret = scpsys_regulator_enable(scpd); |
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if (ret < 0) |
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return ret; |
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ret = scpsys_clk_enable(scpd->clk, MAX_CLKS); |
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if (ret) |
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goto err_clk; |
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/* subsys power on */ |
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val = readl(ctl_addr); |
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val |= PWR_ON_BIT; |
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writel(val, ctl_addr); |
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val |= PWR_ON_2ND_BIT; |
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writel(val, ctl_addr); |
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|
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/* wait until PWR_ACK = 1 */ |
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ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp > 0, |
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
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if (ret < 0) |
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goto err_pwr_ack; |
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|
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val &= ~PWR_CLK_DIS_BIT; |
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writel(val, ctl_addr); |
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|
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val &= ~PWR_ISO_BIT; |
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writel(val, ctl_addr); |
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|
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val |= PWR_RST_B_BIT; |
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writel(val, ctl_addr); |
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|
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ret = scpsys_sram_enable(scpd, ctl_addr); |
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if (ret < 0) |
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goto err_pwr_ack; |
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|
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ret = scpsys_bus_protect_disable(scpd); |
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if (ret < 0) |
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goto err_pwr_ack; |
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|
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return 0; |
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err_pwr_ack: |
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scpsys_clk_disable(scpd->clk, MAX_CLKS); |
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err_clk: |
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scpsys_regulator_disable(scpd); |
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|
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dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name); |
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return ret; |
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} |
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static int scpsys_power_off(struct generic_pm_domain *genpd) |
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{ |
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struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd); |
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struct scp *scp = scpd->scp; |
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void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs; |
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u32 val; |
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int ret, tmp; |
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|
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ret = scpsys_bus_protect_enable(scpd); |
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if (ret < 0) |
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goto out; |
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|
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ret = scpsys_sram_disable(scpd, ctl_addr); |
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if (ret < 0) |
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goto out; |
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|
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/* subsys power off */ |
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val = readl(ctl_addr); |
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val |= PWR_ISO_BIT; |
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writel(val, ctl_addr); |
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|
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val &= ~PWR_RST_B_BIT; |
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writel(val, ctl_addr); |
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|
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val |= PWR_CLK_DIS_BIT; |
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writel(val, ctl_addr); |
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|
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val &= ~PWR_ON_BIT; |
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writel(val, ctl_addr); |
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|
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val &= ~PWR_ON_2ND_BIT; |
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writel(val, ctl_addr); |
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|
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/* wait until PWR_ACK = 0 */ |
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ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp == 0, |
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MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); |
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if (ret < 0) |
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goto out; |
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scpsys_clk_disable(scpd->clk, MAX_CLKS); |
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|
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ret = scpsys_regulator_disable(scpd); |
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if (ret < 0) |
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goto out; |
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|
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return 0; |
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|
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out: |
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dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name); |
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|
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return ret; |
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} |
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static void init_clks(struct platform_device *pdev, struct clk **clk) |
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{ |
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int i; |
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|
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for (i = CLK_NONE + 1; i < CLK_MAX; i++) |
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clk[i] = devm_clk_get(&pdev->dev, clk_names[i]); |
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} |
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|
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static struct scp *init_scp(struct platform_device *pdev, |
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const struct scp_domain_data *scp_domain_data, int num, |
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const struct scp_ctrl_reg *scp_ctrl_reg, |
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bool bus_prot_reg_update) |
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{ |
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struct genpd_onecell_data *pd_data; |
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struct resource *res; |
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int i, j; |
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struct scp *scp; |
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struct clk *clk[CLK_MAX]; |
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|
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scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); |
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if (!scp) |
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return ERR_PTR(-ENOMEM); |
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|
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scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs; |
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scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs; |
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|
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scp->bus_prot_reg_update = bus_prot_reg_update; |
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|
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scp->dev = &pdev->dev; |
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|
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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scp->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(scp->base)) |
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return ERR_CAST(scp->base); |
|
|
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scp->domains = devm_kcalloc(&pdev->dev, |
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num, sizeof(*scp->domains), GFP_KERNEL); |
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if (!scp->domains) |
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return ERR_PTR(-ENOMEM); |
|
|
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pd_data = &scp->pd_data; |
|
|
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pd_data->domains = devm_kcalloc(&pdev->dev, |
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num, sizeof(*pd_data->domains), GFP_KERNEL); |
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if (!pd_data->domains) |
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return ERR_PTR(-ENOMEM); |
|
|
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scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
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"infracfg"); |
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if (IS_ERR(scp->infracfg)) { |
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dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n", |
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PTR_ERR(scp->infracfg)); |
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return ERR_CAST(scp->infracfg); |
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} |
|
|
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for (i = 0; i < num; i++) { |
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struct scp_domain *scpd = &scp->domains[i]; |
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const struct scp_domain_data *data = &scp_domain_data[i]; |
|
|
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scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name); |
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if (IS_ERR(scpd->supply)) { |
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if (PTR_ERR(scpd->supply) == -ENODEV) |
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scpd->supply = NULL; |
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else |
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return ERR_CAST(scpd->supply); |
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} |
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} |
|
|
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pd_data->num_domains = num; |
|
|
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init_clks(pdev, clk); |
|
|
|
for (i = 0; i < num; i++) { |
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struct scp_domain *scpd = &scp->domains[i]; |
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struct generic_pm_domain *genpd = &scpd->genpd; |
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const struct scp_domain_data *data = &scp_domain_data[i]; |
|
|
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pd_data->domains[i] = genpd; |
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scpd->scp = scp; |
|
|
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scpd->data = data; |
|
|
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for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { |
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struct clk *c = clk[data->clk_id[j]]; |
|
|
|
if (IS_ERR(c)) { |
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dev_err(&pdev->dev, "%s: clk unavailable\n", |
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data->name); |
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return ERR_CAST(c); |
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} |
|
|
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scpd->clk[j] = c; |
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} |
|
|
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genpd->name = data->name; |
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genpd->power_off = scpsys_power_off; |
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genpd->power_on = scpsys_power_on; |
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if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP)) |
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genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP; |
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} |
|
|
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return scp; |
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} |
|
|
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static void mtk_register_power_domains(struct platform_device *pdev, |
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struct scp *scp, int num) |
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{ |
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struct genpd_onecell_data *pd_data; |
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int i, ret; |
|
|
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for (i = 0; i < num; i++) { |
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struct scp_domain *scpd = &scp->domains[i]; |
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struct generic_pm_domain *genpd = &scpd->genpd; |
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bool on; |
|
|
|
/* |
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* Initially turn on all domains to make the domains usable |
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* with !CONFIG_PM and to get the hardware in sync with the |
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* software. The unused domains will be switched off during |
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* late_init time. |
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*/ |
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on = !WARN_ON(genpd->power_on(genpd) < 0); |
|
|
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pm_genpd_init(genpd, NULL, !on); |
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} |
|
|
|
/* |
|
* We are not allowed to fail here since there is no way to unregister |
|
* a power domain. Once registered above we have to keep the domains |
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* valid. |
|
*/ |
|
|
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pd_data = &scp->pd_data; |
|
|
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ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data); |
|
if (ret) |
|
dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret); |
|
} |
|
|
|
/* |
|
* MT2701 power domain support |
|
*/ |
|
|
|
static const struct scp_domain_data scp_domain_data_mt2701[] = { |
|
[MT2701_POWER_DOMAIN_CONN] = { |
|
.name = "conn", |
|
.sta_mask = PWR_STATUS_CONN, |
|
.ctl_offs = SPM_CONN_PWR_CON, |
|
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | |
|
MT2701_TOP_AXI_PROT_EN_CONN_S, |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_DISP] = { |
|
.name = "disp", |
|
.sta_mask = PWR_STATUS_DISP, |
|
.ctl_offs = SPM_DIS_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.clk_id = {CLK_MM}, |
|
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_MFG] = { |
|
.name = "mfg", |
|
.sta_mask = PWR_STATUS_MFG, |
|
.ctl_offs = SPM_MFG_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MFG}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_VDEC] = { |
|
.name = "vdec", |
|
.sta_mask = PWR_STATUS_VDEC, |
|
.ctl_offs = SPM_VDE_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_ISP] = { |
|
.name = "isp", |
|
.sta_mask = PWR_STATUS_ISP, |
|
.ctl_offs = SPM_ISP_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(13, 12), |
|
.clk_id = {CLK_MM}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_BDP] = { |
|
.name = "bdp", |
|
.sta_mask = PWR_STATUS_BDP, |
|
.ctl_offs = SPM_BDP_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_ETH] = { |
|
.name = "eth", |
|
.sta_mask = PWR_STATUS_ETH, |
|
.ctl_offs = SPM_ETH_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_ETHIF}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_HIF] = { |
|
.name = "hif", |
|
.sta_mask = PWR_STATUS_HIF, |
|
.ctl_offs = SPM_HIF_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_ETHIF}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2701_POWER_DOMAIN_IFR_MSC] = { |
|
.name = "ifr_msc", |
|
.sta_mask = PWR_STATUS_IFR_MSC, |
|
.ctl_offs = SPM_IFR_MSC_PWR_CON, |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
}; |
|
|
|
/* |
|
* MT2712 power domain support |
|
*/ |
|
static const struct scp_domain_data scp_domain_data_mt2712[] = { |
|
[MT2712_POWER_DOMAIN_MM] = { |
|
.name = "mm", |
|
.sta_mask = PWR_STATUS_DISP, |
|
.ctl_offs = SPM_DIS_PWR_CON, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_VDEC] = { |
|
.name = "vdec", |
|
.sta_mask = PWR_STATUS_VDEC, |
|
.ctl_offs = SPM_VDE_PWR_CON, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM, CLK_VDEC}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_VENC] = { |
|
.name = "venc", |
|
.sta_mask = PWR_STATUS_VENC, |
|
.ctl_offs = SPM_VEN_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_ISP] = { |
|
.name = "isp", |
|
.sta_mask = PWR_STATUS_ISP, |
|
.ctl_offs = SPM_ISP_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(13, 12), |
|
.clk_id = {CLK_MM}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_AUDIO] = { |
|
.name = "audio", |
|
.sta_mask = PWR_STATUS_AUDIO, |
|
.ctl_offs = SPM_AUDIO_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_AUDIO}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_USB] = { |
|
.name = "usb", |
|
.sta_mask = PWR_STATUS_USB, |
|
.ctl_offs = SPM_USB_PWR_CON, |
|
.sram_pdn_bits = GENMASK(10, 8), |
|
.sram_pdn_ack_bits = GENMASK(14, 12), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_USB2] = { |
|
.name = "usb2", |
|
.sta_mask = PWR_STATUS_USB2, |
|
.ctl_offs = SPM_USB2_PWR_CON, |
|
.sram_pdn_bits = GENMASK(10, 8), |
|
.sram_pdn_ack_bits = GENMASK(14, 12), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_MFG] = { |
|
.name = "mfg", |
|
.sta_mask = PWR_STATUS_MFG, |
|
.ctl_offs = SPM_MFG_PWR_CON, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(16, 16), |
|
.clk_id = {CLK_MFG}, |
|
.bus_prot_mask = BIT(14) | BIT(21) | BIT(23), |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_MFG_SC1] = { |
|
.name = "mfg_sc1", |
|
.sta_mask = BIT(22), |
|
.ctl_offs = 0x02c0, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(16, 16), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_MFG_SC2] = { |
|
.name = "mfg_sc2", |
|
.sta_mask = BIT(23), |
|
.ctl_offs = 0x02c4, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(16, 16), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT2712_POWER_DOMAIN_MFG_SC3] = { |
|
.name = "mfg_sc3", |
|
.sta_mask = BIT(30), |
|
.ctl_offs = 0x01f8, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(16, 16), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
}; |
|
|
|
static const struct scp_subdomain scp_subdomain_mt2712[] = { |
|
{MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC}, |
|
{MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC}, |
|
{MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP}, |
|
{MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1}, |
|
{MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2}, |
|
{MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, |
|
}; |
|
|
|
/* |
|
* MT6797 power domain support |
|
*/ |
|
|
|
static const struct scp_domain_data scp_domain_data_mt6797[] = { |
|
[MT6797_POWER_DOMAIN_VDEC] = { |
|
.name = "vdec", |
|
.sta_mask = BIT(7), |
|
.ctl_offs = 0x300, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_VDEC}, |
|
}, |
|
[MT6797_POWER_DOMAIN_VENC] = { |
|
.name = "venc", |
|
.sta_mask = BIT(21), |
|
.ctl_offs = 0x304, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
[MT6797_POWER_DOMAIN_ISP] = { |
|
.name = "isp", |
|
.sta_mask = BIT(5), |
|
.ctl_offs = 0x308, |
|
.sram_pdn_bits = GENMASK(9, 8), |
|
.sram_pdn_ack_bits = GENMASK(13, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
[MT6797_POWER_DOMAIN_MM] = { |
|
.name = "mm", |
|
.sta_mask = BIT(3), |
|
.ctl_offs = 0x30C, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM}, |
|
.bus_prot_mask = (BIT(1) | BIT(2)), |
|
}, |
|
[MT6797_POWER_DOMAIN_AUDIO] = { |
|
.name = "audio", |
|
.sta_mask = BIT(24), |
|
.ctl_offs = 0x314, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
[MT6797_POWER_DOMAIN_MFG_ASYNC] = { |
|
.name = "mfg_async", |
|
.sta_mask = BIT(13), |
|
.ctl_offs = 0x334, |
|
.sram_pdn_bits = 0, |
|
.sram_pdn_ack_bits = 0, |
|
.clk_id = {CLK_MFG}, |
|
}, |
|
[MT6797_POWER_DOMAIN_MJC] = { |
|
.name = "mjc", |
|
.sta_mask = BIT(20), |
|
.ctl_offs = 0x310, |
|
.sram_pdn_bits = GENMASK(8, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
}; |
|
|
|
#define SPM_PWR_STATUS_MT6797 0x0180 |
|
#define SPM_PWR_STATUS_2ND_MT6797 0x0184 |
|
|
|
static const struct scp_subdomain scp_subdomain_mt6797[] = { |
|
{MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VDEC}, |
|
{MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_ISP}, |
|
{MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VENC}, |
|
{MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_MJC}, |
|
}; |
|
|
|
/* |
|
* MT7622 power domain support |
|
*/ |
|
|
|
static const struct scp_domain_data scp_domain_data_mt7622[] = { |
|
[MT7622_POWER_DOMAIN_ETHSYS] = { |
|
.name = "ethsys", |
|
.sta_mask = PWR_STATUS_ETHSYS, |
|
.ctl_offs = SPM_ETHSYS_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_NONE}, |
|
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7622_POWER_DOMAIN_HIF0] = { |
|
.name = "hif0", |
|
.sta_mask = PWR_STATUS_HIF0, |
|
.ctl_offs = SPM_HIF0_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_HIFSEL}, |
|
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7622_POWER_DOMAIN_HIF1] = { |
|
.name = "hif1", |
|
.sta_mask = PWR_STATUS_HIF1, |
|
.ctl_offs = SPM_HIF1_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_HIFSEL}, |
|
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7622_POWER_DOMAIN_WB] = { |
|
.name = "wb", |
|
.sta_mask = PWR_STATUS_WB, |
|
.ctl_offs = SPM_WB_PWR_CON, |
|
.sram_pdn_bits = 0, |
|
.sram_pdn_ack_bits = 0, |
|
.clk_id = {CLK_NONE}, |
|
.bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM, |
|
}, |
|
}; |
|
|
|
/* |
|
* MT7623A power domain support |
|
*/ |
|
|
|
static const struct scp_domain_data scp_domain_data_mt7623a[] = { |
|
[MT7623A_POWER_DOMAIN_CONN] = { |
|
.name = "conn", |
|
.sta_mask = PWR_STATUS_CONN, |
|
.ctl_offs = SPM_CONN_PWR_CON, |
|
.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | |
|
MT2701_TOP_AXI_PROT_EN_CONN_S, |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7623A_POWER_DOMAIN_ETH] = { |
|
.name = "eth", |
|
.sta_mask = PWR_STATUS_ETH, |
|
.ctl_offs = SPM_ETH_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_ETHIF}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7623A_POWER_DOMAIN_HIF] = { |
|
.name = "hif", |
|
.sta_mask = PWR_STATUS_HIF, |
|
.ctl_offs = SPM_HIF_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_ETHIF}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT7623A_POWER_DOMAIN_IFR_MSC] = { |
|
.name = "ifr_msc", |
|
.sta_mask = PWR_STATUS_IFR_MSC, |
|
.ctl_offs = SPM_IFR_MSC_PWR_CON, |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
}; |
|
|
|
/* |
|
* MT8173 power domain support |
|
*/ |
|
|
|
static const struct scp_domain_data scp_domain_data_mt8173[] = { |
|
[MT8173_POWER_DOMAIN_VDEC] = { |
|
.name = "vdec", |
|
.sta_mask = PWR_STATUS_VDEC, |
|
.ctl_offs = SPM_VDE_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM}, |
|
}, |
|
[MT8173_POWER_DOMAIN_VENC] = { |
|
.name = "venc", |
|
.sta_mask = PWR_STATUS_VENC, |
|
.ctl_offs = SPM_VEN_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_MM, CLK_VENC}, |
|
}, |
|
[MT8173_POWER_DOMAIN_ISP] = { |
|
.name = "isp", |
|
.sta_mask = PWR_STATUS_ISP, |
|
.ctl_offs = SPM_ISP_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(13, 12), |
|
.clk_id = {CLK_MM}, |
|
}, |
|
[MT8173_POWER_DOMAIN_MM] = { |
|
.name = "mm", |
|
.sta_mask = PWR_STATUS_DISP, |
|
.ctl_offs = SPM_DIS_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(12, 12), |
|
.clk_id = {CLK_MM}, |
|
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | |
|
MT8173_TOP_AXI_PROT_EN_MM_M1, |
|
}, |
|
[MT8173_POWER_DOMAIN_VENC_LT] = { |
|
.name = "venc_lt", |
|
.sta_mask = PWR_STATUS_VENC_LT, |
|
.ctl_offs = SPM_VEN2_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_MM, CLK_VENC_LT}, |
|
}, |
|
[MT8173_POWER_DOMAIN_AUDIO] = { |
|
.name = "audio", |
|
.sta_mask = PWR_STATUS_AUDIO, |
|
.ctl_offs = SPM_AUDIO_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
[MT8173_POWER_DOMAIN_USB] = { |
|
.name = "usb", |
|
.sta_mask = PWR_STATUS_USB, |
|
.ctl_offs = SPM_USB_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(15, 12), |
|
.clk_id = {CLK_NONE}, |
|
.caps = MTK_SCPD_ACTIVE_WAKEUP, |
|
}, |
|
[MT8173_POWER_DOMAIN_MFG_ASYNC] = { |
|
.name = "mfg_async", |
|
.sta_mask = PWR_STATUS_MFG_ASYNC, |
|
.ctl_offs = SPM_MFG_ASYNC_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = 0, |
|
.clk_id = {CLK_MFG}, |
|
}, |
|
[MT8173_POWER_DOMAIN_MFG_2D] = { |
|
.name = "mfg_2d", |
|
.sta_mask = PWR_STATUS_MFG_2D, |
|
.ctl_offs = SPM_MFG_2D_PWR_CON, |
|
.sram_pdn_bits = GENMASK(11, 8), |
|
.sram_pdn_ack_bits = GENMASK(13, 12), |
|
.clk_id = {CLK_NONE}, |
|
}, |
|
[MT8173_POWER_DOMAIN_MFG] = { |
|
.name = "mfg", |
|
.sta_mask = PWR_STATUS_MFG, |
|
.ctl_offs = SPM_MFG_PWR_CON, |
|
.sram_pdn_bits = GENMASK(13, 8), |
|
.sram_pdn_ack_bits = GENMASK(21, 16), |
|
.clk_id = {CLK_NONE}, |
|
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | |
|
MT8173_TOP_AXI_PROT_EN_MFG_M0 | |
|
MT8173_TOP_AXI_PROT_EN_MFG_M1 | |
|
MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, |
|
}, |
|
}; |
|
|
|
static const struct scp_subdomain scp_subdomain_mt8173[] = { |
|
{MT8173_POWER_DOMAIN_MFG_ASYNC, MT8173_POWER_DOMAIN_MFG_2D}, |
|
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, |
|
}; |
|
|
|
static const struct scp_soc_data mt2701_data = { |
|
.domains = scp_domain_data_mt2701, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
|
}, |
|
.bus_prot_reg_update = true, |
|
}; |
|
|
|
static const struct scp_soc_data mt2712_data = { |
|
.domains = scp_domain_data_mt2712, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt2712), |
|
.subdomains = scp_subdomain_mt2712, |
|
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
|
}, |
|
.bus_prot_reg_update = false, |
|
}; |
|
|
|
static const struct scp_soc_data mt6797_data = { |
|
.domains = scp_domain_data_mt6797, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797), |
|
.subdomains = scp_subdomain_mt6797, |
|
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS_MT6797, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797 |
|
}, |
|
.bus_prot_reg_update = true, |
|
}; |
|
|
|
static const struct scp_soc_data mt7622_data = { |
|
.domains = scp_domain_data_mt7622, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt7622), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
|
}, |
|
.bus_prot_reg_update = true, |
|
}; |
|
|
|
static const struct scp_soc_data mt7623a_data = { |
|
.domains = scp_domain_data_mt7623a, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt7623a), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
|
}, |
|
.bus_prot_reg_update = true, |
|
}; |
|
|
|
static const struct scp_soc_data mt8173_data = { |
|
.domains = scp_domain_data_mt8173, |
|
.num_domains = ARRAY_SIZE(scp_domain_data_mt8173), |
|
.subdomains = scp_subdomain_mt8173, |
|
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173), |
|
.regs = { |
|
.pwr_sta_offs = SPM_PWR_STATUS, |
|
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND |
|
}, |
|
.bus_prot_reg_update = true, |
|
}; |
|
|
|
/* |
|
* scpsys driver init |
|
*/ |
|
|
|
static const struct of_device_id of_scpsys_match_tbl[] = { |
|
{ |
|
.compatible = "mediatek,mt2701-scpsys", |
|
.data = &mt2701_data, |
|
}, { |
|
.compatible = "mediatek,mt2712-scpsys", |
|
.data = &mt2712_data, |
|
}, { |
|
.compatible = "mediatek,mt6797-scpsys", |
|
.data = &mt6797_data, |
|
}, { |
|
.compatible = "mediatek,mt7622-scpsys", |
|
.data = &mt7622_data, |
|
}, { |
|
.compatible = "mediatek,mt7623a-scpsys", |
|
.data = &mt7623a_data, |
|
}, { |
|
.compatible = "mediatek,mt8173-scpsys", |
|
.data = &mt8173_data, |
|
}, { |
|
/* sentinel */ |
|
} |
|
}; |
|
|
|
static int scpsys_probe(struct platform_device *pdev) |
|
{ |
|
const struct scp_subdomain *sd; |
|
const struct scp_soc_data *soc; |
|
struct scp *scp; |
|
struct genpd_onecell_data *pd_data; |
|
int i, ret; |
|
|
|
soc = of_device_get_match_data(&pdev->dev); |
|
|
|
scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs, |
|
soc->bus_prot_reg_update); |
|
if (IS_ERR(scp)) |
|
return PTR_ERR(scp); |
|
|
|
mtk_register_power_domains(pdev, scp, soc->num_domains); |
|
|
|
pd_data = &scp->pd_data; |
|
|
|
for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) { |
|
ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin], |
|
pd_data->domains[sd->subdomain]); |
|
if (ret && IS_ENABLED(CONFIG_PM)) |
|
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", |
|
ret); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver scpsys_drv = { |
|
.probe = scpsys_probe, |
|
.driver = { |
|
.name = "mtk-scpsys", |
|
.suppress_bind_attrs = true, |
|
.owner = THIS_MODULE, |
|
.of_match_table = of_match_ptr(of_scpsys_match_tbl), |
|
}, |
|
}; |
|
builtin_platform_driver(scpsys_drv);
|
|
|