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542 lines
14 KiB
542 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* wm8350-irq.c -- IRQ support for Wolfson WM8350 |
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* |
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* Copyright 2007, 2008, 2009 Wolfson Microelectronics PLC. |
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* |
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* Author: Liam Girdwood, Mark Brown |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/bug.h> |
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#include <linux/device.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/mfd/wm8350/core.h> |
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#include <linux/mfd/wm8350/audio.h> |
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#include <linux/mfd/wm8350/comparator.h> |
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#include <linux/mfd/wm8350/gpio.h> |
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#include <linux/mfd/wm8350/pmic.h> |
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#include <linux/mfd/wm8350/rtc.h> |
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#include <linux/mfd/wm8350/supply.h> |
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#include <linux/mfd/wm8350/wdt.h> |
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#define WM8350_INT_OFFSET_1 0 |
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#define WM8350_INT_OFFSET_2 1 |
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#define WM8350_POWER_UP_INT_OFFSET 2 |
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#define WM8350_UNDER_VOLTAGE_INT_OFFSET 3 |
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#define WM8350_OVER_CURRENT_INT_OFFSET 4 |
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#define WM8350_GPIO_INT_OFFSET 5 |
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#define WM8350_COMPARATOR_INT_OFFSET 6 |
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struct wm8350_irq_data { |
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int primary; |
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int reg; |
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int mask; |
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int primary_only; |
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}; |
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static struct wm8350_irq_data wm8350_irqs[] = { |
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[WM8350_IRQ_OC_LS] = { |
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.primary = WM8350_OC_INT, |
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.reg = WM8350_OVER_CURRENT_INT_OFFSET, |
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.mask = WM8350_OC_LS_EINT, |
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.primary_only = 1, |
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}, |
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[WM8350_IRQ_UV_DC1] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC1_EINT, |
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}, |
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[WM8350_IRQ_UV_DC2] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC2_EINT, |
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}, |
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[WM8350_IRQ_UV_DC3] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC3_EINT, |
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}, |
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[WM8350_IRQ_UV_DC4] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC4_EINT, |
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}, |
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[WM8350_IRQ_UV_DC5] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC5_EINT, |
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}, |
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[WM8350_IRQ_UV_DC6] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_DC6_EINT, |
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}, |
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[WM8350_IRQ_UV_LDO1] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_LDO1_EINT, |
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}, |
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[WM8350_IRQ_UV_LDO2] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_LDO2_EINT, |
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}, |
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[WM8350_IRQ_UV_LDO3] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_LDO3_EINT, |
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}, |
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[WM8350_IRQ_UV_LDO4] = { |
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.primary = WM8350_UV_INT, |
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.reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, |
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.mask = WM8350_UV_LDO4_EINT, |
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}, |
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[WM8350_IRQ_CHG_BAT_HOT] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_BAT_HOT_EINT, |
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}, |
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[WM8350_IRQ_CHG_BAT_COLD] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_BAT_COLD_EINT, |
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}, |
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[WM8350_IRQ_CHG_BAT_FAIL] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_BAT_FAIL_EINT, |
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}, |
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[WM8350_IRQ_CHG_TO] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_TO_EINT, |
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}, |
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[WM8350_IRQ_CHG_END] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_END_EINT, |
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}, |
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[WM8350_IRQ_CHG_START] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_START_EINT, |
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}, |
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[WM8350_IRQ_CHG_FAST_RDY] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_FAST_RDY_EINT, |
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}, |
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[WM8350_IRQ_CHG_VBATT_LT_3P9] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_VBATT_LT_3P9_EINT, |
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}, |
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[WM8350_IRQ_CHG_VBATT_LT_3P1] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_VBATT_LT_3P1_EINT, |
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}, |
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[WM8350_IRQ_CHG_VBATT_LT_2P85] = { |
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.primary = WM8350_CHG_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_CHG_VBATT_LT_2P85_EINT, |
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}, |
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[WM8350_IRQ_RTC_ALM] = { |
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.primary = WM8350_RTC_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_RTC_ALM_EINT, |
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}, |
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[WM8350_IRQ_RTC_SEC] = { |
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.primary = WM8350_RTC_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_RTC_SEC_EINT, |
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}, |
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[WM8350_IRQ_RTC_PER] = { |
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.primary = WM8350_RTC_INT, |
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.reg = WM8350_INT_OFFSET_1, |
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.mask = WM8350_RTC_PER_EINT, |
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}, |
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[WM8350_IRQ_CS1] = { |
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.primary = WM8350_CS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_CS1_EINT, |
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}, |
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[WM8350_IRQ_CS2] = { |
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.primary = WM8350_CS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_CS2_EINT, |
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}, |
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[WM8350_IRQ_SYS_HYST_COMP_FAIL] = { |
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.primary = WM8350_SYS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_SYS_HYST_COMP_FAIL_EINT, |
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}, |
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[WM8350_IRQ_SYS_CHIP_GT115] = { |
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.primary = WM8350_SYS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_SYS_CHIP_GT115_EINT, |
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}, |
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[WM8350_IRQ_SYS_CHIP_GT140] = { |
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.primary = WM8350_SYS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_SYS_CHIP_GT140_EINT, |
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}, |
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[WM8350_IRQ_SYS_WDOG_TO] = { |
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.primary = WM8350_SYS_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_SYS_WDOG_TO_EINT, |
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}, |
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[WM8350_IRQ_AUXADC_DATARDY] = { |
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.primary = WM8350_AUXADC_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_AUXADC_DATARDY_EINT, |
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}, |
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[WM8350_IRQ_AUXADC_DCOMP4] = { |
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.primary = WM8350_AUXADC_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_AUXADC_DCOMP4_EINT, |
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}, |
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[WM8350_IRQ_AUXADC_DCOMP3] = { |
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.primary = WM8350_AUXADC_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_AUXADC_DCOMP3_EINT, |
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}, |
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[WM8350_IRQ_AUXADC_DCOMP2] = { |
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.primary = WM8350_AUXADC_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_AUXADC_DCOMP2_EINT, |
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}, |
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[WM8350_IRQ_AUXADC_DCOMP1] = { |
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.primary = WM8350_AUXADC_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_AUXADC_DCOMP1_EINT, |
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}, |
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[WM8350_IRQ_USB_LIMIT] = { |
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.primary = WM8350_USB_INT, |
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.reg = WM8350_INT_OFFSET_2, |
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.mask = WM8350_USB_LIMIT_EINT, |
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.primary_only = 1, |
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}, |
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[WM8350_IRQ_WKUP_OFF_STATE] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_OFF_STATE_EINT, |
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}, |
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[WM8350_IRQ_WKUP_HIB_STATE] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_HIB_STATE_EINT, |
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}, |
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[WM8350_IRQ_WKUP_CONV_FAULT] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_CONV_FAULT_EINT, |
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}, |
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[WM8350_IRQ_WKUP_WDOG_RST] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_WDOG_RST_EINT, |
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}, |
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[WM8350_IRQ_WKUP_GP_PWR_ON] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_GP_PWR_ON_EINT, |
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}, |
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[WM8350_IRQ_WKUP_ONKEY] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_ONKEY_EINT, |
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}, |
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[WM8350_IRQ_WKUP_GP_WAKEUP] = { |
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.primary = WM8350_WKUP_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_WKUP_GP_WAKEUP_EINT, |
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}, |
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[WM8350_IRQ_CODEC_JCK_DET_L] = { |
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.primary = WM8350_CODEC_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_CODEC_JCK_DET_L_EINT, |
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}, |
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[WM8350_IRQ_CODEC_JCK_DET_R] = { |
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.primary = WM8350_CODEC_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_CODEC_JCK_DET_R_EINT, |
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}, |
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[WM8350_IRQ_CODEC_MICSCD] = { |
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.primary = WM8350_CODEC_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_CODEC_MICSCD_EINT, |
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}, |
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[WM8350_IRQ_CODEC_MICD] = { |
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.primary = WM8350_CODEC_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_CODEC_MICD_EINT, |
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}, |
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[WM8350_IRQ_EXT_USB_FB] = { |
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.primary = WM8350_EXT_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_EXT_USB_FB_EINT, |
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}, |
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[WM8350_IRQ_EXT_WALL_FB] = { |
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.primary = WM8350_EXT_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_EXT_WALL_FB_EINT, |
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}, |
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[WM8350_IRQ_EXT_BAT_FB] = { |
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.primary = WM8350_EXT_INT, |
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.reg = WM8350_COMPARATOR_INT_OFFSET, |
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.mask = WM8350_EXT_BAT_FB_EINT, |
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}, |
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[WM8350_IRQ_GPIO(0)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP0_EINT, |
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}, |
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[WM8350_IRQ_GPIO(1)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP1_EINT, |
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}, |
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[WM8350_IRQ_GPIO(2)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP2_EINT, |
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}, |
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[WM8350_IRQ_GPIO(3)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP3_EINT, |
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}, |
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[WM8350_IRQ_GPIO(4)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP4_EINT, |
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}, |
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[WM8350_IRQ_GPIO(5)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP5_EINT, |
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}, |
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[WM8350_IRQ_GPIO(6)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP6_EINT, |
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}, |
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[WM8350_IRQ_GPIO(7)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP7_EINT, |
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}, |
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[WM8350_IRQ_GPIO(8)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP8_EINT, |
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}, |
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[WM8350_IRQ_GPIO(9)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP9_EINT, |
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}, |
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[WM8350_IRQ_GPIO(10)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP10_EINT, |
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}, |
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[WM8350_IRQ_GPIO(11)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP11_EINT, |
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}, |
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[WM8350_IRQ_GPIO(12)] = { |
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.primary = WM8350_GP_INT, |
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.reg = WM8350_GPIO_INT_OFFSET, |
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.mask = WM8350_GP12_EINT, |
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}, |
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}; |
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static inline struct wm8350_irq_data *irq_to_wm8350_irq(struct wm8350 *wm8350, |
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int irq) |
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{ |
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return &wm8350_irqs[irq - wm8350->irq_base]; |
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} |
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/* |
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* This is a threaded IRQ handler so can access I2C/SPI. Since all |
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* interrupts are clear on read the IRQ line will be reasserted and |
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* the physical IRQ will be handled again if another interrupt is |
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* asserted while we run - in the normal course of events this is a |
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* rare occurrence so we save I2C/SPI reads. We're also assuming that |
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* it's rare to get lots of interrupts firing simultaneously so try to |
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* minimise I/O. |
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*/ |
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static irqreturn_t wm8350_irq(int irq, void *irq_data) |
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{ |
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struct wm8350 *wm8350 = irq_data; |
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u16 level_one; |
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u16 sub_reg[WM8350_NUM_IRQ_REGS]; |
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int read_done[WM8350_NUM_IRQ_REGS]; |
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struct wm8350_irq_data *data; |
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int i; |
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level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS) |
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& ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK); |
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if (!level_one) |
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return IRQ_NONE; |
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memset(&read_done, 0, sizeof(read_done)); |
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for (i = 0; i < ARRAY_SIZE(wm8350_irqs); i++) { |
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data = &wm8350_irqs[i]; |
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if (!(level_one & data->primary)) |
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continue; |
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if (!read_done[data->reg]) { |
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sub_reg[data->reg] = |
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wm8350_reg_read(wm8350, WM8350_INT_STATUS_1 + |
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data->reg); |
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sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg]; |
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read_done[data->reg] = 1; |
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} |
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if (sub_reg[data->reg] & data->mask) |
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handle_nested_irq(wm8350->irq_base + i); |
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} |
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return IRQ_HANDLED; |
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} |
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static void wm8350_irq_lock(struct irq_data *data) |
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{ |
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struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data); |
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mutex_lock(&wm8350->irq_lock); |
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} |
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static void wm8350_irq_sync_unlock(struct irq_data *data) |
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{ |
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struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data); |
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int i; |
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for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) { |
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/* If there's been a change in the mask write it back |
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* to the hardware. */ |
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WARN_ON(regmap_update_bits(wm8350->regmap, |
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WM8350_INT_STATUS_1_MASK + i, |
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0xffff, wm8350->irq_masks[i])); |
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} |
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mutex_unlock(&wm8350->irq_lock); |
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} |
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static void wm8350_irq_enable(struct irq_data *data) |
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{ |
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struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data); |
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struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350, |
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data->irq); |
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wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; |
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} |
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|
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static void wm8350_irq_disable(struct irq_data *data) |
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{ |
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struct wm8350 *wm8350 = irq_data_get_irq_chip_data(data); |
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struct wm8350_irq_data *irq_data = irq_to_wm8350_irq(wm8350, |
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data->irq); |
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wm8350->irq_masks[irq_data->reg] |= irq_data->mask; |
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} |
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static struct irq_chip wm8350_irq_chip = { |
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.name = "wm8350", |
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.irq_bus_lock = wm8350_irq_lock, |
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.irq_bus_sync_unlock = wm8350_irq_sync_unlock, |
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.irq_disable = wm8350_irq_disable, |
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.irq_enable = wm8350_irq_enable, |
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}; |
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|
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int wm8350_irq_init(struct wm8350 *wm8350, int irq, |
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struct wm8350_platform_data *pdata) |
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{ |
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int ret, cur_irq, i; |
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int flags = IRQF_ONESHOT; |
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int irq_base = -1; |
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|
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if (!irq) { |
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dev_warn(wm8350->dev, "No interrupt support, no core IRQ\n"); |
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return 0; |
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} |
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|
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/* Mask top level interrupts */ |
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wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0xFFFF); |
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|
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/* Mask all individual interrupts by default and cache the |
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* masks. We read the masks back since there are unwritable |
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* bits in the mask registers. */ |
|
for (i = 0; i < ARRAY_SIZE(wm8350->irq_masks); i++) { |
|
wm8350_reg_write(wm8350, WM8350_INT_STATUS_1_MASK + i, |
|
0xFFFF); |
|
wm8350->irq_masks[i] = |
|
wm8350_reg_read(wm8350, |
|
WM8350_INT_STATUS_1_MASK + i); |
|
} |
|
|
|
mutex_init(&wm8350->irq_lock); |
|
wm8350->chip_irq = irq; |
|
|
|
if (pdata && pdata->irq_base > 0) |
|
irq_base = pdata->irq_base; |
|
|
|
wm8350->irq_base = |
|
irq_alloc_descs(irq_base, 0, ARRAY_SIZE(wm8350_irqs), 0); |
|
if (wm8350->irq_base < 0) { |
|
dev_warn(wm8350->dev, "Allocating irqs failed with %d\n", |
|
wm8350->irq_base); |
|
return 0; |
|
} |
|
|
|
if (pdata && pdata->irq_high) { |
|
flags |= IRQF_TRIGGER_HIGH; |
|
|
|
wm8350_set_bits(wm8350, WM8350_SYSTEM_CONTROL_1, |
|
WM8350_IRQ_POL); |
|
} else { |
|
flags |= IRQF_TRIGGER_LOW; |
|
|
|
wm8350_clear_bits(wm8350, WM8350_SYSTEM_CONTROL_1, |
|
WM8350_IRQ_POL); |
|
} |
|
|
|
/* Register with genirq */ |
|
for (cur_irq = wm8350->irq_base; |
|
cur_irq < ARRAY_SIZE(wm8350_irqs) + wm8350->irq_base; |
|
cur_irq++) { |
|
irq_set_chip_data(cur_irq, wm8350); |
|
irq_set_chip_and_handler(cur_irq, &wm8350_irq_chip, |
|
handle_edge_irq); |
|
irq_set_nested_thread(cur_irq, 1); |
|
|
|
irq_clear_status_flags(cur_irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
|
} |
|
|
|
ret = request_threaded_irq(irq, NULL, wm8350_irq, flags, |
|
"wm8350", wm8350); |
|
if (ret != 0) |
|
dev_err(wm8350->dev, "Failed to request IRQ: %d\n", ret); |
|
|
|
/* Allow interrupts to fire */ |
|
wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0); |
|
|
|
return ret; |
|
} |
|
|
|
int wm8350_irq_exit(struct wm8350 *wm8350) |
|
{ |
|
free_irq(wm8350->chip_irq, wm8350); |
|
return 0; |
|
}
|
|
|