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487 lines
12 KiB
487 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Rockchip Successive Approximation Register (SAR) A/D Converter |
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* Copyright (C) 2014 ROCKCHIP, Inc. |
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*/ |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/reset.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_buffer.h> |
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#define SARADC_DATA 0x00 |
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#define SARADC_STAS 0x04 |
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#define SARADC_STAS_BUSY BIT(0) |
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#define SARADC_CTRL 0x08 |
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#define SARADC_CTRL_IRQ_STATUS BIT(6) |
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#define SARADC_CTRL_IRQ_ENABLE BIT(5) |
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#define SARADC_CTRL_POWER_CTRL BIT(3) |
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#define SARADC_CTRL_CHN_MASK 0x7 |
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#define SARADC_DLY_PU_SOC 0x0c |
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#define SARADC_DLY_PU_SOC_MASK 0x3f |
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#define SARADC_TIMEOUT msecs_to_jiffies(100) |
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#define SARADC_MAX_CHANNELS 6 |
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struct rockchip_saradc_data { |
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const struct iio_chan_spec *channels; |
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int num_channels; |
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unsigned long clk_rate; |
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}; |
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struct rockchip_saradc { |
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void __iomem *regs; |
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struct clk *pclk; |
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struct clk *clk; |
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struct completion completion; |
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struct regulator *vref; |
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struct reset_control *reset; |
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const struct rockchip_saradc_data *data; |
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u16 last_val; |
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const struct iio_chan_spec *last_chan; |
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}; |
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static void rockchip_saradc_power_down(struct rockchip_saradc *info) |
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{ |
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/* Clear irq & power down adc */ |
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writel_relaxed(0, info->regs + SARADC_CTRL); |
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} |
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static int rockchip_saradc_conversion(struct rockchip_saradc *info, |
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struct iio_chan_spec const *chan) |
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{ |
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reinit_completion(&info->completion); |
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/* 8 clock periods as delay between power up and start cmd */ |
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writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); |
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info->last_chan = chan; |
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/* Select the channel to be used and trigger conversion */ |
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writel(SARADC_CTRL_POWER_CTRL |
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| (chan->channel & SARADC_CTRL_CHN_MASK) |
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| SARADC_CTRL_IRQ_ENABLE, |
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info->regs + SARADC_CTRL); |
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if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, int *val2, long mask) |
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{ |
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struct rockchip_saradc *info = iio_priv(indio_dev); |
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int ret; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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mutex_lock(&indio_dev->mlock); |
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ret = rockchip_saradc_conversion(info, chan); |
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if (ret) { |
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rockchip_saradc_power_down(info); |
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mutex_unlock(&indio_dev->mlock); |
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return ret; |
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} |
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*val = info->last_val; |
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mutex_unlock(&indio_dev->mlock); |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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ret = regulator_get_voltage(info->vref); |
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if (ret < 0) { |
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dev_err(&indio_dev->dev, "failed to get voltage\n"); |
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return ret; |
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} |
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*val = ret / 1000; |
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*val2 = chan->scan_type.realbits; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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default: |
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return -EINVAL; |
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} |
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} |
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static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) |
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{ |
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struct rockchip_saradc *info = dev_id; |
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/* Read value */ |
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info->last_val = readl_relaxed(info->regs + SARADC_DATA); |
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info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); |
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rockchip_saradc_power_down(info); |
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complete(&info->completion); |
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return IRQ_HANDLED; |
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} |
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static const struct iio_info rockchip_saradc_iio_info = { |
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.read_raw = rockchip_saradc_read_raw, |
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}; |
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#define SARADC_CHANNEL(_index, _id, _res) { \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = _index, \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ |
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.datasheet_name = _id, \ |
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.scan_index = _index, \ |
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.scan_type = { \ |
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.sign = 'u', \ |
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.realbits = _res, \ |
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.storagebits = 16, \ |
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.endianness = IIO_CPU, \ |
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}, \ |
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} |
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static const struct iio_chan_spec rockchip_saradc_iio_channels[] = { |
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SARADC_CHANNEL(0, "adc0", 10), |
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SARADC_CHANNEL(1, "adc1", 10), |
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SARADC_CHANNEL(2, "adc2", 10), |
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}; |
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static const struct rockchip_saradc_data saradc_data = { |
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.channels = rockchip_saradc_iio_channels, |
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.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), |
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.clk_rate = 1000000, |
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}; |
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static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { |
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SARADC_CHANNEL(0, "adc0", 12), |
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SARADC_CHANNEL(1, "adc1", 12), |
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}; |
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static const struct rockchip_saradc_data rk3066_tsadc_data = { |
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.channels = rockchip_rk3066_tsadc_iio_channels, |
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.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), |
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.clk_rate = 50000, |
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}; |
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static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { |
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SARADC_CHANNEL(0, "adc0", 10), |
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SARADC_CHANNEL(1, "adc1", 10), |
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SARADC_CHANNEL(2, "adc2", 10), |
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SARADC_CHANNEL(3, "adc3", 10), |
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SARADC_CHANNEL(4, "adc4", 10), |
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SARADC_CHANNEL(5, "adc5", 10), |
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}; |
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static const struct rockchip_saradc_data rk3399_saradc_data = { |
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.channels = rockchip_rk3399_saradc_iio_channels, |
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.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), |
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.clk_rate = 1000000, |
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}; |
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static const struct of_device_id rockchip_saradc_match[] = { |
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{ |
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.compatible = "rockchip,saradc", |
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.data = &saradc_data, |
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}, { |
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.compatible = "rockchip,rk3066-tsadc", |
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.data = &rk3066_tsadc_data, |
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}, { |
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.compatible = "rockchip,rk3399-saradc", |
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.data = &rk3399_saradc_data, |
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}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, rockchip_saradc_match); |
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/* |
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* Reset SARADC Controller. |
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*/ |
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static void rockchip_saradc_reset_controller(struct reset_control *reset) |
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{ |
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reset_control_assert(reset); |
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usleep_range(10, 20); |
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reset_control_deassert(reset); |
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} |
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static void rockchip_saradc_clk_disable(void *data) |
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{ |
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struct rockchip_saradc *info = data; |
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clk_disable_unprepare(info->clk); |
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} |
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static void rockchip_saradc_pclk_disable(void *data) |
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{ |
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struct rockchip_saradc *info = data; |
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clk_disable_unprepare(info->pclk); |
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} |
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static void rockchip_saradc_regulator_disable(void *data) |
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{ |
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struct rockchip_saradc *info = data; |
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regulator_disable(info->vref); |
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} |
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static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) |
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{ |
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struct iio_poll_func *pf = p; |
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struct iio_dev *i_dev = pf->indio_dev; |
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struct rockchip_saradc *info = iio_priv(i_dev); |
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/* |
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* @values: each channel takes an u16 value |
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* @timestamp: will be 8-byte aligned automatically |
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*/ |
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struct { |
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u16 values[SARADC_MAX_CHANNELS]; |
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int64_t timestamp; |
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} data; |
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int ret; |
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int i, j = 0; |
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mutex_lock(&i_dev->mlock); |
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for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) { |
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const struct iio_chan_spec *chan = &i_dev->channels[i]; |
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ret = rockchip_saradc_conversion(info, chan); |
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if (ret) { |
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rockchip_saradc_power_down(info); |
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goto out; |
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} |
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data.values[j] = info->last_val; |
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j++; |
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} |
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iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev)); |
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out: |
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mutex_unlock(&i_dev->mlock); |
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iio_trigger_notify_done(i_dev->trig); |
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return IRQ_HANDLED; |
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} |
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static int rockchip_saradc_probe(struct platform_device *pdev) |
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{ |
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struct rockchip_saradc *info = NULL; |
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struct device_node *np = pdev->dev.of_node; |
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struct iio_dev *indio_dev = NULL; |
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struct resource *mem; |
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const struct of_device_id *match; |
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int ret; |
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int irq; |
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if (!np) |
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return -ENODEV; |
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); |
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if (!indio_dev) { |
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dev_err(&pdev->dev, "failed allocating iio device\n"); |
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return -ENOMEM; |
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} |
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info = iio_priv(indio_dev); |
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match = of_match_device(rockchip_saradc_match, &pdev->dev); |
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if (!match) { |
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dev_err(&pdev->dev, "failed to match device\n"); |
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return -ENODEV; |
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} |
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info->data = match->data; |
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/* Sanity check for possible later IP variants with more channels */ |
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if (info->data->num_channels > SARADC_MAX_CHANNELS) { |
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dev_err(&pdev->dev, "max channels exceeded"); |
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return -EINVAL; |
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} |
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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info->regs = devm_ioremap_resource(&pdev->dev, mem); |
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if (IS_ERR(info->regs)) |
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return PTR_ERR(info->regs); |
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/* |
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* The reset should be an optional property, as it should work |
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* with old devicetrees as well |
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*/ |
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info->reset = devm_reset_control_get_exclusive(&pdev->dev, |
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"saradc-apb"); |
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if (IS_ERR(info->reset)) { |
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ret = PTR_ERR(info->reset); |
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if (ret != -ENOENT) |
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return ret; |
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dev_dbg(&pdev->dev, "no reset control found\n"); |
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info->reset = NULL; |
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} |
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init_completion(&info->completion); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, |
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0, dev_name(&pdev->dev), info); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed requesting irq %d\n", irq); |
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return ret; |
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} |
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info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
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if (IS_ERR(info->pclk)) { |
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dev_err(&pdev->dev, "failed to get pclk\n"); |
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return PTR_ERR(info->pclk); |
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} |
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info->clk = devm_clk_get(&pdev->dev, "saradc"); |
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if (IS_ERR(info->clk)) { |
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dev_err(&pdev->dev, "failed to get adc clock\n"); |
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return PTR_ERR(info->clk); |
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} |
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info->vref = devm_regulator_get(&pdev->dev, "vref"); |
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if (IS_ERR(info->vref)) { |
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dev_err(&pdev->dev, "failed to get regulator, %ld\n", |
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PTR_ERR(info->vref)); |
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return PTR_ERR(info->vref); |
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} |
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if (info->reset) |
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rockchip_saradc_reset_controller(info->reset); |
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/* |
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* Use a default value for the converter clock. |
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* This may become user-configurable in the future. |
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*/ |
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ret = clk_set_rate(info->clk, info->data->clk_rate); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret); |
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return ret; |
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} |
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ret = regulator_enable(info->vref); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to enable vref regulator\n"); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(&pdev->dev, |
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rockchip_saradc_regulator_disable, info); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to register devm action, %d\n", |
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ret); |
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return ret; |
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} |
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ret = clk_prepare_enable(info->pclk); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to enable pclk\n"); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(&pdev->dev, |
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rockchip_saradc_pclk_disable, info); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to register devm action, %d\n", |
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ret); |
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return ret; |
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} |
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ret = clk_prepare_enable(info->clk); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to enable converter clock\n"); |
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return ret; |
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} |
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ret = devm_add_action_or_reset(&pdev->dev, |
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rockchip_saradc_clk_disable, info); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to register devm action, %d\n", |
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ret); |
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return ret; |
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} |
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platform_set_drvdata(pdev, indio_dev); |
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indio_dev->name = dev_name(&pdev->dev); |
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indio_dev->info = &rockchip_saradc_iio_info; |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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indio_dev->channels = info->data->channels; |
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indio_dev->num_channels = info->data->num_channels; |
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ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL, |
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rockchip_saradc_trigger_handler, |
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NULL); |
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if (ret) |
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return ret; |
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return devm_iio_device_register(&pdev->dev, indio_dev); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int rockchip_saradc_suspend(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct rockchip_saradc *info = iio_priv(indio_dev); |
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clk_disable_unprepare(info->clk); |
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clk_disable_unprepare(info->pclk); |
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regulator_disable(info->vref); |
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return 0; |
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} |
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static int rockchip_saradc_resume(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct rockchip_saradc *info = iio_priv(indio_dev); |
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int ret; |
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ret = regulator_enable(info->vref); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(info->pclk); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(info->clk); |
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if (ret) |
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clk_disable_unprepare(info->pclk); |
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return ret; |
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} |
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#endif |
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static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops, |
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rockchip_saradc_suspend, rockchip_saradc_resume); |
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static struct platform_driver rockchip_saradc_driver = { |
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.probe = rockchip_saradc_probe, |
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.driver = { |
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.name = "rockchip-saradc", |
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.of_match_table = rockchip_saradc_match, |
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.pm = &rockchip_saradc_pm_ops, |
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}, |
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}; |
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module_platform_driver(rockchip_saradc_driver); |
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MODULE_AUTHOR("Heiko Stuebner <[email protected]>"); |
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MODULE_DESCRIPTION("Rockchip SARADC driver"); |
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MODULE_LICENSE("GPL v2");
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