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347 lines
8.9 KiB
347 lines
8.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2016 MediaTek Inc. |
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* Author: Zhiyong Tao <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#include <linux/iopoll.h> |
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#include <linux/io.h> |
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#include <linux/iio/iio.h> |
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/* Register definitions */ |
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#define MT6577_AUXADC_CON0 0x00 |
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#define MT6577_AUXADC_CON1 0x04 |
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#define MT6577_AUXADC_CON2 0x10 |
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#define MT6577_AUXADC_STA BIT(0) |
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#define MT6577_AUXADC_DAT0 0x14 |
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#define MT6577_AUXADC_RDY0 BIT(12) |
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#define MT6577_AUXADC_MISC 0x94 |
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#define MT6577_AUXADC_PDN_EN BIT(14) |
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#define MT6577_AUXADC_DAT_MASK 0xfff |
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#define MT6577_AUXADC_SLEEP_US 1000 |
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#define MT6577_AUXADC_TIMEOUT_US 10000 |
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#define MT6577_AUXADC_POWER_READY_MS 1 |
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#define MT6577_AUXADC_SAMPLE_READY_US 25 |
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struct mtk_auxadc_compatible { |
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bool sample_data_cali; |
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bool check_global_idle; |
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}; |
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struct mt6577_auxadc_device { |
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void __iomem *reg_base; |
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struct clk *adc_clk; |
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struct mutex lock; |
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const struct mtk_auxadc_compatible *dev_comp; |
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}; |
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static const struct mtk_auxadc_compatible mt8173_compat = { |
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.sample_data_cali = false, |
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.check_global_idle = true, |
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}; |
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static const struct mtk_auxadc_compatible mt6765_compat = { |
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.sample_data_cali = true, |
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.check_global_idle = false, |
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}; |
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#define MT6577_AUXADC_CHANNEL(idx) { \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = (idx), \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \ |
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} |
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static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = { |
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MT6577_AUXADC_CHANNEL(0), |
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MT6577_AUXADC_CHANNEL(1), |
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MT6577_AUXADC_CHANNEL(2), |
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MT6577_AUXADC_CHANNEL(3), |
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MT6577_AUXADC_CHANNEL(4), |
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MT6577_AUXADC_CHANNEL(5), |
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MT6577_AUXADC_CHANNEL(6), |
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MT6577_AUXADC_CHANNEL(7), |
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MT6577_AUXADC_CHANNEL(8), |
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MT6577_AUXADC_CHANNEL(9), |
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MT6577_AUXADC_CHANNEL(10), |
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MT6577_AUXADC_CHANNEL(11), |
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MT6577_AUXADC_CHANNEL(12), |
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MT6577_AUXADC_CHANNEL(13), |
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MT6577_AUXADC_CHANNEL(14), |
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MT6577_AUXADC_CHANNEL(15), |
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}; |
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static int mt_auxadc_get_cali_data(int rawdata, bool enable_cali) |
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{ |
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return rawdata; |
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} |
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static inline void mt6577_auxadc_mod_reg(void __iomem *reg, |
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u32 or_mask, u32 and_mask) |
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{ |
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u32 val; |
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val = readl(reg); |
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val |= or_mask; |
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val &= ~and_mask; |
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writel(val, reg); |
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} |
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static int mt6577_auxadc_read(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan) |
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{ |
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u32 val; |
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void __iomem *reg_channel; |
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int ret; |
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struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); |
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reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 + |
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chan->channel * 0x04; |
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mutex_lock(&adc_dev->lock); |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, |
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0, 1 << chan->channel); |
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/* read channel and make sure old ready bit == 0 */ |
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ret = readl_poll_timeout(reg_channel, val, |
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((val & MT6577_AUXADC_RDY0) == 0), |
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MT6577_AUXADC_SLEEP_US, |
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MT6577_AUXADC_TIMEOUT_US); |
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if (ret < 0) { |
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dev_err(indio_dev->dev.parent, |
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"wait for channel[%d] ready bit clear time out\n", |
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chan->channel); |
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goto err_timeout; |
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} |
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/* set bit to trigger sample */ |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1, |
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1 << chan->channel, 0); |
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/* we must delay here for hardware sample channel data */ |
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udelay(MT6577_AUXADC_SAMPLE_READY_US); |
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if (adc_dev->dev_comp->check_global_idle) { |
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/* check MTK_AUXADC_CON2 if auxadc is idle */ |
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ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2, |
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val, ((val & MT6577_AUXADC_STA) == 0), |
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MT6577_AUXADC_SLEEP_US, |
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MT6577_AUXADC_TIMEOUT_US); |
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if (ret < 0) { |
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dev_err(indio_dev->dev.parent, |
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"wait for auxadc idle time out\n"); |
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goto err_timeout; |
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} |
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} |
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/* read channel and make sure ready bit == 1 */ |
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ret = readl_poll_timeout(reg_channel, val, |
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((val & MT6577_AUXADC_RDY0) != 0), |
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MT6577_AUXADC_SLEEP_US, |
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MT6577_AUXADC_TIMEOUT_US); |
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if (ret < 0) { |
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dev_err(indio_dev->dev.parent, |
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"wait for channel[%d] data ready time out\n", |
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chan->channel); |
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goto err_timeout; |
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} |
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/* read data */ |
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val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK; |
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mutex_unlock(&adc_dev->lock); |
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return val; |
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err_timeout: |
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mutex_unlock(&adc_dev->lock); |
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return -ETIMEDOUT; |
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} |
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static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, |
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int *val2, |
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long info) |
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{ |
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struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); |
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switch (info) { |
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case IIO_CHAN_INFO_PROCESSED: |
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*val = mt6577_auxadc_read(indio_dev, chan); |
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if (*val < 0) { |
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dev_err(indio_dev->dev.parent, |
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"failed to sample data on channel[%d]\n", |
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chan->channel); |
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return *val; |
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} |
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if (adc_dev->dev_comp->sample_data_cali) |
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*val = mt_auxadc_get_cali_data(*val, true); |
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return IIO_VAL_INT; |
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default: |
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return -EINVAL; |
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} |
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} |
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static const struct iio_info mt6577_auxadc_info = { |
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.read_raw = &mt6577_auxadc_read_raw, |
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}; |
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static int __maybe_unused mt6577_auxadc_resume(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); |
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int ret; |
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ret = clk_prepare_enable(adc_dev->adc_clk); |
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if (ret) { |
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pr_err("failed to enable auxadc clock\n"); |
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return ret; |
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} |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, |
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MT6577_AUXADC_PDN_EN, 0); |
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mdelay(MT6577_AUXADC_POWER_READY_MS); |
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return 0; |
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} |
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static int __maybe_unused mt6577_auxadc_suspend(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, |
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0, MT6577_AUXADC_PDN_EN); |
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clk_disable_unprepare(adc_dev->adc_clk); |
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return 0; |
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} |
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static int mt6577_auxadc_probe(struct platform_device *pdev) |
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{ |
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struct mt6577_auxadc_device *adc_dev; |
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unsigned long adc_clk_rate; |
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struct iio_dev *indio_dev; |
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int ret; |
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev)); |
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if (!indio_dev) |
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return -ENOMEM; |
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adc_dev = iio_priv(indio_dev); |
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indio_dev->name = dev_name(&pdev->dev); |
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indio_dev->info = &mt6577_auxadc_info; |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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indio_dev->channels = mt6577_auxadc_iio_channels; |
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indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels); |
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adc_dev->reg_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(adc_dev->reg_base)) { |
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dev_err(&pdev->dev, "failed to get auxadc base address\n"); |
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return PTR_ERR(adc_dev->reg_base); |
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} |
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adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main"); |
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if (IS_ERR(adc_dev->adc_clk)) { |
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dev_err(&pdev->dev, "failed to get auxadc clock\n"); |
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return PTR_ERR(adc_dev->adc_clk); |
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} |
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ret = clk_prepare_enable(adc_dev->adc_clk); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to enable auxadc clock\n"); |
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return ret; |
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} |
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adc_clk_rate = clk_get_rate(adc_dev->adc_clk); |
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if (!adc_clk_rate) { |
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ret = -EINVAL; |
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dev_err(&pdev->dev, "null clock rate\n"); |
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goto err_disable_clk; |
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} |
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adc_dev->dev_comp = device_get_match_data(&pdev->dev); |
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mutex_init(&adc_dev->lock); |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, |
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MT6577_AUXADC_PDN_EN, 0); |
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mdelay(MT6577_AUXADC_POWER_READY_MS); |
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platform_set_drvdata(pdev, indio_dev); |
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ret = iio_device_register(indio_dev); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to register iio device\n"); |
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goto err_power_off; |
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} |
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return 0; |
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err_power_off: |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, |
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0, MT6577_AUXADC_PDN_EN); |
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err_disable_clk: |
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clk_disable_unprepare(adc_dev->adc_clk); |
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return ret; |
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} |
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static int mt6577_auxadc_remove(struct platform_device *pdev) |
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{ |
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struct iio_dev *indio_dev = platform_get_drvdata(pdev); |
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struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev); |
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iio_device_unregister(indio_dev); |
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mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC, |
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0, MT6577_AUXADC_PDN_EN); |
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clk_disable_unprepare(adc_dev->adc_clk); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops, |
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mt6577_auxadc_suspend, |
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mt6577_auxadc_resume); |
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static const struct of_device_id mt6577_auxadc_of_match[] = { |
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{ .compatible = "mediatek,mt2701-auxadc", .data = &mt8173_compat}, |
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{ .compatible = "mediatek,mt2712-auxadc", .data = &mt8173_compat}, |
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{ .compatible = "mediatek,mt7622-auxadc", .data = &mt8173_compat}, |
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{ .compatible = "mediatek,mt8173-auxadc", .data = &mt8173_compat}, |
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{ .compatible = "mediatek,mt6765-auxadc", .data = &mt6765_compat}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match); |
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static struct platform_driver mt6577_auxadc_driver = { |
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.driver = { |
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.name = "mt6577-auxadc", |
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.of_match_table = mt6577_auxadc_of_match, |
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.pm = &mt6577_auxadc_pm_ops, |
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}, |
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.probe = mt6577_auxadc_probe, |
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.remove = mt6577_auxadc_remove, |
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}; |
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module_platform_driver(mt6577_auxadc_driver); |
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MODULE_AUTHOR("Zhiyong Tao <[email protected]>"); |
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MODULE_DESCRIPTION("MTK AUXADC Device Driver"); |
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MODULE_LICENSE("GPL v2");
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