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564 lines
15 KiB
564 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Freescale i.MX7D ADC driver |
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* |
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/driver.h> |
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#include <linux/iio/sysfs.h> |
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/* ADC register */ |
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#define IMX7D_REG_ADC_CH_A_CFG1 0x00 |
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#define IMX7D_REG_ADC_CH_A_CFG2 0x10 |
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#define IMX7D_REG_ADC_CH_B_CFG1 0x20 |
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#define IMX7D_REG_ADC_CH_B_CFG2 0x30 |
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#define IMX7D_REG_ADC_CH_C_CFG1 0x40 |
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#define IMX7D_REG_ADC_CH_C_CFG2 0x50 |
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#define IMX7D_REG_ADC_CH_D_CFG1 0x60 |
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#define IMX7D_REG_ADC_CH_D_CFG2 0x70 |
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#define IMX7D_REG_ADC_CH_SW_CFG 0x80 |
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#define IMX7D_REG_ADC_TIMER_UNIT 0x90 |
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#define IMX7D_REG_ADC_DMA_FIFO 0xa0 |
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#define IMX7D_REG_ADC_FIFO_STATUS 0xb0 |
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#define IMX7D_REG_ADC_INT_SIG_EN 0xc0 |
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#define IMX7D_REG_ADC_INT_EN 0xd0 |
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#define IMX7D_REG_ADC_INT_STATUS 0xe0 |
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#define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0 |
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#define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100 |
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#define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110 |
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#define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120 |
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#define IMX7D_REG_ADC_ADC_CFG 0x130 |
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#define IMX7D_REG_ADC_CHANNEL_CFG2_BASE 0x10 |
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#define IMX7D_EACH_CHANNEL_REG_OFFSET 0x20 |
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#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31) |
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#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30) |
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#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29) |
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#define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(x) ((x) << 24) |
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#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12) |
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#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12) |
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#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12) |
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#define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32 (0x3 << 29) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64 (0x4 << 29) |
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#define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128 (0x5 << 29) |
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#define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31) |
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#define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1) |
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#define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0) |
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#define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8) |
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#define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9) |
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#define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10) |
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#define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11) |
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#define IMX7D_REG_ADC_INT_CHANNEL_INT_EN \ |
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(IMX7D_REG_ADC_INT_CHA_COV_INT_EN | \ |
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IMX7D_REG_ADC_INT_CHB_COV_INT_EN | \ |
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IMX7D_REG_ADC_INT_CHC_COV_INT_EN | \ |
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IMX7D_REG_ADC_INT_CHD_COV_INT_EN) |
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#define IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS 0xf00 |
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#define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000 |
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#define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100) |
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#define IMX7D_ADC_INPUT_CLK 24000000 |
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enum imx7d_adc_clk_pre_div { |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_4, |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_8, |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_16, |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_32, |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_64, |
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IMX7D_ADC_ANALOG_CLK_PRE_DIV_128, |
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}; |
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enum imx7d_adc_average_num { |
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IMX7D_ADC_AVERAGE_NUM_4, |
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IMX7D_ADC_AVERAGE_NUM_8, |
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IMX7D_ADC_AVERAGE_NUM_16, |
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IMX7D_ADC_AVERAGE_NUM_32, |
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}; |
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struct imx7d_adc_feature { |
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enum imx7d_adc_clk_pre_div clk_pre_div; |
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enum imx7d_adc_average_num avg_num; |
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u32 core_time_unit; /* impact the sample rate */ |
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}; |
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struct imx7d_adc { |
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struct device *dev; |
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void __iomem *regs; |
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struct clk *clk; |
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u32 vref_uv; |
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u32 value; |
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u32 channel; |
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u32 pre_div_num; |
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struct regulator *vref; |
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struct imx7d_adc_feature adc_feature; |
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struct completion completion; |
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}; |
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struct imx7d_adc_analogue_core_clk { |
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u32 pre_div; |
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u32 reg_config; |
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}; |
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#define IMX7D_ADC_ANALOGUE_CLK_CONFIG(_pre_div, _reg_conf) { \ |
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.pre_div = (_pre_div), \ |
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.reg_config = (_reg_conf), \ |
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} |
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static const struct imx7d_adc_analogue_core_clk imx7d_adc_analogue_clk[] = { |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(4, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4), |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(8, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8), |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(16, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16), |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(32, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32), |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(64, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64), |
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IMX7D_ADC_ANALOGUE_CLK_CONFIG(128, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128), |
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}; |
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#define IMX7D_ADC_CHAN(_idx) { \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = (_idx), \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ |
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \ |
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} |
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static const struct iio_chan_spec imx7d_adc_iio_channels[] = { |
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IMX7D_ADC_CHAN(0), |
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IMX7D_ADC_CHAN(1), |
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IMX7D_ADC_CHAN(2), |
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IMX7D_ADC_CHAN(3), |
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IMX7D_ADC_CHAN(4), |
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IMX7D_ADC_CHAN(5), |
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IMX7D_ADC_CHAN(6), |
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IMX7D_ADC_CHAN(7), |
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IMX7D_ADC_CHAN(8), |
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IMX7D_ADC_CHAN(9), |
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IMX7D_ADC_CHAN(10), |
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IMX7D_ADC_CHAN(11), |
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IMX7D_ADC_CHAN(12), |
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IMX7D_ADC_CHAN(13), |
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IMX7D_ADC_CHAN(14), |
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IMX7D_ADC_CHAN(15), |
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}; |
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static const u32 imx7d_adc_average_num[] = { |
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IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4, |
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IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8, |
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IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16, |
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IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32, |
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}; |
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static void imx7d_adc_feature_config(struct imx7d_adc *info) |
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{ |
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info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4; |
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info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32; |
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info->adc_feature.core_time_unit = 1; |
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} |
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static void imx7d_adc_sample_rate_set(struct imx7d_adc *info) |
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{ |
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struct imx7d_adc_feature *adc_feature = &info->adc_feature; |
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struct imx7d_adc_analogue_core_clk adc_analogure_clk; |
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u32 i; |
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u32 tmp_cfg1; |
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u32 sample_rate = 0; |
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/* |
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* Before sample set, disable channel A,B,C,D. Here we |
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* clear the bit 31 of register REG_ADC_CH_A\B\C\D_CFG1. |
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*/ |
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for (i = 0; i < 4; i++) { |
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tmp_cfg1 = |
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readl(info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET); |
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tmp_cfg1 &= ~IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN; |
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writel(tmp_cfg1, |
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info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET); |
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} |
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adc_analogure_clk = imx7d_adc_analogue_clk[adc_feature->clk_pre_div]; |
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sample_rate |= adc_analogure_clk.reg_config; |
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info->pre_div_num = adc_analogure_clk.pre_div; |
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sample_rate |= adc_feature->core_time_unit; |
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writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT); |
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} |
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static void imx7d_adc_hw_init(struct imx7d_adc *info) |
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{ |
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u32 cfg; |
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/* power up and enable adc analogue core */ |
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cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG); |
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cfg &= ~(IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN | |
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IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN); |
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cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_EN; |
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writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG); |
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/* enable channel A,B,C,D interrupt */ |
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writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN, |
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info->regs + IMX7D_REG_ADC_INT_SIG_EN); |
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writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN, |
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info->regs + IMX7D_REG_ADC_INT_EN); |
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imx7d_adc_sample_rate_set(info); |
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} |
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static void imx7d_adc_channel_set(struct imx7d_adc *info) |
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{ |
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u32 cfg1 = 0; |
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u32 cfg2; |
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u32 channel; |
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channel = info->channel; |
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/* the channel choose single conversion, and enable average mode */ |
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cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | |
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IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE | |
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IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN); |
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/* |
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* physical channel 0 chose logical channel A |
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* physical channel 1 chose logical channel B |
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* physical channel 2 chose logical channel C |
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* physical channel 3 chose logical channel D |
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*/ |
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cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel); |
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/* |
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* read register REG_ADC_CH_A\B\C\D_CFG2, according to the |
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* channel chosen |
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*/ |
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cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel + |
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IMX7D_REG_ADC_CHANNEL_CFG2_BASE); |
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cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num]; |
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/* |
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* write the register REG_ADC_CH_A\B\C\D_CFG2, according to |
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* the channel chosen |
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*/ |
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writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel + |
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IMX7D_REG_ADC_CHANNEL_CFG2_BASE); |
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writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel); |
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} |
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static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info) |
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{ |
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u32 analogue_core_clk; |
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u32 core_time_unit = info->adc_feature.core_time_unit; |
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u32 tmp; |
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analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num; |
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tmp = (core_time_unit + 1) * 6; |
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return analogue_core_clk / tmp; |
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} |
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static int imx7d_adc_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, |
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int *val2, |
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long mask) |
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{ |
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struct imx7d_adc *info = iio_priv(indio_dev); |
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u32 channel; |
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long ret; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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mutex_lock(&indio_dev->mlock); |
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reinit_completion(&info->completion); |
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channel = chan->channel & 0x03; |
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info->channel = channel; |
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imx7d_adc_channel_set(info); |
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ret = wait_for_completion_interruptible_timeout |
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(&info->completion, IMX7D_ADC_TIMEOUT); |
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if (ret == 0) { |
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mutex_unlock(&indio_dev->mlock); |
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return -ETIMEDOUT; |
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} |
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if (ret < 0) { |
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mutex_unlock(&indio_dev->mlock); |
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return ret; |
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} |
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*val = info->value; |
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mutex_unlock(&indio_dev->mlock); |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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info->vref_uv = regulator_get_voltage(info->vref); |
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*val = info->vref_uv / 1000; |
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*val2 = 12; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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*val = imx7d_adc_get_sample_rate(info); |
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return IIO_VAL_INT; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int imx7d_adc_read_data(struct imx7d_adc *info) |
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{ |
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u32 channel; |
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u32 value; |
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channel = info->channel & 0x03; |
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/* |
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* channel A and B conversion result share one register, |
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* bit[27~16] is the channel B conversion result, |
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* bit[11~0] is the channel A conversion result. |
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* channel C and D is the same. |
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*/ |
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if (channel < 2) |
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value = readl(info->regs + IMX7D_REG_ADC_CHA_B_CNV_RSLT); |
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else |
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value = readl(info->regs + IMX7D_REG_ADC_CHC_D_CNV_RSLT); |
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if (channel & 0x1) /* channel B or D */ |
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value = (value >> 16) & 0xFFF; |
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else /* channel A or C */ |
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value &= 0xFFF; |
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return value; |
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} |
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static irqreturn_t imx7d_adc_isr(int irq, void *dev_id) |
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{ |
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struct imx7d_adc *info = dev_id; |
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int status; |
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status = readl(info->regs + IMX7D_REG_ADC_INT_STATUS); |
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if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS) { |
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info->value = imx7d_adc_read_data(info); |
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complete(&info->completion); |
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/* |
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* The register IMX7D_REG_ADC_INT_STATUS can't clear |
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* itself after read operation, need software to write |
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* 0 to the related bit. Here we clear the channel A/B/C/D |
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* conversion finished flag. |
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*/ |
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status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS; |
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writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS); |
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} |
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/* |
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* If the channel A/B/C/D conversion timeout, report it and clear these |
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* timeout flags. |
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*/ |
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if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT) { |
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dev_err(info->dev, |
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"ADC got conversion time out interrupt: 0x%08x\n", |
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status); |
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status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT; |
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writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS); |
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} |
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return IRQ_HANDLED; |
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} |
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static int imx7d_adc_reg_access(struct iio_dev *indio_dev, |
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unsigned reg, unsigned writeval, |
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unsigned *readval) |
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{ |
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struct imx7d_adc *info = iio_priv(indio_dev); |
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if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG) |
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return -EINVAL; |
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*readval = readl(info->regs + reg); |
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return 0; |
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} |
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static const struct iio_info imx7d_adc_iio_info = { |
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.read_raw = &imx7d_adc_read_raw, |
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.debugfs_reg_access = &imx7d_adc_reg_access, |
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}; |
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static const struct of_device_id imx7d_adc_match[] = { |
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{ .compatible = "fsl,imx7d-adc", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, imx7d_adc_match); |
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static void imx7d_adc_power_down(struct imx7d_adc *info) |
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{ |
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u32 adc_cfg; |
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adc_cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG); |
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adc_cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN | |
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IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN; |
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adc_cfg &= ~IMX7D_REG_ADC_ADC_CFG_ADC_EN; |
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writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG); |
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} |
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static int imx7d_adc_enable(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct imx7d_adc *info = iio_priv(indio_dev); |
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int ret; |
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ret = regulator_enable(info->vref); |
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if (ret) { |
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dev_err(info->dev, |
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"Can't enable adc reference top voltage, err = %d\n", |
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ret); |
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return ret; |
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} |
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ret = clk_prepare_enable(info->clk); |
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if (ret) { |
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dev_err(info->dev, |
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"Could not prepare or enable clock.\n"); |
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regulator_disable(info->vref); |
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return ret; |
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} |
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imx7d_adc_hw_init(info); |
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return 0; |
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} |
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static int imx7d_adc_disable(struct device *dev) |
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{ |
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struct iio_dev *indio_dev = dev_get_drvdata(dev); |
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struct imx7d_adc *info = iio_priv(indio_dev); |
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imx7d_adc_power_down(info); |
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clk_disable_unprepare(info->clk); |
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regulator_disable(info->vref); |
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return 0; |
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} |
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static void __imx7d_adc_disable(void *data) |
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{ |
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imx7d_adc_disable(data); |
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} |
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static int imx7d_adc_probe(struct platform_device *pdev) |
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{ |
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struct imx7d_adc *info; |
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struct iio_dev *indio_dev; |
|
struct device *dev = &pdev->dev; |
|
int irq; |
|
int ret; |
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*info)); |
|
if (!indio_dev) { |
|
dev_err(&pdev->dev, "Failed allocating iio device\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
info = iio_priv(indio_dev); |
|
info->dev = dev; |
|
|
|
info->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(info->regs)) |
|
return PTR_ERR(info->regs); |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
info->clk = devm_clk_get(dev, "adc"); |
|
if (IS_ERR(info->clk)) { |
|
ret = PTR_ERR(info->clk); |
|
dev_err(dev, "Failed getting clock, err = %d\n", ret); |
|
return ret; |
|
} |
|
|
|
info->vref = devm_regulator_get(dev, "vref"); |
|
if (IS_ERR(info->vref)) { |
|
ret = PTR_ERR(info->vref); |
|
dev_err(dev, |
|
"Failed getting reference voltage, err = %d\n", ret); |
|
return ret; |
|
} |
|
|
|
platform_set_drvdata(pdev, indio_dev); |
|
|
|
init_completion(&info->completion); |
|
|
|
indio_dev->name = dev_name(dev); |
|
indio_dev->info = &imx7d_adc_iio_info; |
|
indio_dev->modes = INDIO_DIRECT_MODE; |
|
indio_dev->channels = imx7d_adc_iio_channels; |
|
indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels); |
|
|
|
ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info); |
|
if (ret < 0) { |
|
dev_err(dev, "Failed requesting irq, irq = %d\n", irq); |
|
return ret; |
|
} |
|
|
|
imx7d_adc_feature_config(info); |
|
|
|
ret = imx7d_adc_enable(&indio_dev->dev); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_add_action_or_reset(dev, __imx7d_adc_disable, |
|
&indio_dev->dev); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_iio_device_register(dev, indio_dev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Couldn't register the device.\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable, imx7d_adc_enable); |
|
|
|
static struct platform_driver imx7d_adc_driver = { |
|
.probe = imx7d_adc_probe, |
|
.driver = { |
|
.name = "imx7d_adc", |
|
.of_match_table = imx7d_adc_match, |
|
.pm = &imx7d_adc_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(imx7d_adc_driver); |
|
|
|
MODULE_AUTHOR("Haibo Chen <[email protected]>"); |
|
MODULE_DESCRIPTION("Freescale IMX7D ADC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|