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246 lines
6.6 KiB
246 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for ADC module on the Cirrus Logic EP93xx series of SoCs |
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* |
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* Copyright (C) 2015 Alexander Sverdlin |
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* |
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* The driver uses polling to get the conversion status. According to EP93xx |
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* datasheets, reading ADCResult register starts the conversion, but user is also |
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* responsible for ensuring that delay between adjacent conversion triggers is |
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* long enough so that maximum allowed conversion rate is not exceeded. This |
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* basically renders IRQ mode unusable. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/iio/iio.h> |
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#include <linux/io.h> |
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#include <linux/irqflags.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/platform_device.h> |
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/* |
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* This code could benefit from real HR Timers, but jiffy granularity would |
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* lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait |
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* in such case. |
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* |
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* HR Timers-based version loads CPU only up to 10% during back to back ADC |
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* conversion, while busy wait-based version consumes whole CPU power. |
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*/ |
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#ifdef CONFIG_HIGH_RES_TIMERS |
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#define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax) |
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#else |
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#define ep93xx_adc_delay(usmin, usmax) udelay(usmin) |
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#endif |
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#define EP93XX_ADC_RESULT 0x08 |
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#define EP93XX_ADC_SDR BIT(31) |
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#define EP93XX_ADC_SWITCH 0x18 |
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#define EP93XX_ADC_SW_LOCK 0x20 |
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struct ep93xx_adc_priv { |
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struct clk *clk; |
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void __iomem *base; |
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int lastch; |
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struct mutex lock; |
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}; |
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#define EP93XX_ADC_CH(index, dname, swcfg) { \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = index, \ |
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.address = swcfg, \ |
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.datasheet_name = dname, \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \ |
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BIT(IIO_CHAN_INFO_OFFSET), \ |
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} |
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/* |
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* Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets. |
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* EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is |
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* not defined. So the last three are numbered randomly, let's say. |
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*/ |
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static const struct iio_chan_spec ep93xx_adc_channels[8] = { |
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EP93XX_ADC_CH(0, "YM", 0x608), |
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EP93XX_ADC_CH(1, "SXP", 0x680), |
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EP93XX_ADC_CH(2, "SXM", 0x640), |
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EP93XX_ADC_CH(3, "SYP", 0x620), |
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EP93XX_ADC_CH(4, "SYM", 0x610), |
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EP93XX_ADC_CH(5, "XP", 0x601), |
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EP93XX_ADC_CH(6, "XM", 0x602), |
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EP93XX_ADC_CH(7, "YP", 0x604), |
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}; |
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static int ep93xx_read_raw(struct iio_dev *iiodev, |
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struct iio_chan_spec const *channel, int *value, |
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int *shift, long mask) |
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{ |
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struct ep93xx_adc_priv *priv = iio_priv(iiodev); |
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unsigned long timeout; |
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int ret; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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mutex_lock(&priv->lock); |
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if (priv->lastch != channel->channel) { |
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priv->lastch = channel->channel; |
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/* |
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* Switch register is software-locked, unlocking must be |
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* immediately followed by write |
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*/ |
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local_irq_disable(); |
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writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK); |
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writel_relaxed(channel->address, |
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priv->base + EP93XX_ADC_SWITCH); |
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local_irq_enable(); |
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/* |
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* Settling delay depends on module clock and could be |
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* 2ms or 500us |
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*/ |
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ep93xx_adc_delay(2000, 2000); |
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} |
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/* Start the conversion, eventually discarding old result */ |
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readl_relaxed(priv->base + EP93XX_ADC_RESULT); |
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/* Ensure maximum conversion rate is not exceeded */ |
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ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925), |
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DIV_ROUND_UP(1000000, 925)); |
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/* At this point conversion must be completed, but anyway... */ |
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ret = IIO_VAL_INT; |
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timeout = jiffies + msecs_to_jiffies(1) + 1; |
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while (1) { |
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u32 t; |
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t = readl_relaxed(priv->base + EP93XX_ADC_RESULT); |
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if (t & EP93XX_ADC_SDR) { |
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*value = sign_extend32(t, 15); |
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break; |
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} |
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if (time_after(jiffies, timeout)) { |
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dev_err(&iiodev->dev, "Conversion timeout\n"); |
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ret = -ETIMEDOUT; |
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break; |
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} |
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cpu_relax(); |
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} |
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mutex_unlock(&priv->lock); |
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return ret; |
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case IIO_CHAN_INFO_OFFSET: |
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/* According to datasheet, range is -25000..25000 */ |
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*value = 25000; |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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/* Typical supply voltage is 3.3v */ |
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*value = (1ULL << 32) * 3300 / 50000; |
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*shift = 32; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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} |
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return -EINVAL; |
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} |
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static const struct iio_info ep93xx_adc_info = { |
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.read_raw = ep93xx_read_raw, |
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}; |
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static int ep93xx_adc_probe(struct platform_device *pdev) |
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{ |
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int ret; |
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struct iio_dev *iiodev; |
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struct ep93xx_adc_priv *priv; |
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struct clk *pclk; |
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struct resource *res; |
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iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv)); |
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if (!iiodev) |
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return -ENOMEM; |
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priv = iio_priv(iiodev); |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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priv->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(priv->base)) { |
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dev_err(&pdev->dev, "Cannot map memory resource\n"); |
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return PTR_ERR(priv->base); |
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} |
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iiodev->name = dev_name(&pdev->dev); |
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iiodev->modes = INDIO_DIRECT_MODE; |
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iiodev->info = &ep93xx_adc_info; |
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iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels); |
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iiodev->channels = ep93xx_adc_channels; |
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priv->lastch = -1; |
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mutex_init(&priv->lock); |
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platform_set_drvdata(pdev, iiodev); |
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priv->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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dev_err(&pdev->dev, "Cannot obtain clock\n"); |
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return PTR_ERR(priv->clk); |
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} |
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pclk = clk_get_parent(priv->clk); |
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if (!pclk) { |
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dev_warn(&pdev->dev, "Cannot obtain parent clock\n"); |
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} else { |
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/* |
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* This is actually a place for improvement: |
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* EP93xx ADC supports two clock divisors -- 4 and 16, |
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* resulting in conversion rates 3750 and 925 samples per second |
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* with 500us or 2ms settling time respectively. |
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* One might find this interesting enough to be configurable. |
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*/ |
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ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16); |
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if (ret) |
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dev_warn(&pdev->dev, "Cannot set clock rate\n"); |
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/* |
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* We can tolerate rate setting failure because the module should |
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* work in any case. |
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*/ |
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} |
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ret = clk_enable(priv->clk); |
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if (ret) { |
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dev_err(&pdev->dev, "Cannot enable clock\n"); |
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return ret; |
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} |
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ret = iio_device_register(iiodev); |
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if (ret) |
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clk_disable(priv->clk); |
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return ret; |
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} |
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static int ep93xx_adc_remove(struct platform_device *pdev) |
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{ |
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struct iio_dev *iiodev = platform_get_drvdata(pdev); |
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struct ep93xx_adc_priv *priv = iio_priv(iiodev); |
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iio_device_unregister(iiodev); |
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clk_disable(priv->clk); |
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return 0; |
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} |
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static struct platform_driver ep93xx_adc_driver = { |
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.driver = { |
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.name = "ep93xx-adc", |
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}, |
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.probe = ep93xx_adc_probe, |
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.remove = ep93xx_adc_remove, |
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}; |
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module_platform_driver(ep93xx_adc_driver); |
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MODULE_AUTHOR("Alexander Sverdlin <[email protected]>"); |
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MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:ep93xx-adc");
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