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1398 lines
39 KiB
1398 lines
39 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for the ADC present in the Atmel AT91 evaluation boards. |
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* |
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* Copyright 2011 Free Electrons |
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*/ |
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#include <linux/bitmap.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/input.h> |
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#include <linux/interrupt.h> |
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#include <linux/jiffies.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <linux/wait.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/buffer.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/trigger_consumer.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/pinctrl/consumer.h> |
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/* Registers */ |
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#define AT91_ADC_CR 0x00 /* Control Register */ |
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#define AT91_ADC_SWRST (1 << 0) /* Software Reset */ |
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#define AT91_ADC_START (1 << 1) /* Start Conversion */ |
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#define AT91_ADC_MR 0x04 /* Mode Register */ |
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#define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ |
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#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ |
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#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ |
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#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ |
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#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ |
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#define AT91_ADC_TRGSEL_TC0 (0 << 1) |
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#define AT91_ADC_TRGSEL_TC1 (1 << 1) |
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#define AT91_ADC_TRGSEL_TC2 (2 << 1) |
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#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) |
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#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ |
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#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ |
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#define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ |
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#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ |
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#define AT91_ADC_PRESCAL_9G45 (0xff << 8) |
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#define AT91_ADC_PRESCAL_(x) ((x) << 8) |
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#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ |
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#define AT91_ADC_STARTUP_9G45 (0x7f << 16) |
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#define AT91_ADC_STARTUP_9X5 (0xf << 16) |
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#define AT91_ADC_STARTUP_(x) ((x) << 16) |
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#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ |
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#define AT91_ADC_SHTIM_(x) ((x) << 24) |
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#define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ |
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#define AT91_ADC_PENDBC_(x) ((x) << 28) |
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#define AT91_ADC_TSR 0x0C |
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#define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ |
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#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) |
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#define AT91_ADC_CHER 0x10 /* Channel Enable Register */ |
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#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ |
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#define AT91_ADC_CHSR 0x18 /* Channel Status Register */ |
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#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ |
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#define AT91_ADC_SR 0x1C /* Status Register */ |
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#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ |
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#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ |
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#define AT91_ADC_DRDY (1 << 16) /* Data Ready */ |
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#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ |
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#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ |
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#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ |
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#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ |
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#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ |
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#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ |
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#define AT91_ADC_LDATA (0x3ff) |
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#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ |
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#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ |
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#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ |
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#define AT91RL_ADC_IER_PEN (1 << 20) |
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#define AT91RL_ADC_IER_NOPEN (1 << 21) |
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#define AT91_ADC_IER_PEN (1 << 29) |
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#define AT91_ADC_IER_NOPEN (1 << 30) |
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#define AT91_ADC_IER_XRDY (1 << 20) |
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#define AT91_ADC_IER_YRDY (1 << 21) |
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#define AT91_ADC_IER_PRDY (1 << 22) |
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#define AT91_ADC_ISR_PENS (1 << 31) |
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#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ |
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#define AT91_ADC_DATA (0x3ff) |
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#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ |
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#define AT91_ADC_ACR 0x94 /* Analog Control Register */ |
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#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ |
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#define AT91_ADC_TSMR 0xB0 |
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#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ |
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#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) |
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#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) |
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#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) |
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#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) |
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#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ |
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#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) |
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#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ |
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#define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) |
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#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ |
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#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) |
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#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ |
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#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ |
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#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ |
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#define AT91_ADC_TSXPOSR 0xB4 |
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#define AT91_ADC_TSYPOSR 0xB8 |
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#define AT91_ADC_TSPRESSR 0xBC |
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#define AT91_ADC_TRGR_9260 AT91_ADC_MR |
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#define AT91_ADC_TRGR_9G45 0x08 |
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#define AT91_ADC_TRGR_9X5 0xC0 |
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/* Trigger Register bit field */ |
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#define AT91_ADC_TRGR_TRGPER (0xffff << 16) |
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#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) |
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#define AT91_ADC_TRGR_TRGMOD (0x7 << 0) |
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#define AT91_ADC_TRGR_NONE (0 << 0) |
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#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) |
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#define AT91_ADC_CHAN(st, ch) \ |
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(st->registers->channel_base + (ch * 4)) |
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#define at91_adc_readl(st, reg) \ |
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(readl_relaxed(st->reg_base + reg)) |
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#define at91_adc_writel(st, reg, val) \ |
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(writel_relaxed(val, st->reg_base + reg)) |
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#define DRIVER_NAME "at91_adc" |
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#define MAX_POS_BITS 12 |
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#define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ |
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#define TOUCH_PEN_DETECT_DEBOUNCE_US 200 |
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#define MAX_RLPOS_BITS 10 |
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#define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ |
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#define TOUCH_SHTIM 0xa |
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#define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ |
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enum atmel_adc_ts_type { |
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ATMEL_ADC_TOUCHSCREEN_NONE = 0, |
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ATMEL_ADC_TOUCHSCREEN_4WIRE = 4, |
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ATMEL_ADC_TOUCHSCREEN_5WIRE = 5, |
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}; |
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/** |
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* struct at91_adc_trigger - description of triggers |
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* @name: name of the trigger advertised to the user |
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* @value: value to set in the ADC's trigger setup register |
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* to enable the trigger |
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* @is_external: Does the trigger rely on an external pin? |
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*/ |
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struct at91_adc_trigger { |
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const char *name; |
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u8 value; |
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bool is_external; |
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}; |
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/** |
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* struct at91_adc_reg_desc - Various informations relative to registers |
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* @channel_base: Base offset for the channel data registers |
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* @drdy_mask: Mask of the DRDY field in the relevant registers |
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* (Interruptions registers mostly) |
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* @status_register: Offset of the Interrupt Status Register |
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* @trigger_register: Offset of the Trigger setup register |
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* @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register |
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* @mr_startup_mask: Mask of the STARTUP field in the adc MR register |
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*/ |
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struct at91_adc_reg_desc { |
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u8 channel_base; |
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u32 drdy_mask; |
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u8 status_register; |
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u8 trigger_register; |
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u32 mr_prescal_mask; |
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u32 mr_startup_mask; |
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}; |
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struct at91_adc_caps { |
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bool has_ts; /* Support touch screen */ |
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bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ |
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/* |
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* Numbers of sampling data will be averaged. Can be 0~3. |
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* Hardware can average (2 ^ ts_filter_average) sample data. |
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*/ |
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u8 ts_filter_average; |
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/* Pen Detection input pull-up resistor, can be 0~3 */ |
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u8 ts_pen_detect_sensitivity; |
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/* startup time calculate function */ |
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u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); |
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u8 num_channels; |
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u8 low_res_bits; |
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u8 high_res_bits; |
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u32 trigger_number; |
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const struct at91_adc_trigger *triggers; |
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struct at91_adc_reg_desc registers; |
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}; |
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struct at91_adc_state { |
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struct clk *adc_clk; |
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u16 *buffer; |
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unsigned long channels_mask; |
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struct clk *clk; |
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bool done; |
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int irq; |
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u16 last_value; |
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int chnb; |
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struct mutex lock; |
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u8 num_channels; |
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void __iomem *reg_base; |
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const struct at91_adc_reg_desc *registers; |
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u32 startup_time; |
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u8 sample_hold_time; |
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bool sleep_mode; |
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struct iio_trigger **trig; |
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bool use_external; |
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u32 vref_mv; |
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u32 res; /* resolution used for convertions */ |
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wait_queue_head_t wq_data_avail; |
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const struct at91_adc_caps *caps; |
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/* |
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* Following ADC channels are shared by touchscreen: |
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* |
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* CH0 -- Touch screen XP/UL |
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* CH1 -- Touch screen XM/UR |
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* CH2 -- Touch screen YP/LL |
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* CH3 -- Touch screen YM/Sense |
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* CH4 -- Touch screen LR(5-wire only) |
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* |
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* The bitfields below represents the reserved channel in the |
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* touchscreen mode. |
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*/ |
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#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) |
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#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) |
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enum atmel_adc_ts_type touchscreen_type; |
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struct input_dev *ts_input; |
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u16 ts_sample_period_val; |
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u32 ts_pressure_threshold; |
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u16 ts_pendbc; |
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bool ts_bufferedmeasure; |
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u32 ts_prev_absx; |
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u32 ts_prev_absy; |
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}; |
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static irqreturn_t at91_adc_trigger_handler(int irq, void *p) |
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{ |
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struct iio_poll_func *pf = p; |
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struct iio_dev *idev = pf->indio_dev; |
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struct at91_adc_state *st = iio_priv(idev); |
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struct iio_chan_spec const *chan; |
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int i, j = 0; |
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for (i = 0; i < idev->masklength; i++) { |
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if (!test_bit(i, idev->active_scan_mask)) |
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continue; |
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chan = idev->channels + i; |
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st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); |
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j++; |
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} |
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iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); |
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iio_trigger_notify_done(idev->trig); |
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/* Needed to ACK the DRDY interruption */ |
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at91_adc_readl(st, AT91_ADC_LCDR); |
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enable_irq(st->irq); |
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return IRQ_HANDLED; |
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} |
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/* Handler for classic adc channel eoc trigger */ |
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static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) |
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{ |
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struct at91_adc_state *st = iio_priv(idev); |
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if (iio_buffer_enabled(idev)) { |
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disable_irq_nosync(irq); |
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iio_trigger_poll(idev->trig); |
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} else { |
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st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); |
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/* Needed to ACK the DRDY interruption */ |
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at91_adc_readl(st, AT91_ADC_LCDR); |
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st->done = true; |
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wake_up_interruptible(&st->wq_data_avail); |
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} |
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} |
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static int at91_ts_sample(struct iio_dev *idev) |
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{ |
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struct at91_adc_state *st = iio_priv(idev); |
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unsigned int xscale, yscale, reg, z1, z2; |
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unsigned int x, y, pres, xpos, ypos; |
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unsigned int rxp = 1; |
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unsigned int factor = 1000; |
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unsigned int xyz_mask_bits = st->res; |
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unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; |
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/* calculate position */ |
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/* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ |
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reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); |
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xpos = reg & xyz_mask; |
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x = (xpos << MAX_POS_BITS) - xpos; |
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xscale = (reg >> 16) & xyz_mask; |
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if (xscale == 0) { |
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dev_err(&idev->dev, "Error: xscale == 0!\n"); |
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return -1; |
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} |
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x /= xscale; |
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/* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ |
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reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); |
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ypos = reg & xyz_mask; |
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y = (ypos << MAX_POS_BITS) - ypos; |
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yscale = (reg >> 16) & xyz_mask; |
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if (yscale == 0) { |
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dev_err(&idev->dev, "Error: yscale == 0!\n"); |
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return -1; |
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} |
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y /= yscale; |
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/* calculate the pressure */ |
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reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); |
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z1 = reg & xyz_mask; |
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z2 = (reg >> 16) & xyz_mask; |
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if (z1 != 0) |
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pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) |
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/ factor; |
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else |
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pres = st->ts_pressure_threshold; /* no pen contacted */ |
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dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", |
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xpos, xscale, ypos, yscale, z1, z2, pres); |
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if (pres < st->ts_pressure_threshold) { |
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dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", |
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x, y, pres / factor); |
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input_report_abs(st->ts_input, ABS_X, x); |
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input_report_abs(st->ts_input, ABS_Y, y); |
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input_report_abs(st->ts_input, ABS_PRESSURE, pres); |
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input_report_key(st->ts_input, BTN_TOUCH, 1); |
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input_sync(st->ts_input); |
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} else { |
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dev_dbg(&idev->dev, "pressure too low: not reporting\n"); |
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} |
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return 0; |
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} |
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static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) |
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{ |
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struct iio_dev *idev = private; |
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struct at91_adc_state *st = iio_priv(idev); |
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u32 status = at91_adc_readl(st, st->registers->status_register); |
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unsigned int reg; |
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status &= at91_adc_readl(st, AT91_ADC_IMR); |
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if (status & GENMASK(st->num_channels - 1, 0)) |
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handle_adc_eoc_trigger(irq, idev); |
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if (status & AT91RL_ADC_IER_PEN) { |
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/* Disabling pen debounce is required to get a NOPEN irq */ |
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reg = at91_adc_readl(st, AT91_ADC_MR); |
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reg &= ~AT91_ADC_PENDBC; |
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at91_adc_writel(st, AT91_ADC_MR, reg); |
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at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); |
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at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN |
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| AT91_ADC_EOC(3)); |
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/* Set up period trigger for sampling */ |
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at91_adc_writel(st, st->registers->trigger_register, |
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AT91_ADC_TRGR_MOD_PERIOD_TRIG | |
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AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); |
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} else if (status & AT91RL_ADC_IER_NOPEN) { |
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reg = at91_adc_readl(st, AT91_ADC_MR); |
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reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; |
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at91_adc_writel(st, AT91_ADC_MR, reg); |
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at91_adc_writel(st, st->registers->trigger_register, |
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AT91_ADC_TRGR_NONE); |
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at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN |
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| AT91_ADC_EOC(3)); |
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at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); |
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st->ts_bufferedmeasure = false; |
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input_report_key(st->ts_input, BTN_TOUCH, 0); |
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input_sync(st->ts_input); |
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} else if (status & AT91_ADC_EOC(3) && st->ts_input) { |
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/* Conversion finished and we've a touchscreen */ |
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if (st->ts_bufferedmeasure) { |
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/* |
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* Last measurement is always discarded, since it can |
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* be erroneous. |
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* Always report previous measurement |
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*/ |
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input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); |
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input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); |
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input_report_key(st->ts_input, BTN_TOUCH, 1); |
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input_sync(st->ts_input); |
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} else |
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st->ts_bufferedmeasure = true; |
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|
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/* Now make new measurement */ |
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st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) |
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<< MAX_RLPOS_BITS; |
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st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); |
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st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) |
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<< MAX_RLPOS_BITS; |
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st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); |
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} |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) |
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{ |
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struct iio_dev *idev = private; |
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struct at91_adc_state *st = iio_priv(idev); |
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u32 status = at91_adc_readl(st, st->registers->status_register); |
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const uint32_t ts_data_irq_mask = |
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AT91_ADC_IER_XRDY | |
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AT91_ADC_IER_YRDY | |
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AT91_ADC_IER_PRDY; |
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|
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if (status & GENMASK(st->num_channels - 1, 0)) |
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handle_adc_eoc_trigger(irq, idev); |
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if (status & AT91_ADC_IER_PEN) { |
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at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); |
|
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | |
|
ts_data_irq_mask); |
|
/* Set up period trigger for sampling */ |
|
at91_adc_writel(st, st->registers->trigger_register, |
|
AT91_ADC_TRGR_MOD_PERIOD_TRIG | |
|
AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); |
|
} else if (status & AT91_ADC_IER_NOPEN) { |
|
at91_adc_writel(st, st->registers->trigger_register, 0); |
|
at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | |
|
ts_data_irq_mask); |
|
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); |
|
|
|
input_report_key(st->ts_input, BTN_TOUCH, 0); |
|
input_sync(st->ts_input); |
|
} else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { |
|
/* Now all touchscreen data is ready */ |
|
|
|
if (status & AT91_ADC_ISR_PENS) { |
|
/* validate data by pen contact */ |
|
at91_ts_sample(idev); |
|
} else { |
|
/* triggered by event that is no pen contact, just read |
|
* them to clean the interrupt and discard all. |
|
*/ |
|
at91_adc_readl(st, AT91_ADC_TSXPOSR); |
|
at91_adc_readl(st, AT91_ADC_TSYPOSR); |
|
at91_adc_readl(st, AT91_ADC_TSPRESSR); |
|
} |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int at91_adc_channel_init(struct iio_dev *idev) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
struct iio_chan_spec *chan_array, *timestamp; |
|
int bit, idx = 0; |
|
unsigned long rsvd_mask = 0; |
|
|
|
/* If touchscreen is enable, then reserve the adc channels */ |
|
if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) |
|
rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; |
|
else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) |
|
rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; |
|
|
|
/* set up the channel mask to reserve touchscreen channels */ |
|
st->channels_mask &= ~rsvd_mask; |
|
|
|
idev->num_channels = bitmap_weight(&st->channels_mask, |
|
st->num_channels) + 1; |
|
|
|
chan_array = devm_kzalloc(&idev->dev, |
|
((idev->num_channels + 1) * |
|
sizeof(struct iio_chan_spec)), |
|
GFP_KERNEL); |
|
|
|
if (!chan_array) |
|
return -ENOMEM; |
|
|
|
for_each_set_bit(bit, &st->channels_mask, st->num_channels) { |
|
struct iio_chan_spec *chan = chan_array + idx; |
|
|
|
chan->type = IIO_VOLTAGE; |
|
chan->indexed = 1; |
|
chan->channel = bit; |
|
chan->scan_index = idx; |
|
chan->scan_type.sign = 'u'; |
|
chan->scan_type.realbits = st->res; |
|
chan->scan_type.storagebits = 16; |
|
chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); |
|
chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); |
|
idx++; |
|
} |
|
timestamp = chan_array + idx; |
|
|
|
timestamp->type = IIO_TIMESTAMP; |
|
timestamp->channel = -1; |
|
timestamp->scan_index = idx; |
|
timestamp->scan_type.sign = 's'; |
|
timestamp->scan_type.realbits = 64; |
|
timestamp->scan_type.storagebits = 64; |
|
|
|
idev->channels = chan_array; |
|
return idev->num_channels; |
|
} |
|
|
|
static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, |
|
const struct at91_adc_trigger *triggers, |
|
const char *trigger_name) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
int i; |
|
|
|
for (i = 0; i < st->caps->trigger_number; i++) { |
|
char *name = kasprintf(GFP_KERNEL, |
|
"%s-dev%d-%s", |
|
idev->name, |
|
idev->id, |
|
triggers[i].name); |
|
if (!name) |
|
return -ENOMEM; |
|
|
|
if (strcmp(trigger_name, name) == 0) { |
|
kfree(name); |
|
if (triggers[i].value == 0) |
|
return -EINVAL; |
|
return triggers[i].value; |
|
} |
|
|
|
kfree(name); |
|
} |
|
|
|
return -EINVAL; |
|
} |
|
|
|
static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) |
|
{ |
|
struct iio_dev *idev = iio_trigger_get_drvdata(trig); |
|
struct at91_adc_state *st = iio_priv(idev); |
|
const struct at91_adc_reg_desc *reg = st->registers; |
|
u32 status = at91_adc_readl(st, reg->trigger_register); |
|
int value; |
|
u8 bit; |
|
|
|
value = at91_adc_get_trigger_value_by_name(idev, |
|
st->caps->triggers, |
|
idev->trig->name); |
|
if (value < 0) |
|
return value; |
|
|
|
if (state) { |
|
st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); |
|
if (st->buffer == NULL) |
|
return -ENOMEM; |
|
|
|
at91_adc_writel(st, reg->trigger_register, |
|
status | value); |
|
|
|
for_each_set_bit(bit, idev->active_scan_mask, |
|
st->num_channels) { |
|
struct iio_chan_spec const *chan = idev->channels + bit; |
|
at91_adc_writel(st, AT91_ADC_CHER, |
|
AT91_ADC_CH(chan->channel)); |
|
} |
|
|
|
at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); |
|
|
|
} else { |
|
at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); |
|
|
|
at91_adc_writel(st, reg->trigger_register, |
|
status & ~value); |
|
|
|
for_each_set_bit(bit, idev->active_scan_mask, |
|
st->num_channels) { |
|
struct iio_chan_spec const *chan = idev->channels + bit; |
|
at91_adc_writel(st, AT91_ADC_CHDR, |
|
AT91_ADC_CH(chan->channel)); |
|
} |
|
kfree(st->buffer); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct iio_trigger_ops at91_adc_trigger_ops = { |
|
.set_trigger_state = &at91_adc_configure_trigger, |
|
}; |
|
|
|
static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, |
|
const struct at91_adc_trigger *trigger) |
|
{ |
|
struct iio_trigger *trig; |
|
int ret; |
|
|
|
trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, |
|
idev->id, trigger->name); |
|
if (trig == NULL) |
|
return NULL; |
|
|
|
trig->dev.parent = idev->dev.parent; |
|
iio_trigger_set_drvdata(trig, idev); |
|
trig->ops = &at91_adc_trigger_ops; |
|
|
|
ret = iio_trigger_register(trig); |
|
if (ret) |
|
return NULL; |
|
|
|
return trig; |
|
} |
|
|
|
static int at91_adc_trigger_init(struct iio_dev *idev) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
int i, ret; |
|
|
|
st->trig = devm_kcalloc(&idev->dev, |
|
st->caps->trigger_number, sizeof(*st->trig), |
|
GFP_KERNEL); |
|
|
|
if (st->trig == NULL) { |
|
ret = -ENOMEM; |
|
goto error_ret; |
|
} |
|
|
|
for (i = 0; i < st->caps->trigger_number; i++) { |
|
if (st->caps->triggers[i].is_external && !(st->use_external)) |
|
continue; |
|
|
|
st->trig[i] = at91_adc_allocate_trigger(idev, |
|
st->caps->triggers + i); |
|
if (st->trig[i] == NULL) { |
|
dev_err(&idev->dev, |
|
"Could not allocate trigger %d\n", i); |
|
ret = -ENOMEM; |
|
goto error_trigger; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
error_trigger: |
|
for (i--; i >= 0; i--) { |
|
iio_trigger_unregister(st->trig[i]); |
|
iio_trigger_free(st->trig[i]); |
|
} |
|
error_ret: |
|
return ret; |
|
} |
|
|
|
static void at91_adc_trigger_remove(struct iio_dev *idev) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
int i; |
|
|
|
for (i = 0; i < st->caps->trigger_number; i++) { |
|
iio_trigger_unregister(st->trig[i]); |
|
iio_trigger_free(st->trig[i]); |
|
} |
|
} |
|
|
|
static int at91_adc_buffer_init(struct iio_dev *idev) |
|
{ |
|
return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, |
|
&at91_adc_trigger_handler, NULL); |
|
} |
|
|
|
static void at91_adc_buffer_remove(struct iio_dev *idev) |
|
{ |
|
iio_triggered_buffer_cleanup(idev); |
|
} |
|
|
|
static int at91_adc_read_raw(struct iio_dev *idev, |
|
struct iio_chan_spec const *chan, |
|
int *val, int *val2, long mask) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
int ret; |
|
|
|
switch (mask) { |
|
case IIO_CHAN_INFO_RAW: |
|
mutex_lock(&st->lock); |
|
|
|
st->chnb = chan->channel; |
|
at91_adc_writel(st, AT91_ADC_CHER, |
|
AT91_ADC_CH(chan->channel)); |
|
at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); |
|
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); |
|
|
|
ret = wait_event_interruptible_timeout(st->wq_data_avail, |
|
st->done, |
|
msecs_to_jiffies(1000)); |
|
|
|
/* Disable interrupts, regardless if adc conversion was |
|
* successful or not |
|
*/ |
|
at91_adc_writel(st, AT91_ADC_CHDR, |
|
AT91_ADC_CH(chan->channel)); |
|
at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); |
|
|
|
if (ret > 0) { |
|
/* a valid conversion took place */ |
|
*val = st->last_value; |
|
st->last_value = 0; |
|
st->done = false; |
|
ret = IIO_VAL_INT; |
|
} else if (ret == 0) { |
|
/* conversion timeout */ |
|
dev_err(&idev->dev, "ADC Channel %d timeout.\n", |
|
chan->channel); |
|
ret = -ETIMEDOUT; |
|
} |
|
|
|
mutex_unlock(&st->lock); |
|
return ret; |
|
|
|
case IIO_CHAN_INFO_SCALE: |
|
*val = st->vref_mv; |
|
*val2 = chan->scan_type.realbits; |
|
return IIO_VAL_FRACTIONAL_LOG2; |
|
default: |
|
break; |
|
} |
|
return -EINVAL; |
|
} |
|
|
|
|
|
static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) |
|
{ |
|
/* |
|
* Number of ticks needed to cover the startup time of the ADC |
|
* as defined in the electrical characteristics of the board, |
|
* divided by 8. The formula thus is : |
|
* Startup Time = (ticks + 1) * 8 / ADC Clock |
|
*/ |
|
return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; |
|
} |
|
|
|
static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) |
|
{ |
|
/* |
|
* For sama5d3x and at91sam9x5, the formula changes to: |
|
* Startup Time = <lookup_table_value> / ADC Clock |
|
*/ |
|
static const int startup_lookup[] = { |
|
0, 8, 16, 24, |
|
64, 80, 96, 112, |
|
512, 576, 640, 704, |
|
768, 832, 896, 960 |
|
}; |
|
int i, size = ARRAY_SIZE(startup_lookup); |
|
unsigned int ticks; |
|
|
|
ticks = startup_time * adc_clk_khz / 1000; |
|
for (i = 0; i < size; i++) |
|
if (ticks < startup_lookup[i]) |
|
break; |
|
|
|
ticks = i; |
|
if (ticks == size) |
|
/* Reach the end of lookup table */ |
|
ticks = size - 1; |
|
|
|
return ticks; |
|
} |
|
|
|
static int at91_adc_probe_dt_ts(struct device_node *node, |
|
struct at91_adc_state *st, struct device *dev) |
|
{ |
|
int ret; |
|
u32 prop; |
|
|
|
ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); |
|
if (ret) { |
|
dev_info(dev, "ADC Touch screen is disabled.\n"); |
|
return 0; |
|
} |
|
|
|
switch (prop) { |
|
case 4: |
|
case 5: |
|
st->touchscreen_type = prop; |
|
break; |
|
default: |
|
dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); |
|
return -EINVAL; |
|
} |
|
|
|
if (!st->caps->has_tsmr) |
|
return 0; |
|
prop = 0; |
|
of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); |
|
st->ts_pressure_threshold = prop; |
|
if (st->ts_pressure_threshold) { |
|
return 0; |
|
} else { |
|
dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static const struct iio_info at91_adc_info = { |
|
.read_raw = &at91_adc_read_raw, |
|
}; |
|
|
|
/* Touchscreen related functions */ |
|
static int atmel_ts_open(struct input_dev *dev) |
|
{ |
|
struct at91_adc_state *st = input_get_drvdata(dev); |
|
|
|
if (st->caps->has_tsmr) |
|
at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); |
|
else |
|
at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); |
|
return 0; |
|
} |
|
|
|
static void atmel_ts_close(struct input_dev *dev) |
|
{ |
|
struct at91_adc_state *st = input_get_drvdata(dev); |
|
|
|
if (st->caps->has_tsmr) |
|
at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); |
|
else |
|
at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); |
|
} |
|
|
|
static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
u32 reg = 0; |
|
u32 tssctim = 0; |
|
int i = 0; |
|
|
|
/* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid |
|
* pen detect noise. |
|
* The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock |
|
*/ |
|
st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / |
|
1000, 1); |
|
|
|
while (st->ts_pendbc >> ++i) |
|
; /* Empty! Find the shift offset */ |
|
if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) |
|
st->ts_pendbc = i; |
|
else |
|
st->ts_pendbc = i - 1; |
|
|
|
if (!st->caps->has_tsmr) { |
|
reg = at91_adc_readl(st, AT91_ADC_MR); |
|
reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; |
|
|
|
reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; |
|
at91_adc_writel(st, AT91_ADC_MR, reg); |
|
|
|
reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; |
|
at91_adc_writel(st, AT91_ADC_TSR, reg); |
|
|
|
st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * |
|
adc_clk_khz / 1000) - 1, 1); |
|
|
|
return 0; |
|
} |
|
|
|
/* Touchscreen Switches Closure time needed for allowing the value to |
|
* stabilize. |
|
* Switch Closure Time = (TSSCTIM * 4) ADCClock periods |
|
*/ |
|
tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); |
|
dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n", |
|
adc_clk_khz, tssctim); |
|
|
|
if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) |
|
reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; |
|
else |
|
reg = AT91_ADC_TSMR_TSMODE_5WIRE; |
|
|
|
reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; |
|
reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) |
|
& AT91_ADC_TSMR_TSAV; |
|
reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; |
|
reg |= AT91_ADC_TSMR_NOTSDMA; |
|
reg |= AT91_ADC_TSMR_PENDET_ENA; |
|
reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ |
|
|
|
at91_adc_writel(st, AT91_ADC_TSMR, reg); |
|
|
|
/* Change adc internal resistor value for better pen detection, |
|
* default value is 100 kOhm. |
|
* 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm |
|
* option only available on ES2 and higher |
|
*/ |
|
at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity |
|
& AT91_ADC_ACR_PENDETSENS); |
|
|
|
/* Sample Period Time = (TRGPER + 1) / ADCClock */ |
|
st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * |
|
adc_clk_khz / 1000) - 1, 1); |
|
|
|
return 0; |
|
} |
|
|
|
static int at91_ts_register(struct iio_dev *idev, |
|
struct platform_device *pdev) |
|
{ |
|
struct at91_adc_state *st = iio_priv(idev); |
|
struct input_dev *input; |
|
int ret; |
|
|
|
input = input_allocate_device(); |
|
if (!input) { |
|
dev_err(&idev->dev, "Failed to allocate TS device!\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
input->name = DRIVER_NAME; |
|
input->id.bustype = BUS_HOST; |
|
input->dev.parent = &pdev->dev; |
|
input->open = atmel_ts_open; |
|
input->close = atmel_ts_close; |
|
|
|
__set_bit(EV_ABS, input->evbit); |
|
__set_bit(EV_KEY, input->evbit); |
|
__set_bit(BTN_TOUCH, input->keybit); |
|
if (st->caps->has_tsmr) { |
|
input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, |
|
0, 0); |
|
input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, |
|
0, 0); |
|
input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); |
|
} else { |
|
if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { |
|
dev_err(&pdev->dev, |
|
"This touchscreen controller only support 4 wires\n"); |
|
ret = -EINVAL; |
|
goto err; |
|
} |
|
|
|
input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, |
|
0, 0); |
|
input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, |
|
0, 0); |
|
} |
|
|
|
st->ts_input = input; |
|
input_set_drvdata(input, st); |
|
|
|
ret = input_register_device(input); |
|
if (ret) |
|
goto err; |
|
|
|
return ret; |
|
|
|
err: |
|
input_free_device(st->ts_input); |
|
return ret; |
|
} |
|
|
|
static void at91_ts_unregister(struct at91_adc_state *st) |
|
{ |
|
input_unregister_device(st->ts_input); |
|
} |
|
|
|
static int at91_adc_probe(struct platform_device *pdev) |
|
{ |
|
unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; |
|
struct device_node *node = pdev->dev.of_node; |
|
int ret; |
|
struct iio_dev *idev; |
|
struct at91_adc_state *st; |
|
u32 reg, prop; |
|
char *s; |
|
|
|
idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); |
|
if (!idev) |
|
return -ENOMEM; |
|
|
|
st = iio_priv(idev); |
|
|
|
st->caps = of_device_get_match_data(&pdev->dev); |
|
|
|
st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); |
|
|
|
if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { |
|
dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); |
|
return -EINVAL; |
|
} |
|
st->channels_mask = prop; |
|
|
|
st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); |
|
|
|
if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { |
|
dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); |
|
return -EINVAL; |
|
} |
|
st->startup_time = prop; |
|
|
|
prop = 0; |
|
of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); |
|
st->sample_hold_time = prop; |
|
|
|
if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { |
|
dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); |
|
return -EINVAL; |
|
} |
|
st->vref_mv = prop; |
|
|
|
st->res = st->caps->high_res_bits; |
|
if (st->caps->low_res_bits && |
|
!of_property_read_string(node, "atmel,adc-use-res", (const char **)&s) |
|
&& !strcmp(s, "lowres")) |
|
st->res = st->caps->low_res_bits; |
|
|
|
dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); |
|
|
|
st->registers = &st->caps->registers; |
|
st->num_channels = st->caps->num_channels; |
|
|
|
/* Check if touchscreen is supported. */ |
|
if (st->caps->has_ts) { |
|
ret = at91_adc_probe_dt_ts(node, st, &idev->dev); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
platform_set_drvdata(pdev, idev); |
|
|
|
idev->name = dev_name(&pdev->dev); |
|
idev->modes = INDIO_DIRECT_MODE; |
|
idev->info = &at91_adc_info; |
|
|
|
st->irq = platform_get_irq(pdev, 0); |
|
if (st->irq < 0) |
|
return -ENODEV; |
|
|
|
st->reg_base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(st->reg_base)) |
|
return PTR_ERR(st->reg_base); |
|
|
|
|
|
/* |
|
* Disable all IRQs before setting up the handler |
|
*/ |
|
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); |
|
at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); |
|
|
|
if (st->caps->has_tsmr) |
|
ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, |
|
pdev->dev.driver->name, idev); |
|
else |
|
ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, |
|
pdev->dev.driver->name, idev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); |
|
return ret; |
|
} |
|
|
|
st->clk = devm_clk_get(&pdev->dev, "adc_clk"); |
|
if (IS_ERR(st->clk)) { |
|
dev_err(&pdev->dev, "Failed to get the clock.\n"); |
|
ret = PTR_ERR(st->clk); |
|
goto error_free_irq; |
|
} |
|
|
|
ret = clk_prepare_enable(st->clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, |
|
"Could not prepare or enable the clock.\n"); |
|
goto error_free_irq; |
|
} |
|
|
|
st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); |
|
if (IS_ERR(st->adc_clk)) { |
|
dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); |
|
ret = PTR_ERR(st->adc_clk); |
|
goto error_disable_clk; |
|
} |
|
|
|
ret = clk_prepare_enable(st->adc_clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, |
|
"Could not prepare or enable the ADC clock.\n"); |
|
goto error_disable_clk; |
|
} |
|
|
|
/* |
|
* Prescaler rate computation using the formula from the Atmel's |
|
* datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being |
|
* specified by the electrical characteristics of the board. |
|
*/ |
|
mstrclk = clk_get_rate(st->clk); |
|
adc_clk = clk_get_rate(st->adc_clk); |
|
adc_clk_khz = adc_clk / 1000; |
|
|
|
dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", |
|
mstrclk, adc_clk); |
|
|
|
prsc = (mstrclk / (2 * adc_clk)) - 1; |
|
|
|
if (!st->startup_time) { |
|
dev_err(&pdev->dev, "No startup time available.\n"); |
|
ret = -EINVAL; |
|
goto error_disable_adc_clk; |
|
} |
|
ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); |
|
|
|
/* |
|
* a minimal Sample and Hold Time is necessary for the ADC to guarantee |
|
* the best converted final value between two channels selection |
|
* The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock |
|
*/ |
|
if (st->sample_hold_time > 0) |
|
shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) |
|
- 1, 1); |
|
else |
|
shtim = 0; |
|
|
|
reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; |
|
reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; |
|
if (st->res == st->caps->low_res_bits) |
|
reg |= AT91_ADC_LOWRES; |
|
if (st->sleep_mode) |
|
reg |= AT91_ADC_SLEEP; |
|
reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; |
|
at91_adc_writel(st, AT91_ADC_MR, reg); |
|
|
|
/* Setup the ADC channels available on the board */ |
|
ret = at91_adc_channel_init(idev); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); |
|
goto error_disable_adc_clk; |
|
} |
|
|
|
init_waitqueue_head(&st->wq_data_avail); |
|
mutex_init(&st->lock); |
|
|
|
/* |
|
* Since touch screen will set trigger register as period trigger. So |
|
* when touch screen is enabled, then we have to disable hardware |
|
* trigger for classic adc. |
|
*/ |
|
if (!st->touchscreen_type) { |
|
ret = at91_adc_buffer_init(idev); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); |
|
goto error_disable_adc_clk; |
|
} |
|
|
|
ret = at91_adc_trigger_init(idev); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); |
|
at91_adc_buffer_remove(idev); |
|
goto error_disable_adc_clk; |
|
} |
|
} else { |
|
ret = at91_ts_register(idev, pdev); |
|
if (ret) |
|
goto error_disable_adc_clk; |
|
|
|
at91_ts_hw_init(idev, adc_clk_khz); |
|
} |
|
|
|
ret = iio_device_register(idev); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Couldn't register the device.\n"); |
|
goto error_iio_device_register; |
|
} |
|
|
|
return 0; |
|
|
|
error_iio_device_register: |
|
if (!st->touchscreen_type) { |
|
at91_adc_trigger_remove(idev); |
|
at91_adc_buffer_remove(idev); |
|
} else { |
|
at91_ts_unregister(st); |
|
} |
|
error_disable_adc_clk: |
|
clk_disable_unprepare(st->adc_clk); |
|
error_disable_clk: |
|
clk_disable_unprepare(st->clk); |
|
error_free_irq: |
|
free_irq(st->irq, idev); |
|
return ret; |
|
} |
|
|
|
static int at91_adc_remove(struct platform_device *pdev) |
|
{ |
|
struct iio_dev *idev = platform_get_drvdata(pdev); |
|
struct at91_adc_state *st = iio_priv(idev); |
|
|
|
iio_device_unregister(idev); |
|
if (!st->touchscreen_type) { |
|
at91_adc_trigger_remove(idev); |
|
at91_adc_buffer_remove(idev); |
|
} else { |
|
at91_ts_unregister(st); |
|
} |
|
clk_disable_unprepare(st->adc_clk); |
|
clk_disable_unprepare(st->clk); |
|
free_irq(st->irq, idev); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int at91_adc_suspend(struct device *dev) |
|
{ |
|
struct iio_dev *idev = dev_get_drvdata(dev); |
|
struct at91_adc_state *st = iio_priv(idev); |
|
|
|
pinctrl_pm_select_sleep_state(dev); |
|
clk_disable_unprepare(st->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int at91_adc_resume(struct device *dev) |
|
{ |
|
struct iio_dev *idev = dev_get_drvdata(dev); |
|
struct at91_adc_state *st = iio_priv(idev); |
|
|
|
clk_prepare_enable(st->clk); |
|
pinctrl_pm_select_default_state(dev); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); |
|
|
|
static const struct at91_adc_trigger at91sam9260_triggers[] = { |
|
{ .name = "timer-counter-0", .value = 0x1 }, |
|
{ .name = "timer-counter-1", .value = 0x3 }, |
|
{ .name = "timer-counter-2", .value = 0x5 }, |
|
{ .name = "external", .value = 0xd, .is_external = true }, |
|
}; |
|
|
|
static struct at91_adc_caps at91sam9260_caps = { |
|
.calc_startup_ticks = calc_startup_ticks_9260, |
|
.num_channels = 4, |
|
.low_res_bits = 8, |
|
.high_res_bits = 10, |
|
.registers = { |
|
.channel_base = AT91_ADC_CHR(0), |
|
.drdy_mask = AT91_ADC_DRDY, |
|
.status_register = AT91_ADC_SR, |
|
.trigger_register = AT91_ADC_TRGR_9260, |
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
|
.mr_startup_mask = AT91_ADC_STARTUP_9260, |
|
}, |
|
.triggers = at91sam9260_triggers, |
|
.trigger_number = ARRAY_SIZE(at91sam9260_triggers), |
|
}; |
|
|
|
static const struct at91_adc_trigger at91sam9x5_triggers[] = { |
|
{ .name = "external-rising", .value = 0x1, .is_external = true }, |
|
{ .name = "external-falling", .value = 0x2, .is_external = true }, |
|
{ .name = "external-any", .value = 0x3, .is_external = true }, |
|
{ .name = "continuous", .value = 0x6 }, |
|
}; |
|
|
|
static struct at91_adc_caps at91sam9rl_caps = { |
|
.has_ts = true, |
|
.calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ |
|
.num_channels = 6, |
|
.low_res_bits = 8, |
|
.high_res_bits = 10, |
|
.registers = { |
|
.channel_base = AT91_ADC_CHR(0), |
|
.drdy_mask = AT91_ADC_DRDY, |
|
.status_register = AT91_ADC_SR, |
|
.trigger_register = AT91_ADC_TRGR_9G45, |
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9260, |
|
.mr_startup_mask = AT91_ADC_STARTUP_9G45, |
|
}, |
|
.triggers = at91sam9x5_triggers, |
|
.trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
|
}; |
|
|
|
static struct at91_adc_caps at91sam9g45_caps = { |
|
.has_ts = true, |
|
.calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ |
|
.num_channels = 8, |
|
.low_res_bits = 8, |
|
.high_res_bits = 10, |
|
.registers = { |
|
.channel_base = AT91_ADC_CHR(0), |
|
.drdy_mask = AT91_ADC_DRDY, |
|
.status_register = AT91_ADC_SR, |
|
.trigger_register = AT91_ADC_TRGR_9G45, |
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
|
.mr_startup_mask = AT91_ADC_STARTUP_9G45, |
|
}, |
|
.triggers = at91sam9x5_triggers, |
|
.trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
|
}; |
|
|
|
static struct at91_adc_caps at91sam9x5_caps = { |
|
.has_ts = true, |
|
.has_tsmr = true, |
|
.ts_filter_average = 3, |
|
.ts_pen_detect_sensitivity = 2, |
|
.calc_startup_ticks = calc_startup_ticks_9x5, |
|
.num_channels = 12, |
|
.low_res_bits = 8, |
|
.high_res_bits = 10, |
|
.registers = { |
|
.channel_base = AT91_ADC_CDR0_9X5, |
|
.drdy_mask = AT91_ADC_SR_DRDY_9X5, |
|
.status_register = AT91_ADC_SR_9X5, |
|
.trigger_register = AT91_ADC_TRGR_9X5, |
|
/* prescal mask is same as 9G45 */ |
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
|
.mr_startup_mask = AT91_ADC_STARTUP_9X5, |
|
}, |
|
.triggers = at91sam9x5_triggers, |
|
.trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
|
}; |
|
|
|
static struct at91_adc_caps sama5d3_caps = { |
|
.has_ts = true, |
|
.has_tsmr = true, |
|
.ts_filter_average = 3, |
|
.ts_pen_detect_sensitivity = 2, |
|
.calc_startup_ticks = calc_startup_ticks_9x5, |
|
.num_channels = 12, |
|
.low_res_bits = 0, |
|
.high_res_bits = 12, |
|
.registers = { |
|
.channel_base = AT91_ADC_CDR0_9X5, |
|
.drdy_mask = AT91_ADC_SR_DRDY_9X5, |
|
.status_register = AT91_ADC_SR_9X5, |
|
.trigger_register = AT91_ADC_TRGR_9X5, |
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9G45, |
|
.mr_startup_mask = AT91_ADC_STARTUP_9X5, |
|
}, |
|
.triggers = at91sam9x5_triggers, |
|
.trigger_number = ARRAY_SIZE(at91sam9x5_triggers), |
|
}; |
|
|
|
static const struct of_device_id at91_adc_dt_ids[] = { |
|
{ .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, |
|
{ .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, |
|
{ .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, |
|
{ .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, |
|
{ .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); |
|
|
|
static struct platform_driver at91_adc_driver = { |
|
.probe = at91_adc_probe, |
|
.remove = at91_adc_remove, |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = at91_adc_dt_ids, |
|
.pm = &at91_adc_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(at91_adc_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); |
|
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
|
|
|