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843 lines
21 KiB
843 lines
21 KiB
/* |
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* Copyright (C) 2001-2002 Andre Hedrick <[email protected]> |
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* Copyright (C) 2003 Red Hat |
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* Copyright (C) 2007-2008 MontaVista Software, Inc. |
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* Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz |
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* |
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* May be copied or modified under the terms of the GNU General Public License |
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* |
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* Documentation for CMD680: |
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* http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2 |
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* |
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* Documentation for SiI 3112: |
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* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 |
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* |
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* Errata and other documentation only available under NDA. |
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* |
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* |
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* FAQ Items: |
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* If you are using Marvell SATA-IDE adapters with Maxtor drives |
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* ensure the system is set up for ATA100/UDMA5, not UDMA6. |
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* |
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* If you are using WD drives with SATA bridges you must set the |
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* drive to "Single". "Master" will hang. |
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* |
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* If you have strange problems with nVidia chipset systems please |
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* see the SI support documentation and update your system BIOS |
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* if necessary |
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* |
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* The Dell DRAC4 has some interesting features including effectively hot |
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* unplugging/replugging the virtual CD interface when the DRAC is reset. |
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* This often causes drivers/ide/siimage to panic but is ok with the rather |
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* smarter code in libata. |
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* |
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* TODO: |
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* - VDMA support |
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*/ |
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|
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#include <linux/types.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/ide.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#define DRV_NAME "siimage" |
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|
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/** |
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* pdev_is_sata - check if device is SATA |
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* @pdev: PCI device to check |
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* |
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* Returns true if this is a SATA controller |
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*/ |
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static int pdev_is_sata(struct pci_dev *pdev) |
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{ |
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#ifdef CONFIG_BLK_DEV_IDE_SATA |
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switch (pdev->device) { |
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case PCI_DEVICE_ID_SII_3112: |
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case PCI_DEVICE_ID_SII_1210SA: |
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return 1; |
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case PCI_DEVICE_ID_SII_680: |
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return 0; |
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} |
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BUG(); |
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#endif |
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return 0; |
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} |
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/** |
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* is_sata - check if hwif is SATA |
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* @hwif: interface to check |
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* |
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* Returns true if this is a SATA controller |
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*/ |
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static inline int is_sata(ide_hwif_t *hwif) |
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{ |
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return pdev_is_sata(to_pci_dev(hwif->dev)); |
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} |
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/** |
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* siimage_selreg - return register base |
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* @hwif: interface |
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* @r: config offset |
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* |
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* Turn a config register offset into the right address in either |
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* PCI space or MMIO space to access the control register in question |
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* Thankfully this is a configuration operation, so isn't performance |
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* critical. |
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*/ |
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static unsigned long siimage_selreg(ide_hwif_t *hwif, int r) |
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{ |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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base += 0xA0 + r; |
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if (hwif->host_flags & IDE_HFLAG_MMIO) |
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base += hwif->channel << 6; |
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else |
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base += hwif->channel << 4; |
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return base; |
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} |
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|
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/** |
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* siimage_seldev - return register base |
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* @hwif: interface |
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* @r: config offset |
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* |
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* Turn a config register offset into the right address in either |
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* PCI space or MMIO space to access the control register in question |
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* including accounting for the unit shift. |
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*/ |
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static inline unsigned long siimage_seldev(ide_drive_t *drive, int r) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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u8 unit = drive->dn & 1; |
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base += 0xA0 + r; |
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if (hwif->host_flags & IDE_HFLAG_MMIO) |
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base += hwif->channel << 6; |
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else |
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base += hwif->channel << 4; |
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base |= unit << unit; |
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return base; |
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} |
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static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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u8 tmp = 0; |
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if (host->host_priv) |
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tmp = readb((void __iomem *)addr); |
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else |
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pci_read_config_byte(dev, addr, &tmp); |
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return tmp; |
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} |
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static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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u16 tmp = 0; |
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if (host->host_priv) |
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tmp = readw((void __iomem *)addr); |
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else |
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pci_read_config_word(dev, addr, &tmp); |
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return tmp; |
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} |
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static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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if (host->host_priv) |
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writeb(val, (void __iomem *)addr); |
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else |
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pci_write_config_byte(dev, addr, val); |
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} |
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static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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if (host->host_priv) |
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writew(val, (void __iomem *)addr); |
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else |
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pci_write_config_word(dev, addr, val); |
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} |
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static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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if (host->host_priv) |
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writel(val, (void __iomem *)addr); |
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else |
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pci_write_config_dword(dev, addr, val); |
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} |
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/** |
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* sil_udma_filter - compute UDMA mask |
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* @drive: IDE device |
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* |
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* Compute the available UDMA speeds for the device on the interface. |
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* |
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* For the CMD680 this depends on the clocking mode (scsc), for the |
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* SI3112 SATA controller life is a bit simpler. |
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*/ |
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static u8 sil_pata_udma_filter(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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u8 scsc, mask = 0; |
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base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A; |
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scsc = sil_ioread8(dev, base); |
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switch (scsc & 0x30) { |
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case 0x10: /* 133 */ |
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mask = ATA_UDMA6; |
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break; |
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case 0x20: /* 2xPCI */ |
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mask = ATA_UDMA6; |
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break; |
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case 0x00: /* 100 */ |
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mask = ATA_UDMA5; |
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break; |
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default: /* Disabled ? */ |
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BUG(); |
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} |
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return mask; |
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} |
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static u8 sil_sata_udma_filter(ide_drive_t *drive) |
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{ |
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char *m = (char *)&drive->id[ATA_ID_PROD]; |
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return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6; |
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} |
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/** |
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* sil_set_pio_mode - set host controller for PIO mode |
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* @hwif: port |
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* @drive: drive |
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* |
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* Load the timing settings for this device mode into the |
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* controller. |
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*/ |
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static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 }; |
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static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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ide_drive_t *pair = ide_get_pair_dev(drive); |
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u32 speedt = 0; |
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u16 speedp = 0; |
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unsigned long addr = siimage_seldev(drive, 0x04); |
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unsigned long tfaddr = siimage_selreg(hwif, 0x02); |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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const u8 pio = drive->pio_mode - XFER_PIO_0; |
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u8 tf_pio = pio; |
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u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
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u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) |
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: (mmio ? 0xB4 : 0x80); |
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u8 mode = 0; |
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u8 unit = drive->dn & 1; |
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/* trim *taskfile* PIO to the slowest of the master/slave */ |
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if (pair) { |
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u8 pair_pio = pair->pio_mode - XFER_PIO_0; |
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if (pair_pio < tf_pio) |
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tf_pio = pair_pio; |
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} |
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/* cheat for now and use the docs */ |
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speedp = data_speed[pio]; |
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speedt = tf_speed[tf_pio]; |
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sil_iowrite16(dev, speedp, addr); |
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sil_iowrite16(dev, speedt, tfaddr); |
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/* now set up IORDY */ |
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speedp = sil_ioread16(dev, tfaddr - 2); |
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speedp &= ~0x200; |
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mode = sil_ioread8(dev, base + addr_mask); |
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mode &= ~(unit ? 0x30 : 0x03); |
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if (ide_pio_need_iordy(drive, pio)) { |
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speedp |= 0x200; |
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mode |= unit ? 0x10 : 0x01; |
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} |
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sil_iowrite16(dev, speedp, tfaddr - 2); |
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sil_iowrite8(dev, mode, base + addr_mask); |
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} |
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/** |
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* sil_set_dma_mode - set host controller for DMA mode |
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* @hwif: port |
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* @drive: drive |
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* |
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* Tune the SiI chipset for the desired DMA mode. |
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*/ |
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static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }; |
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static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 }; |
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static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 }; |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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u16 ultra = 0, multi = 0; |
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u8 mode = 0, unit = drive->dn & 1; |
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u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
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u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) |
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: (mmio ? 0xB4 : 0x80); |
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unsigned long ma = siimage_seldev(drive, 0x08); |
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unsigned long ua = siimage_seldev(drive, 0x0C); |
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const u8 speed = drive->dma_mode; |
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scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); |
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mode = sil_ioread8 (dev, base + addr_mask); |
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multi = sil_ioread16(dev, ma); |
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ultra = sil_ioread16(dev, ua); |
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mode &= ~(unit ? 0x30 : 0x03); |
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ultra &= ~0x3F; |
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scsc = ((scsc & 0x30) == 0x00) ? 0 : 1; |
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scsc = is_sata(hwif) ? 1 : scsc; |
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if (speed >= XFER_UDMA_0) { |
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multi = dma[2]; |
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ultra |= scsc ? ultra6[speed - XFER_UDMA_0] : |
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ultra5[speed - XFER_UDMA_0]; |
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mode |= unit ? 0x30 : 0x03; |
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} else { |
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multi = dma[speed - XFER_MW_DMA_0]; |
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mode |= unit ? 0x20 : 0x02; |
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} |
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sil_iowrite8 (dev, mode, base + addr_mask); |
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sil_iowrite16(dev, multi, ma); |
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sil_iowrite16(dev, ultra, ua); |
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} |
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static int sil_test_irq(ide_hwif_t *hwif) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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unsigned long addr = siimage_selreg(hwif, 1); |
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u8 val = sil_ioread8(dev, addr); |
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/* Return 1 if INTRQ asserted */ |
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return (val & 8) ? 1 : 0; |
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} |
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/** |
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* siimage_mmio_dma_test_irq - check we caused an IRQ |
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* @drive: drive we are testing |
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* |
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* Check if we caused an IDE DMA interrupt. We may also have caused |
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* SATA status interrupts, if so we clean them up and continue. |
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*/ |
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static int siimage_mmio_dma_test_irq(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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void __iomem *sata_error_addr |
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= (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET]; |
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if (sata_error_addr) { |
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unsigned long base = (unsigned long)hwif->hwif_data; |
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u32 ext_stat = readl((void __iomem *)(base + 0x10)); |
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u8 watchdog = 0; |
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if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) { |
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u32 sata_error = readl(sata_error_addr); |
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writel(sata_error, sata_error_addr); |
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watchdog = (sata_error & 0x00680000) ? 1 : 0; |
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printk(KERN_WARNING "%s: sata_error = 0x%08x, " |
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"watchdog = %d, %s\n", |
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drive->name, sata_error, watchdog, __func__); |
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} else |
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watchdog = (ext_stat & 0x8000) ? 1 : 0; |
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ext_stat >>= 16; |
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if (!(ext_stat & 0x0404) && !watchdog) |
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return 0; |
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} |
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/* return 1 if INTR asserted */ |
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if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4) |
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return 1; |
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return 0; |
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} |
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static int siimage_dma_test_irq(ide_drive_t *drive) |
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{ |
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if (drive->hwif->host_flags & IDE_HFLAG_MMIO) |
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return siimage_mmio_dma_test_irq(drive); |
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else |
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return ide_dma_test_irq(drive); |
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} |
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/** |
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* sil_sata_reset_poll - wait for SATA reset |
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* @drive: drive we are resetting |
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* |
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* Poll the SATA phy and see whether it has come back from the dead |
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* yet. |
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*/ |
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static blk_status_t sil_sata_reset_poll(ide_drive_t *drive) |
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{ |
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ide_hwif_t *hwif = drive->hwif; |
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void __iomem *sata_status_addr |
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= (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET]; |
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if (sata_status_addr) { |
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/* SATA Status is available only when in MMIO mode */ |
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u32 sata_stat = readl(sata_status_addr); |
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if ((sata_stat & 0x03) != 0x03) { |
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printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n", |
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hwif->name, sata_stat); |
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return BLK_STS_IOERR; |
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} |
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} |
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return BLK_STS_OK; |
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} |
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/** |
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* sil_sata_pre_reset - reset hook |
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* @drive: IDE device being reset |
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* |
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* For the SATA devices we need to handle recalibration/geometry |
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* differently |
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*/ |
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static void sil_sata_pre_reset(ide_drive_t *drive) |
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{ |
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if (drive->media == ide_disk) { |
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drive->special_flags &= |
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~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE); |
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} |
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} |
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|
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/** |
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* init_chipset_siimage - set up an SI device |
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* @dev: PCI device |
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* |
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* Perform the initial PCI set up for this device. Attempt to switch |
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* to 133 MHz clocking if the system isn't already set up to do it. |
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*/ |
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static int init_chipset_siimage(struct pci_dev *dev) |
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{ |
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struct ide_host *host = pci_get_drvdata(dev); |
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void __iomem *ioaddr = host->host_priv; |
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unsigned long base, scsc_addr; |
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u8 rev = dev->revision, tmp; |
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255); |
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if (ioaddr) |
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pci_set_master(dev); |
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base = (unsigned long)ioaddr; |
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if (ioaddr && pdev_is_sata(dev)) { |
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u32 tmp32, irq_mask; |
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/* make sure IDE0/1 interrupts are not masked */ |
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irq_mask = (1 << 22) | (1 << 23); |
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tmp32 = readl(ioaddr + 0x48); |
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if (tmp32 & irq_mask) { |
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tmp32 &= ~irq_mask; |
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writel(tmp32, ioaddr + 0x48); |
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readl(ioaddr + 0x48); /* flush */ |
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} |
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writel(0, ioaddr + 0x148); |
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writel(0, ioaddr + 0x1C8); |
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} |
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sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80); |
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sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84); |
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scsc_addr = base ? (base + 0x4A) : 0x8A; |
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tmp = sil_ioread8(dev, scsc_addr); |
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switch (tmp & 0x30) { |
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case 0x00: |
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/* On 100 MHz clocking, try and switch to 133 MHz */ |
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sil_iowrite8(dev, tmp | 0x10, scsc_addr); |
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break; |
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case 0x30: |
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/* Clocking is disabled, attempt to force 133MHz clocking. */ |
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sil_iowrite8(dev, tmp & ~0x20, scsc_addr); |
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case 0x10: |
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/* On 133Mhz clocking. */ |
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break; |
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case 0x20: |
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/* On PCIx2 clocking. */ |
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break; |
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} |
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tmp = sil_ioread8(dev, scsc_addr); |
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sil_iowrite8 (dev, 0x72, base + 0xA1); |
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sil_iowrite16(dev, 0x328A, base + 0xA2); |
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sil_iowrite32(dev, 0x62DD62DD, base + 0xA4); |
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sil_iowrite32(dev, 0x43924392, base + 0xA8); |
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sil_iowrite32(dev, 0x40094009, base + 0xAC); |
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sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1); |
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sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2); |
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sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4); |
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sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8); |
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sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC); |
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|
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if (base && pdev_is_sata(dev)) { |
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writel(0xFFFF0000, ioaddr + 0x108); |
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writel(0xFFFF0000, ioaddr + 0x188); |
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writel(0x00680000, ioaddr + 0x148); |
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writel(0x00680000, ioaddr + 0x1C8); |
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} |
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|
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/* report the clocking mode of the controller */ |
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if (!pdev_is_sata(dev)) { |
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static const char *clk_str[] = |
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{ "== 100", "== 133", "== 2X PCI", "DISABLED!" }; |
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|
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tmp >>= 4; |
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printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n", |
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pci_name(dev), clk_str[tmp & 3]); |
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} |
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|
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return 0; |
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} |
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|
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/** |
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* init_mmio_iops_siimage - set up the iops for MMIO |
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* @hwif: interface to set up |
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* |
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* The basic setup here is fairly simple, we can use standard MMIO |
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* operations. However we do have to set the taskfile register offsets |
|
* by hand as there isn't a standard defined layout for them this time. |
|
* |
|
* The hardware supports buffered taskfiles and also some rather nice |
|
* extended PRD tables. For better SI3112 support use the libata driver |
|
*/ |
|
|
|
static void init_mmio_iops_siimage(ide_hwif_t *hwif) |
|
{ |
|
struct pci_dev *dev = to_pci_dev(hwif->dev); |
|
struct ide_host *host = pci_get_drvdata(dev); |
|
void *addr = host->host_priv; |
|
u8 ch = hwif->channel; |
|
struct ide_io_ports *io_ports = &hwif->io_ports; |
|
unsigned long base; |
|
|
|
/* |
|
* Fill in the basic hwif bits |
|
*/ |
|
hwif->host_flags |= IDE_HFLAG_MMIO; |
|
|
|
hwif->hwif_data = addr; |
|
|
|
/* |
|
* Now set up the hw. We have to do this ourselves as the |
|
* MMIO layout isn't the same as the standard port based I/O. |
|
*/ |
|
memset(io_ports, 0, sizeof(*io_ports)); |
|
|
|
base = (unsigned long)addr; |
|
if (ch) |
|
base += 0xC0; |
|
else |
|
base += 0x80; |
|
|
|
/* |
|
* The buffered task file doesn't have status/control, so we |
|
* can't currently use it sanely since we want to use LBA48 mode. |
|
*/ |
|
io_ports->data_addr = base; |
|
io_ports->error_addr = base + 1; |
|
io_ports->nsect_addr = base + 2; |
|
io_ports->lbal_addr = base + 3; |
|
io_ports->lbam_addr = base + 4; |
|
io_ports->lbah_addr = base + 5; |
|
io_ports->device_addr = base + 6; |
|
io_ports->status_addr = base + 7; |
|
io_ports->ctl_addr = base + 10; |
|
|
|
if (pdev_is_sata(dev)) { |
|
base = (unsigned long)addr; |
|
if (ch) |
|
base += 0x80; |
|
hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104; |
|
hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108; |
|
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100; |
|
} |
|
|
|
hwif->irq = dev->irq; |
|
|
|
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00); |
|
} |
|
|
|
static int is_dev_seagate_sata(ide_drive_t *drive) |
|
{ |
|
const char *s = (const char *)&drive->id[ATA_ID_PROD]; |
|
unsigned len = strnlen(s, ATA_ID_PROD_LEN); |
|
|
|
if ((len > 4) && (!memcmp(s, "ST", 2))) |
|
if ((!memcmp(s + len - 2, "AS", 2)) || |
|
(!memcmp(s + len - 3, "ASL", 3))) { |
|
printk(KERN_INFO "%s: applying pessimistic Seagate " |
|
"errata fix\n", drive->name); |
|
return 1; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* sil_quirkproc - post probe fixups |
|
* @drive: drive |
|
* |
|
* Called after drive probe we use this to decide whether the |
|
* Seagate fixup must be applied. This used to be in init_iops but |
|
* that can occur before we know what drives are present. |
|
*/ |
|
|
|
static void sil_quirkproc(ide_drive_t *drive) |
|
{ |
|
ide_hwif_t *hwif = drive->hwif; |
|
|
|
/* Try and rise the rqsize */ |
|
if (!is_sata(hwif) || !is_dev_seagate_sata(drive)) |
|
hwif->rqsize = 128; |
|
} |
|
|
|
/** |
|
* init_iops_siimage - set up iops |
|
* @hwif: interface to set up |
|
* |
|
* Do the basic setup for the SIIMAGE hardware interface |
|
* and then do the MMIO setup if we can. This is the first |
|
* look in we get for setting up the hwif so that we |
|
* can get the iops right before using them. |
|
*/ |
|
|
|
static void init_iops_siimage(ide_hwif_t *hwif) |
|
{ |
|
struct ide_host *host = dev_get_drvdata(hwif->dev); |
|
|
|
hwif->hwif_data = NULL; |
|
|
|
/* Pessimal until we finish probing */ |
|
hwif->rqsize = 15; |
|
|
|
if (host->host_priv) |
|
init_mmio_iops_siimage(hwif); |
|
} |
|
|
|
/** |
|
* sil_cable_detect - cable detection |
|
* @hwif: interface to check |
|
* |
|
* Check for the presence of an ATA66 capable cable on the interface. |
|
*/ |
|
|
|
static u8 sil_cable_detect(ide_hwif_t *hwif) |
|
{ |
|
struct pci_dev *dev = to_pci_dev(hwif->dev); |
|
unsigned long addr = siimage_selreg(hwif, 0); |
|
u8 ata66 = sil_ioread8(dev, addr); |
|
|
|
return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; |
|
} |
|
|
|
static const struct ide_port_ops sil_pata_port_ops = { |
|
.set_pio_mode = sil_set_pio_mode, |
|
.set_dma_mode = sil_set_dma_mode, |
|
.quirkproc = sil_quirkproc, |
|
.test_irq = sil_test_irq, |
|
.udma_filter = sil_pata_udma_filter, |
|
.cable_detect = sil_cable_detect, |
|
}; |
|
|
|
static const struct ide_port_ops sil_sata_port_ops = { |
|
.set_pio_mode = sil_set_pio_mode, |
|
.set_dma_mode = sil_set_dma_mode, |
|
.reset_poll = sil_sata_reset_poll, |
|
.pre_reset = sil_sata_pre_reset, |
|
.quirkproc = sil_quirkproc, |
|
.test_irq = sil_test_irq, |
|
.udma_filter = sil_sata_udma_filter, |
|
.cable_detect = sil_cable_detect, |
|
}; |
|
|
|
static const struct ide_dma_ops sil_dma_ops = { |
|
.dma_host_set = ide_dma_host_set, |
|
.dma_setup = ide_dma_setup, |
|
.dma_start = ide_dma_start, |
|
.dma_end = ide_dma_end, |
|
.dma_test_irq = siimage_dma_test_irq, |
|
.dma_timer_expiry = ide_dma_sff_timer_expiry, |
|
.dma_lost_irq = ide_dma_lost_irq, |
|
.dma_sff_read_status = ide_dma_sff_read_status, |
|
}; |
|
|
|
#define DECLARE_SII_DEV(p_ops) \ |
|
{ \ |
|
.name = DRV_NAME, \ |
|
.init_chipset = init_chipset_siimage, \ |
|
.init_iops = init_iops_siimage, \ |
|
.port_ops = p_ops, \ |
|
.dma_ops = &sil_dma_ops, \ |
|
.pio_mask = ATA_PIO4, \ |
|
.mwdma_mask = ATA_MWDMA2, \ |
|
.udma_mask = ATA_UDMA6, \ |
|
} |
|
|
|
static const struct ide_port_info siimage_chipsets[] = { |
|
/* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops), |
|
/* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops) |
|
}; |
|
|
|
/** |
|
* siimage_init_one - PCI layer discovery entry |
|
* @dev: PCI device |
|
* @id: ident table entry |
|
* |
|
* Called by the PCI code when it finds an SiI680 or SiI3112 controller. |
|
* We then use the IDE PCI generic helper to do most of the work. |
|
*/ |
|
|
|
static int siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
|
{ |
|
void __iomem *ioaddr = NULL; |
|
resource_size_t bar5 = pci_resource_start(dev, 5); |
|
unsigned long barsize = pci_resource_len(dev, 5); |
|
int rc; |
|
struct ide_port_info d; |
|
u8 idx = id->driver_data; |
|
u8 BA5_EN; |
|
|
|
d = siimage_chipsets[idx]; |
|
|
|
if (idx) { |
|
static int first = 1; |
|
|
|
if (first) { |
|
printk(KERN_INFO DRV_NAME ": For full SATA support you " |
|
"should use the libata sata_sil module.\n"); |
|
first = 0; |
|
} |
|
|
|
d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
|
} |
|
|
|
rc = pci_enable_device(dev); |
|
if (rc) |
|
return rc; |
|
|
|
pci_read_config_byte(dev, 0x8A, &BA5_EN); |
|
if ((BA5_EN & 0x01) || bar5) { |
|
/* |
|
* Drop back to PIO if we can't map the MMIO. Some systems |
|
* seem to get terminally confused in the PCI spaces. |
|
*/ |
|
if (!request_mem_region(bar5, barsize, d.name)) { |
|
printk(KERN_WARNING DRV_NAME " %s: MMIO ports not " |
|
"available\n", pci_name(dev)); |
|
} else { |
|
ioaddr = pci_ioremap_bar(dev, 5); |
|
if (ioaddr == NULL) |
|
release_mem_region(bar5, barsize); |
|
} |
|
} |
|
|
|
rc = ide_pci_init_one(dev, &d, ioaddr); |
|
if (rc) { |
|
if (ioaddr) { |
|
iounmap(ioaddr); |
|
release_mem_region(bar5, barsize); |
|
} |
|
pci_disable_device(dev); |
|
} |
|
|
|
return rc; |
|
} |
|
|
|
static void siimage_remove(struct pci_dev *dev) |
|
{ |
|
struct ide_host *host = pci_get_drvdata(dev); |
|
void __iomem *ioaddr = host->host_priv; |
|
|
|
ide_pci_remove(dev); |
|
|
|
if (ioaddr) { |
|
resource_size_t bar5 = pci_resource_start(dev, 5); |
|
unsigned long barsize = pci_resource_len(dev, 5); |
|
|
|
iounmap(ioaddr); |
|
release_mem_region(bar5, barsize); |
|
} |
|
|
|
pci_disable_device(dev); |
|
} |
|
|
|
static const struct pci_device_id siimage_pci_tbl[] = { |
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 }, |
|
#ifdef CONFIG_BLK_DEV_IDE_SATA |
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 }, |
|
{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 }, |
|
#endif |
|
{ 0, }, |
|
}; |
|
MODULE_DEVICE_TABLE(pci, siimage_pci_tbl); |
|
|
|
static struct pci_driver siimage_pci_driver = { |
|
.name = "SiI_IDE", |
|
.id_table = siimage_pci_tbl, |
|
.probe = siimage_init_one, |
|
.remove = siimage_remove, |
|
.suspend = ide_pci_suspend, |
|
.resume = ide_pci_resume, |
|
}; |
|
|
|
static int __init siimage_ide_init(void) |
|
{ |
|
return ide_pci_register_driver(&siimage_pci_driver); |
|
} |
|
|
|
static void __exit siimage_ide_exit(void) |
|
{ |
|
pci_unregister_driver(&siimage_pci_driver); |
|
} |
|
|
|
module_init(siimage_ide_init); |
|
module_exit(siimage_ide_exit); |
|
|
|
MODULE_AUTHOR("Andre Hedrick, Alan Cox"); |
|
MODULE_DESCRIPTION("PCI driver module for SiI IDE"); |
|
MODULE_LICENSE("GPL");
|
|
|