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718 lines
16 KiB
718 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* exynos_ppmu.c - Exynos PPMU (Platform Performance Monitoring Unit) support |
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* |
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* Copyright (c) 2014-2015 Samsung Electronics Co., Ltd. |
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* Author : Chanwoo Choi <[email protected]> |
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* |
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* This driver is based on drivers/devfreq/exynos/exynos_ppmu.c |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/suspend.h> |
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#include <linux/devfreq-event.h> |
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|
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#include "exynos-ppmu.h" |
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|
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enum exynos_ppmu_type { |
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EXYNOS_TYPE_PPMU, |
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EXYNOS_TYPE_PPMU_V2, |
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}; |
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struct exynos_ppmu_data { |
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struct clk *clk; |
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}; |
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struct exynos_ppmu { |
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struct devfreq_event_dev **edev; |
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struct devfreq_event_desc *desc; |
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unsigned int num_events; |
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struct device *dev; |
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struct regmap *regmap; |
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struct exynos_ppmu_data ppmu; |
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enum exynos_ppmu_type ppmu_type; |
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}; |
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#define PPMU_EVENT(name) \ |
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{ "ppmu-event0-"#name, PPMU_PMNCNT0 }, \ |
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{ "ppmu-event1-"#name, PPMU_PMNCNT1 }, \ |
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{ "ppmu-event2-"#name, PPMU_PMNCNT2 }, \ |
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{ "ppmu-event3-"#name, PPMU_PMNCNT3 } |
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static struct __exynos_ppmu_events { |
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char *name; |
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int id; |
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} ppmu_events[] = { |
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/* For Exynos3250, Exynos4 and Exynos5260 */ |
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PPMU_EVENT(g3d), |
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PPMU_EVENT(fsys), |
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|
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/* For Exynos4 SoCs and Exynos3250 */ |
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PPMU_EVENT(dmc0), |
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PPMU_EVENT(dmc1), |
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PPMU_EVENT(cpu), |
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PPMU_EVENT(rightbus), |
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PPMU_EVENT(leftbus), |
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PPMU_EVENT(lcd0), |
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PPMU_EVENT(camif), |
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/* Only for Exynos3250 and Exynos5260 */ |
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PPMU_EVENT(mfc), |
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/* Only for Exynos4 SoCs */ |
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PPMU_EVENT(mfc-left), |
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PPMU_EVENT(mfc-right), |
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/* Only for Exynos5260 SoCs */ |
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PPMU_EVENT(drex0-s0), |
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PPMU_EVENT(drex0-s1), |
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PPMU_EVENT(drex1-s0), |
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PPMU_EVENT(drex1-s1), |
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PPMU_EVENT(eagle), |
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PPMU_EVENT(kfc), |
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PPMU_EVENT(isp), |
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PPMU_EVENT(fimc), |
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PPMU_EVENT(gscl), |
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PPMU_EVENT(mscl), |
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PPMU_EVENT(fimd0x), |
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PPMU_EVENT(fimd1x), |
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/* Only for Exynos5433 SoCs */ |
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PPMU_EVENT(d0-cpu), |
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PPMU_EVENT(d0-general), |
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PPMU_EVENT(d0-rt), |
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PPMU_EVENT(d1-cpu), |
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PPMU_EVENT(d1-general), |
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PPMU_EVENT(d1-rt), |
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/* For Exynos5422 SoC */ |
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PPMU_EVENT(dmc0_0), |
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PPMU_EVENT(dmc0_1), |
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PPMU_EVENT(dmc1_0), |
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PPMU_EVENT(dmc1_1), |
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}; |
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static int __exynos_ppmu_find_ppmu_id(const char *edev_name) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(ppmu_events); i++) |
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if (!strcmp(edev_name, ppmu_events[i].name)) |
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return ppmu_events[i].id; |
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return -EINVAL; |
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} |
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static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) |
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{ |
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return __exynos_ppmu_find_ppmu_id(edev->desc->name); |
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} |
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/* |
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* The devfreq-event ops structure for PPMU v1.1 |
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*/ |
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static int exynos_ppmu_disable(struct devfreq_event_dev *edev) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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int ret; |
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u32 pmnc; |
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/* Disable all counters */ |
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ret = regmap_write(info->regmap, PPMU_CNTENC, |
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PPMU_CCNT_MASK | |
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PPMU_PMCNT0_MASK | |
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PPMU_PMCNT1_MASK | |
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PPMU_PMCNT2_MASK | |
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PPMU_PMCNT3_MASK); |
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if (ret < 0) |
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return ret; |
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/* Disable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~PPMU_PMNC_ENABLE_MASK; |
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int exynos_ppmu_set_event(struct devfreq_event_dev *edev) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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int id = exynos_ppmu_find_ppmu_id(edev); |
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int ret; |
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u32 pmnc, cntens; |
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if (id < 0) |
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return id; |
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/* Enable specific counter */ |
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ret = regmap_read(info->regmap, PPMU_CNTENS, &cntens); |
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if (ret < 0) |
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return ret; |
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cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); |
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ret = regmap_write(info->regmap, PPMU_CNTENS, cntens); |
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if (ret < 0) |
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return ret; |
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/* Set the event of proper data type monitoring */ |
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ret = regmap_write(info->regmap, PPMU_BEVTxSEL(id), |
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edev->desc->event_type); |
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if (ret < 0) |
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return ret; |
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/* Reset cycle counter/performance counter and enable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~(PPMU_PMNC_ENABLE_MASK |
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| PPMU_PMNC_COUNTER_RESET_MASK |
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| PPMU_PMNC_CC_RESET_MASK); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT); |
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int exynos_ppmu_get_event(struct devfreq_event_dev *edev, |
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struct devfreq_event_data *edata) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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int id = exynos_ppmu_find_ppmu_id(edev); |
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unsigned int total_count, load_count; |
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unsigned int pmcnt3_high, pmcnt3_low; |
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unsigned int pmnc, cntenc; |
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int ret; |
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if (id < 0) |
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return -EINVAL; |
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/* Disable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~PPMU_PMNC_ENABLE_MASK; |
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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/* Read cycle count */ |
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ret = regmap_read(info->regmap, PPMU_CCNT, &total_count); |
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if (ret < 0) |
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return ret; |
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edata->total_count = total_count; |
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/* Read performance count */ |
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switch (id) { |
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case PPMU_PMNCNT0: |
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case PPMU_PMNCNT1: |
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case PPMU_PMNCNT2: |
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ret = regmap_read(info->regmap, PPMU_PMNCT(id), &load_count); |
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if (ret < 0) |
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return ret; |
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edata->load_count = load_count; |
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break; |
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case PPMU_PMNCNT3: |
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ret = regmap_read(info->regmap, PPMU_PMCNT3_HIGH, &pmcnt3_high); |
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if (ret < 0) |
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return ret; |
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ret = regmap_read(info->regmap, PPMU_PMCNT3_LOW, &pmcnt3_low); |
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if (ret < 0) |
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return ret; |
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edata->load_count = ((pmcnt3_high << 8) | pmcnt3_low); |
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break; |
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default: |
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return -EINVAL; |
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} |
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/* Disable specific counter */ |
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ret = regmap_read(info->regmap, PPMU_CNTENC, &cntenc); |
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if (ret < 0) |
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return ret; |
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cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); |
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ret = regmap_write(info->regmap, PPMU_CNTENC, cntenc); |
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if (ret < 0) |
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return ret; |
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dev_dbg(&edev->dev, "%s (event: %ld/%ld)\n", edev->desc->name, |
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edata->load_count, edata->total_count); |
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return 0; |
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} |
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static const struct devfreq_event_ops exynos_ppmu_ops = { |
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.disable = exynos_ppmu_disable, |
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.set_event = exynos_ppmu_set_event, |
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.get_event = exynos_ppmu_get_event, |
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}; |
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/* |
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* The devfreq-event ops structure for PPMU v2.0 |
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*/ |
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static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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int ret; |
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u32 pmnc, clear; |
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/* Disable all counters */ |
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clear = (PPMU_CCNT_MASK | PPMU_PMCNT0_MASK | PPMU_PMCNT1_MASK |
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| PPMU_PMCNT2_MASK | PPMU_PMCNT3_MASK); |
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ret = regmap_write(info->regmap, PPMU_V2_FLAG, clear); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_INTENC, clear); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CNTENC, clear); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CNT_RESET, clear); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG0, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG1, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG2, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CIG_RESULT, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CNT_AUTO, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV0_TYPE, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV1_TYPE, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV2_TYPE, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV3_TYPE, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_SM_ID_V, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_SM_ID_A, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_V, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_A, 0x0); |
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if (ret < 0) |
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return ret; |
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ret = regmap_write(info->regmap, PPMU_V2_INTERRUPT_RESET, 0x0); |
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if (ret < 0) |
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return ret; |
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/* Disable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~PPMU_PMNC_ENABLE_MASK; |
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int exynos_ppmu_v2_set_event(struct devfreq_event_dev *edev) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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unsigned int pmnc, cntens; |
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int id = exynos_ppmu_find_ppmu_id(edev); |
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int ret; |
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/* Enable all counters */ |
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ret = regmap_read(info->regmap, PPMU_V2_CNTENS, &cntens); |
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if (ret < 0) |
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return ret; |
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cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); |
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ret = regmap_write(info->regmap, PPMU_V2_CNTENS, cntens); |
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if (ret < 0) |
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return ret; |
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/* Set the event of proper data type monitoring */ |
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ret = regmap_write(info->regmap, PPMU_V2_CH_EVx_TYPE(id), |
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edev->desc->event_type); |
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if (ret < 0) |
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return ret; |
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/* Reset cycle counter/performance counter and enable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~(PPMU_PMNC_ENABLE_MASK |
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| PPMU_PMNC_COUNTER_RESET_MASK |
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| PPMU_PMNC_CC_RESET_MASK |
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| PPMU_PMNC_CC_DIVIDER_MASK |
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| PPMU_V2_PMNC_START_MODE_MASK); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT); |
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT); |
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pmnc |= (PPMU_V2_MODE_MANUAL << PPMU_V2_PMNC_START_MODE_SHIFT); |
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int exynos_ppmu_v2_get_event(struct devfreq_event_dev *edev, |
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struct devfreq_event_data *edata) |
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{ |
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev); |
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int id = exynos_ppmu_find_ppmu_id(edev); |
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int ret; |
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unsigned int pmnc, cntenc; |
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unsigned int pmcnt_high, pmcnt_low; |
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unsigned int total_count, count; |
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unsigned long load_count = 0; |
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/* Disable PPMU */ |
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc); |
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if (ret < 0) |
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return ret; |
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pmnc &= ~PPMU_PMNC_ENABLE_MASK; |
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc); |
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if (ret < 0) |
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return ret; |
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|
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/* Read cycle count and performance count */ |
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ret = regmap_read(info->regmap, PPMU_V2_CCNT, &total_count); |
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if (ret < 0) |
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return ret; |
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edata->total_count = total_count; |
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switch (id) { |
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case PPMU_PMNCNT0: |
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case PPMU_PMNCNT1: |
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case PPMU_PMNCNT2: |
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ret = regmap_read(info->regmap, PPMU_V2_PMNCT(id), &count); |
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if (ret < 0) |
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return ret; |
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load_count = count; |
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break; |
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case PPMU_PMNCNT3: |
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ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_HIGH, |
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&pmcnt_high); |
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if (ret < 0) |
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return ret; |
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ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_LOW, &pmcnt_low); |
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if (ret < 0) |
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return ret; |
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load_count = ((u64)((pmcnt_high & 0xff)) << 32)+ (u64)pmcnt_low; |
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break; |
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} |
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edata->load_count = load_count; |
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|
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/* Disable all counters */ |
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ret = regmap_read(info->regmap, PPMU_V2_CNTENC, &cntenc); |
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if (ret < 0) |
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return 0; |
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cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id)); |
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ret = regmap_write(info->regmap, PPMU_V2_CNTENC, cntenc); |
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if (ret < 0) |
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return ret; |
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|
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dev_dbg(&edev->dev, "%25s (load: %ld / %ld)\n", edev->desc->name, |
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edata->load_count, edata->total_count); |
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return 0; |
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} |
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|
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static const struct devfreq_event_ops exynos_ppmu_v2_ops = { |
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.disable = exynos_ppmu_v2_disable, |
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.set_event = exynos_ppmu_v2_set_event, |
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.get_event = exynos_ppmu_v2_get_event, |
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}; |
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|
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static const struct of_device_id exynos_ppmu_id_match[] = { |
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{ |
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.compatible = "samsung,exynos-ppmu", |
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.data = (void *)EXYNOS_TYPE_PPMU, |
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}, { |
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.compatible = "samsung,exynos-ppmu-v2", |
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.data = (void *)EXYNOS_TYPE_PPMU_V2, |
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}, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, exynos_ppmu_id_match); |
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|
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static int of_get_devfreq_events(struct device_node *np, |
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struct exynos_ppmu *info) |
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{ |
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struct devfreq_event_desc *desc; |
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struct device *dev = info->dev; |
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struct device_node *events_np, *node; |
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int i, j, count; |
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const struct of_device_id *of_id; |
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int ret; |
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|
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events_np = of_get_child_by_name(np, "events"); |
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if (!events_np) { |
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dev_err(dev, |
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"failed to get child node of devfreq-event devices\n"); |
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return -EINVAL; |
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} |
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count = of_get_child_count(events_np); |
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desc = devm_kcalloc(dev, count, sizeof(*desc), GFP_KERNEL); |
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if (!desc) |
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return -ENOMEM; |
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info->num_events = count; |
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|
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of_id = of_match_device(exynos_ppmu_id_match, dev); |
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if (of_id) |
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info->ppmu_type = (enum exynos_ppmu_type)of_id->data; |
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else |
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return -EINVAL; |
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|
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j = 0; |
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for_each_child_of_node(events_np, node) { |
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for (i = 0; i < ARRAY_SIZE(ppmu_events); i++) { |
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if (!ppmu_events[i].name) |
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continue; |
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|
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if (of_node_name_eq(node, ppmu_events[i].name)) |
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break; |
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} |
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|
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if (i == ARRAY_SIZE(ppmu_events)) { |
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dev_warn(dev, |
|
"don't know how to configure events : %pOFn\n", |
|
node); |
|
continue; |
|
} |
|
|
|
switch (info->ppmu_type) { |
|
case EXYNOS_TYPE_PPMU: |
|
desc[j].ops = &exynos_ppmu_ops; |
|
break; |
|
case EXYNOS_TYPE_PPMU_V2: |
|
desc[j].ops = &exynos_ppmu_v2_ops; |
|
break; |
|
} |
|
|
|
desc[j].driver_data = info; |
|
|
|
of_property_read_string(node, "event-name", &desc[j].name); |
|
ret = of_property_read_u32(node, "event-data-type", |
|
&desc[j].event_type); |
|
if (ret) { |
|
/* Set the event of proper data type counting. |
|
* Check if the data type has been defined in DT, |
|
* use default if not. |
|
*/ |
|
if (info->ppmu_type == EXYNOS_TYPE_PPMU_V2) { |
|
int id; |
|
/* Not all registers take the same value for |
|
* read+write data count. |
|
*/ |
|
id = __exynos_ppmu_find_ppmu_id(desc[j].name); |
|
|
|
switch (id) { |
|
case PPMU_PMNCNT0: |
|
case PPMU_PMNCNT1: |
|
case PPMU_PMNCNT2: |
|
desc[j].event_type = PPMU_V2_RO_DATA_CNT |
|
| PPMU_V2_WO_DATA_CNT; |
|
break; |
|
case PPMU_PMNCNT3: |
|
desc[j].event_type = |
|
PPMU_V2_EVT3_RW_DATA_CNT; |
|
break; |
|
} |
|
} else { |
|
desc[j].event_type = PPMU_RO_DATA_CNT | |
|
PPMU_WO_DATA_CNT; |
|
} |
|
} |
|
|
|
j++; |
|
} |
|
info->desc = desc; |
|
|
|
of_node_put(events_np); |
|
|
|
return 0; |
|
} |
|
|
|
static struct regmap_config exynos_ppmu_regmap_config = { |
|
.reg_bits = 32, |
|
.val_bits = 32, |
|
.reg_stride = 4, |
|
}; |
|
|
|
static int exynos_ppmu_parse_dt(struct platform_device *pdev, |
|
struct exynos_ppmu *info) |
|
{ |
|
struct device *dev = info->dev; |
|
struct device_node *np = dev->of_node; |
|
struct resource *res; |
|
void __iomem *base; |
|
int ret = 0; |
|
|
|
if (!np) { |
|
dev_err(dev, "failed to find devicetree node\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* Maps the memory mapped IO to control PPMU register */ |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
base = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
|
|
exynos_ppmu_regmap_config.max_register = resource_size(res) - 4; |
|
info->regmap = devm_regmap_init_mmio(dev, base, |
|
&exynos_ppmu_regmap_config); |
|
if (IS_ERR(info->regmap)) { |
|
dev_err(dev, "failed to initialize regmap\n"); |
|
return PTR_ERR(info->regmap); |
|
} |
|
|
|
info->ppmu.clk = devm_clk_get(dev, "ppmu"); |
|
if (IS_ERR(info->ppmu.clk)) { |
|
info->ppmu.clk = NULL; |
|
dev_warn(dev, "cannot get PPMU clock\n"); |
|
} |
|
|
|
ret = of_get_devfreq_events(np, info); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to parse exynos ppmu dt node\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int exynos_ppmu_probe(struct platform_device *pdev) |
|
{ |
|
struct exynos_ppmu *info; |
|
struct devfreq_event_dev **edev; |
|
struct devfreq_event_desc *desc; |
|
int i, ret = 0, size; |
|
|
|
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
|
if (!info) |
|
return -ENOMEM; |
|
|
|
info->dev = &pdev->dev; |
|
|
|
/* Parse dt data to get resource */ |
|
ret = exynos_ppmu_parse_dt(pdev, info); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, |
|
"failed to parse devicetree for resource\n"); |
|
return ret; |
|
} |
|
desc = info->desc; |
|
|
|
size = sizeof(struct devfreq_event_dev *) * info->num_events; |
|
info->edev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
|
if (!info->edev) |
|
return -ENOMEM; |
|
|
|
edev = info->edev; |
|
platform_set_drvdata(pdev, info); |
|
|
|
for (i = 0; i < info->num_events; i++) { |
|
edev[i] = devm_devfreq_event_add_edev(&pdev->dev, &desc[i]); |
|
if (IS_ERR(edev[i])) { |
|
dev_err(&pdev->dev, |
|
"failed to add devfreq-event device\n"); |
|
return PTR_ERR(edev[i]); |
|
} |
|
|
|
pr_info("exynos-ppmu: new PPMU device registered %s (%s)\n", |
|
dev_name(&pdev->dev), desc[i].name); |
|
} |
|
|
|
ret = clk_prepare_enable(info->ppmu.clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to prepare ppmu clock\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int exynos_ppmu_remove(struct platform_device *pdev) |
|
{ |
|
struct exynos_ppmu *info = platform_get_drvdata(pdev); |
|
|
|
clk_disable_unprepare(info->ppmu.clk); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver exynos_ppmu_driver = { |
|
.probe = exynos_ppmu_probe, |
|
.remove = exynos_ppmu_remove, |
|
.driver = { |
|
.name = "exynos-ppmu", |
|
.of_match_table = exynos_ppmu_id_match, |
|
}, |
|
}; |
|
module_platform_driver(exynos_ppmu_driver); |
|
|
|
MODULE_DESCRIPTION("Exynos PPMU(Platform Performance Monitoring Unit) driver"); |
|
MODULE_AUTHOR("Chanwoo Choi <[email protected]>"); |
|
MODULE_LICENSE("GPL");
|
|
|