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1625 lines
44 KiB
1625 lines
44 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Counter driver for the ACCES 104-QUAD-8 |
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* Copyright (C) 2016 William Breathitt Gray |
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* |
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* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/counter.h> |
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#include <linux/device.h> |
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#include <linux/errno.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/types.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/isa.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/types.h> |
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#define QUAD8_EXTENT 32 |
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static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)]; |
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static unsigned int num_quad8; |
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module_param_array(base, uint, &num_quad8, 0); |
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MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses"); |
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#define QUAD8_NUM_COUNTERS 8 |
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|
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/** |
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* struct quad8_iio - IIO device private data structure |
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* @counter: instance of the counter_device |
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* @fck_prescaler: array of filter clock prescaler configurations |
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* @preset: array of preset values |
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* @count_mode: array of count mode configurations |
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* @quadrature_mode: array of quadrature mode configurations |
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* @quadrature_scale: array of quadrature mode scale configurations |
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* @ab_enable: array of A and B inputs enable configurations |
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* @preset_enable: array of set_to_preset_on_index attribute configurations |
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* @synchronous_mode: array of index function synchronous mode configurations |
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* @index_polarity: array of index function polarity configurations |
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* @cable_fault_enable: differential encoder cable status enable configurations |
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* @base: base port address of the IIO device |
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*/ |
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struct quad8_iio { |
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struct mutex lock; |
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struct counter_device counter; |
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unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; |
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unsigned int preset[QUAD8_NUM_COUNTERS]; |
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unsigned int count_mode[QUAD8_NUM_COUNTERS]; |
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unsigned int quadrature_mode[QUAD8_NUM_COUNTERS]; |
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unsigned int quadrature_scale[QUAD8_NUM_COUNTERS]; |
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unsigned int ab_enable[QUAD8_NUM_COUNTERS]; |
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unsigned int preset_enable[QUAD8_NUM_COUNTERS]; |
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unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; |
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unsigned int index_polarity[QUAD8_NUM_COUNTERS]; |
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unsigned int cable_fault_enable; |
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unsigned int base; |
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}; |
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#define QUAD8_REG_CHAN_OP 0x11 |
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#define QUAD8_REG_INDEX_INPUT_LEVELS 0x16 |
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#define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17 |
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/* Borrow Toggle flip-flop */ |
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#define QUAD8_FLAG_BT BIT(0) |
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/* Carry Toggle flip-flop */ |
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#define QUAD8_FLAG_CT BIT(1) |
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/* Error flag */ |
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#define QUAD8_FLAG_E BIT(4) |
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/* Up/Down flag */ |
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#define QUAD8_FLAG_UD BIT(5) |
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/* Reset and Load Signal Decoders */ |
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#define QUAD8_CTR_RLD 0x00 |
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/* Counter Mode Register */ |
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#define QUAD8_CTR_CMR 0x20 |
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/* Input / Output Control Register */ |
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#define QUAD8_CTR_IOR 0x40 |
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/* Index Control Register */ |
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#define QUAD8_CTR_IDR 0x60 |
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/* Reset Byte Pointer (three byte data pointer) */ |
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#define QUAD8_RLD_RESET_BP 0x01 |
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/* Reset Counter */ |
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#define QUAD8_RLD_RESET_CNTR 0x02 |
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/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */ |
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#define QUAD8_RLD_RESET_FLAGS 0x04 |
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/* Reset Error flag */ |
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#define QUAD8_RLD_RESET_E 0x06 |
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/* Preset Register to Counter */ |
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#define QUAD8_RLD_PRESET_CNTR 0x08 |
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/* Transfer Counter to Output Latch */ |
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#define QUAD8_RLD_CNTR_OUT 0x10 |
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/* Transfer Preset Register LSB to FCK Prescaler */ |
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#define QUAD8_RLD_PRESET_PSC 0x18 |
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#define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00 |
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#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01 |
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#define QUAD8_CMR_QUADRATURE_X1 0x08 |
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#define QUAD8_CMR_QUADRATURE_X2 0x10 |
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#define QUAD8_CMR_QUADRATURE_X4 0x18 |
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static int quad8_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, int *val, int *val2, long mask) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel; |
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unsigned int flags; |
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unsigned int borrow; |
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unsigned int carry; |
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int i; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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if (chan->type == IIO_INDEX) { |
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*val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) |
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& BIT(chan->channel)); |
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return IIO_VAL_INT; |
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} |
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flags = inb(base_offset + 1); |
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borrow = flags & QUAD8_FLAG_BT; |
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carry = !!(flags & QUAD8_FLAG_CT); |
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/* Borrow XOR Carry effectively doubles count range */ |
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*val = (borrow ^ carry) << 24; |
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mutex_lock(&priv->lock); |
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/* Reset Byte Pointer; transfer Counter to Output Latch */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, |
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base_offset + 1); |
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for (i = 0; i < 3; i++) |
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*val |= (unsigned int)inb(base_offset) << (8 * i); |
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mutex_unlock(&priv->lock); |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_ENABLE: |
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*val = priv->ab_enable[chan->channel]; |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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*val = 1; |
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*val2 = priv->quadrature_scale[chan->channel]; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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} |
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return -EINVAL; |
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} |
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static int quad8_write_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, int val, int val2, long mask) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel; |
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int i; |
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unsigned int ior_cfg; |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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if (chan->type == IIO_INDEX) |
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return -EINVAL; |
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/* Only 24-bit values are supported */ |
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if ((unsigned int)val > 0xFFFFFF) |
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return -EINVAL; |
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mutex_lock(&priv->lock); |
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/* Reset Byte Pointer */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
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/* Counter can only be set via Preset Register */ |
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for (i = 0; i < 3; i++) |
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outb(val >> (8 * i), base_offset); |
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/* Transfer Preset Register to Counter */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); |
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/* Reset Byte Pointer */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
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/* Set Preset Register back to original value */ |
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val = priv->preset[chan->channel]; |
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for (i = 0; i < 3; i++) |
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outb(val >> (8 * i), base_offset); |
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/* Reset Borrow, Carry, Compare, and Sign flags */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); |
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/* Reset Error flag */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); |
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mutex_unlock(&priv->lock); |
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return 0; |
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case IIO_CHAN_INFO_ENABLE: |
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/* only boolean values accepted */ |
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if (val < 0 || val > 1) |
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return -EINVAL; |
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mutex_lock(&priv->lock); |
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priv->ab_enable[chan->channel] = val; |
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ior_cfg = val | priv->preset_enable[chan->channel] << 1; |
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/* Load I/O control configuration */ |
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); |
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mutex_unlock(&priv->lock); |
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return 0; |
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case IIO_CHAN_INFO_SCALE: |
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mutex_lock(&priv->lock); |
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/* Quadrature scaling only available in quadrature mode */ |
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if (!priv->quadrature_mode[chan->channel] && |
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(val2 || val != 1)) { |
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mutex_unlock(&priv->lock); |
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return -EINVAL; |
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} |
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/* Only three gain states (1, 0.5, 0.25) */ |
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if (val == 1 && !val2) |
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priv->quadrature_scale[chan->channel] = 0; |
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else if (!val) |
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switch (val2) { |
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case 500000: |
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priv->quadrature_scale[chan->channel] = 1; |
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break; |
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case 250000: |
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priv->quadrature_scale[chan->channel] = 2; |
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break; |
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default: |
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mutex_unlock(&priv->lock); |
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return -EINVAL; |
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} |
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else { |
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mutex_unlock(&priv->lock); |
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return -EINVAL; |
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} |
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mutex_unlock(&priv->lock); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static const struct iio_info quad8_info = { |
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.read_raw = quad8_read_raw, |
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.write_raw = quad8_write_raw |
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}; |
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static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private, |
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const struct iio_chan_spec *chan, char *buf) |
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{ |
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const struct quad8_iio *const priv = iio_priv(indio_dev); |
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return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]); |
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} |
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static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private, |
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const struct iio_chan_spec *chan, const char *buf, size_t len) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel; |
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unsigned int preset; |
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int ret; |
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int i; |
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ret = kstrtouint(buf, 0, &preset); |
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if (ret) |
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return ret; |
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/* Only 24-bit values are supported */ |
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if (preset > 0xFFFFFF) |
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return -EINVAL; |
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mutex_lock(&priv->lock); |
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priv->preset[chan->channel] = preset; |
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/* Reset Byte Pointer */ |
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
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/* Set Preset Register */ |
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for (i = 0; i < 3; i++) |
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outb(preset >> (8 * i), base_offset); |
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mutex_unlock(&priv->lock); |
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return len; |
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} |
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static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev, |
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uintptr_t private, const struct iio_chan_spec *chan, char *buf) |
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{ |
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const struct quad8_iio *const priv = iio_priv(indio_dev); |
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return snprintf(buf, PAGE_SIZE, "%u\n", |
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!priv->preset_enable[chan->channel]); |
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} |
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static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev, |
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uintptr_t private, const struct iio_chan_spec *chan, const char *buf, |
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size_t len) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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bool preset_enable; |
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int ret; |
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unsigned int ior_cfg; |
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ret = kstrtobool(buf, &preset_enable); |
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if (ret) |
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return ret; |
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/* Preset enable is active low in Input/Output Control register */ |
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preset_enable = !preset_enable; |
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mutex_lock(&priv->lock); |
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priv->preset_enable[chan->channel] = preset_enable; |
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ior_cfg = priv->ab_enable[chan->channel] | |
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(unsigned int)preset_enable << 1; |
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/* Load I/O control configuration to Input / Output Control Register */ |
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset); |
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mutex_unlock(&priv->lock); |
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return len; |
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} |
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static const char *const quad8_noise_error_states[] = { |
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"No excessive noise is present at the count inputs", |
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"Excessive noise is present at the count inputs" |
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}; |
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static int quad8_get_noise_error(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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return !!(inb(base_offset) & QUAD8_FLAG_E); |
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} |
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static const struct iio_enum quad8_noise_error_enum = { |
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.items = quad8_noise_error_states, |
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.num_items = ARRAY_SIZE(quad8_noise_error_states), |
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.get = quad8_get_noise_error |
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}; |
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static const char *const quad8_count_direction_states[] = { |
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"down", |
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"up" |
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}; |
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static int quad8_get_count_direction(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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return !!(inb(base_offset) & QUAD8_FLAG_UD); |
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} |
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static const struct iio_enum quad8_count_direction_enum = { |
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.items = quad8_count_direction_states, |
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.num_items = ARRAY_SIZE(quad8_count_direction_states), |
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.get = quad8_get_count_direction |
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}; |
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static const char *const quad8_count_modes[] = { |
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"normal", |
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"range limit", |
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"non-recycle", |
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"modulo-n" |
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}; |
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static int quad8_set_count_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, unsigned int cnt_mode) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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unsigned int mode_cfg = cnt_mode << 1; |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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mutex_lock(&priv->lock); |
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priv->count_mode[chan->channel] = cnt_mode; |
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/* Add quadrature mode configuration */ |
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if (priv->quadrature_mode[chan->channel]) |
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mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3; |
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/* Load mode configuration to Counter Mode Register */ |
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset); |
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mutex_unlock(&priv->lock); |
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return 0; |
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} |
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static int quad8_get_count_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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const struct quad8_iio *const priv = iio_priv(indio_dev); |
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return priv->count_mode[chan->channel]; |
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} |
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static const struct iio_enum quad8_count_mode_enum = { |
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.items = quad8_count_modes, |
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.num_items = ARRAY_SIZE(quad8_count_modes), |
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.set = quad8_set_count_mode, |
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.get = quad8_get_count_mode |
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}; |
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static const char *const quad8_synchronous_modes[] = { |
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"non-synchronous", |
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"synchronous" |
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}; |
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static int quad8_set_synchronous_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, unsigned int synchronous_mode) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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unsigned int idr_cfg = synchronous_mode; |
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mutex_lock(&priv->lock); |
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idr_cfg |= priv->index_polarity[chan->channel] << 1; |
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/* Index function must be non-synchronous in non-quadrature mode */ |
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if (synchronous_mode && !priv->quadrature_mode[chan->channel]) { |
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mutex_unlock(&priv->lock); |
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return -EINVAL; |
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} |
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priv->synchronous_mode[chan->channel] = synchronous_mode; |
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|
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/* Load Index Control configuration to Index Control Register */ |
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset); |
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mutex_unlock(&priv->lock); |
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return 0; |
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} |
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static int quad8_get_synchronous_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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const struct quad8_iio *const priv = iio_priv(indio_dev); |
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return priv->synchronous_mode[chan->channel]; |
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} |
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static const struct iio_enum quad8_synchronous_mode_enum = { |
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.items = quad8_synchronous_modes, |
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.num_items = ARRAY_SIZE(quad8_synchronous_modes), |
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.set = quad8_set_synchronous_mode, |
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.get = quad8_get_synchronous_mode |
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}; |
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static const char *const quad8_quadrature_modes[] = { |
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"non-quadrature", |
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"quadrature" |
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}; |
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static int quad8_set_quadrature_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, unsigned int quadrature_mode) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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unsigned int mode_cfg; |
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mutex_lock(&priv->lock); |
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|
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mode_cfg = priv->count_mode[chan->channel] << 1; |
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|
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if (quadrature_mode) |
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mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3; |
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else { |
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/* Quadrature scaling only available in quadrature mode */ |
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priv->quadrature_scale[chan->channel] = 0; |
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|
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/* Synchronous function not supported in non-quadrature mode */ |
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if (priv->synchronous_mode[chan->channel]) |
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quad8_set_synchronous_mode(indio_dev, chan, 0); |
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} |
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priv->quadrature_mode[chan->channel] = quadrature_mode; |
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|
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/* Load mode configuration to Counter Mode Register */ |
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset); |
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|
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mutex_unlock(&priv->lock); |
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|
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return 0; |
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} |
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|
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static int quad8_get_quadrature_mode(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan) |
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{ |
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const struct quad8_iio *const priv = iio_priv(indio_dev); |
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|
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return priv->quadrature_mode[chan->channel]; |
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} |
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static const struct iio_enum quad8_quadrature_mode_enum = { |
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.items = quad8_quadrature_modes, |
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.num_items = ARRAY_SIZE(quad8_quadrature_modes), |
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.set = quad8_set_quadrature_mode, |
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.get = quad8_get_quadrature_mode |
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}; |
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|
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static const char *const quad8_index_polarity_modes[] = { |
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"negative", |
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"positive" |
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}; |
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|
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static int quad8_set_index_polarity(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, unsigned int index_polarity) |
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{ |
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struct quad8_iio *const priv = iio_priv(indio_dev); |
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const int base_offset = priv->base + 2 * chan->channel + 1; |
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unsigned int idr_cfg = index_polarity << 1; |
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|
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mutex_lock(&priv->lock); |
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|
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idr_cfg |= priv->synchronous_mode[chan->channel]; |
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|
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priv->index_polarity[chan->channel] = index_polarity; |
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|
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/* Load Index Control configuration to Index Control Register */ |
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_get_index_polarity(struct iio_dev *indio_dev, |
|
const struct iio_chan_spec *chan) |
|
{ |
|
const struct quad8_iio *const priv = iio_priv(indio_dev); |
|
|
|
return priv->index_polarity[chan->channel]; |
|
} |
|
|
|
static const struct iio_enum quad8_index_polarity_enum = { |
|
.items = quad8_index_polarity_modes, |
|
.num_items = ARRAY_SIZE(quad8_index_polarity_modes), |
|
.set = quad8_set_index_polarity, |
|
.get = quad8_get_index_polarity |
|
}; |
|
|
|
static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = { |
|
{ |
|
.name = "preset", |
|
.shared = IIO_SEPARATE, |
|
.read = quad8_read_preset, |
|
.write = quad8_write_preset |
|
}, |
|
{ |
|
.name = "set_to_preset_on_index", |
|
.shared = IIO_SEPARATE, |
|
.read = quad8_read_set_to_preset_on_index, |
|
.write = quad8_write_set_to_preset_on_index |
|
}, |
|
IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum), |
|
IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum), |
|
IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum), |
|
IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum), |
|
IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum), |
|
IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum), |
|
IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum), |
|
IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum), |
|
{} |
|
}; |
|
|
|
static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = { |
|
IIO_ENUM("synchronous_mode", IIO_SEPARATE, |
|
&quad8_synchronous_mode_enum), |
|
IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum), |
|
IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum), |
|
IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum), |
|
{} |
|
}; |
|
|
|
#define QUAD8_COUNT_CHAN(_chan) { \ |
|
.type = IIO_COUNT, \ |
|
.channel = (_chan), \ |
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ |
|
BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \ |
|
.ext_info = quad8_count_ext_info, \ |
|
.indexed = 1 \ |
|
} |
|
|
|
#define QUAD8_INDEX_CHAN(_chan) { \ |
|
.type = IIO_INDEX, \ |
|
.channel = (_chan), \ |
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ |
|
.ext_info = quad8_index_ext_info, \ |
|
.indexed = 1 \ |
|
} |
|
|
|
static const struct iio_chan_spec quad8_channels[] = { |
|
QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0), |
|
QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1), |
|
QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2), |
|
QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3), |
|
QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4), |
|
QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5), |
|
QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6), |
|
QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7) |
|
}; |
|
|
|
static int quad8_signal_read(struct counter_device *counter, |
|
struct counter_signal *signal, enum counter_signal_value *val) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
unsigned int state; |
|
|
|
/* Only Index signal levels can be read */ |
|
if (signal->id < 16) |
|
return -EINVAL; |
|
|
|
state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) |
|
& BIT(signal->id - 16); |
|
|
|
*val = (state) ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW; |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_count_read(struct counter_device *counter, |
|
struct counter_count *count, unsigned long *val) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int base_offset = priv->base + 2 * count->id; |
|
unsigned int flags; |
|
unsigned int borrow; |
|
unsigned int carry; |
|
int i; |
|
|
|
flags = inb(base_offset + 1); |
|
borrow = flags & QUAD8_FLAG_BT; |
|
carry = !!(flags & QUAD8_FLAG_CT); |
|
|
|
/* Borrow XOR Carry effectively doubles count range */ |
|
*val = (unsigned long)(borrow ^ carry) << 24; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
/* Reset Byte Pointer; transfer Counter to Output Latch */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, |
|
base_offset + 1); |
|
|
|
for (i = 0; i < 3; i++) |
|
*val |= (unsigned long)inb(base_offset) << (8 * i); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_count_write(struct counter_device *counter, |
|
struct counter_count *count, unsigned long val) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int base_offset = priv->base + 2 * count->id; |
|
int i; |
|
|
|
/* Only 24-bit values are supported */ |
|
if (val > 0xFFFFFF) |
|
return -EINVAL; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
|
|
/* Counter can only be set via Preset Register */ |
|
for (i = 0; i < 3; i++) |
|
outb(val >> (8 * i), base_offset); |
|
|
|
/* Transfer Preset Register to Counter */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); |
|
|
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
|
|
/* Set Preset Register back to original value */ |
|
val = priv->preset[count->id]; |
|
for (i = 0; i < 3; i++) |
|
outb(val >> (8 * i), base_offset); |
|
|
|
/* Reset Borrow, Carry, Compare, and Sign flags */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); |
|
/* Reset Error flag */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
enum quad8_count_function { |
|
QUAD8_COUNT_FUNCTION_PULSE_DIRECTION = 0, |
|
QUAD8_COUNT_FUNCTION_QUADRATURE_X1, |
|
QUAD8_COUNT_FUNCTION_QUADRATURE_X2, |
|
QUAD8_COUNT_FUNCTION_QUADRATURE_X4 |
|
}; |
|
|
|
static enum counter_count_function quad8_count_functions_list[] = { |
|
[QUAD8_COUNT_FUNCTION_PULSE_DIRECTION] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION, |
|
[QUAD8_COUNT_FUNCTION_QUADRATURE_X1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A, |
|
[QUAD8_COUNT_FUNCTION_QUADRATURE_X2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A, |
|
[QUAD8_COUNT_FUNCTION_QUADRATURE_X4] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4 |
|
}; |
|
|
|
static int quad8_function_get(struct counter_device *counter, |
|
struct counter_count *count, size_t *function) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int id = count->id; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
if (priv->quadrature_mode[id]) |
|
switch (priv->quadrature_scale[id]) { |
|
case 0: |
|
*function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1; |
|
break; |
|
case 1: |
|
*function = QUAD8_COUNT_FUNCTION_QUADRATURE_X2; |
|
break; |
|
case 2: |
|
*function = QUAD8_COUNT_FUNCTION_QUADRATURE_X4; |
|
break; |
|
} |
|
else |
|
*function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION; |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_function_set(struct counter_device *counter, |
|
struct counter_count *count, size_t function) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int id = count->id; |
|
unsigned int *const quadrature_mode = priv->quadrature_mode + id; |
|
unsigned int *const scale = priv->quadrature_scale + id; |
|
unsigned int *const synchronous_mode = priv->synchronous_mode + id; |
|
const int base_offset = priv->base + 2 * id + 1; |
|
unsigned int mode_cfg; |
|
unsigned int idr_cfg; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
mode_cfg = priv->count_mode[id] << 1; |
|
idr_cfg = priv->index_polarity[id] << 1; |
|
|
|
if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) { |
|
*quadrature_mode = 0; |
|
|
|
/* Quadrature scaling only available in quadrature mode */ |
|
*scale = 0; |
|
|
|
/* Synchronous function not supported in non-quadrature mode */ |
|
if (*synchronous_mode) { |
|
*synchronous_mode = 0; |
|
/* Disable synchronous function mode */ |
|
outb(QUAD8_CTR_IDR | idr_cfg, base_offset); |
|
} |
|
} else { |
|
*quadrature_mode = 1; |
|
|
|
switch (function) { |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X1: |
|
*scale = 0; |
|
mode_cfg |= QUAD8_CMR_QUADRATURE_X1; |
|
break; |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X2: |
|
*scale = 1; |
|
mode_cfg |= QUAD8_CMR_QUADRATURE_X2; |
|
break; |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X4: |
|
*scale = 2; |
|
mode_cfg |= QUAD8_CMR_QUADRATURE_X4; |
|
break; |
|
} |
|
} |
|
|
|
/* Load mode configuration to Counter Mode Register */ |
|
outb(QUAD8_CTR_CMR | mode_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static void quad8_direction_get(struct counter_device *counter, |
|
struct counter_count *count, enum counter_count_direction *direction) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
unsigned int ud_flag; |
|
const unsigned int flag_addr = priv->base + 2 * count->id + 1; |
|
|
|
/* U/D flag: nonzero = up, zero = down */ |
|
ud_flag = inb(flag_addr) & QUAD8_FLAG_UD; |
|
|
|
*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : |
|
COUNTER_COUNT_DIRECTION_BACKWARD; |
|
} |
|
|
|
enum quad8_synapse_action { |
|
QUAD8_SYNAPSE_ACTION_NONE = 0, |
|
QUAD8_SYNAPSE_ACTION_RISING_EDGE, |
|
QUAD8_SYNAPSE_ACTION_FALLING_EDGE, |
|
QUAD8_SYNAPSE_ACTION_BOTH_EDGES |
|
}; |
|
|
|
static enum counter_synapse_action quad8_index_actions_list[] = { |
|
[QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, |
|
[QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE |
|
}; |
|
|
|
static enum counter_synapse_action quad8_synapse_actions_list[] = { |
|
[QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, |
|
[QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE, |
|
[QUAD8_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE, |
|
[QUAD8_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES |
|
}; |
|
|
|
static int quad8_action_get(struct counter_device *counter, |
|
struct counter_count *count, struct counter_synapse *synapse, |
|
size_t *action) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
int err; |
|
size_t function = 0; |
|
const size_t signal_a_id = count->synapses[0].signal->id; |
|
enum counter_count_direction direction; |
|
|
|
/* Handle Index signals */ |
|
if (synapse->signal->id >= 16) { |
|
if (priv->preset_enable[count->id]) |
|
*action = QUAD8_SYNAPSE_ACTION_RISING_EDGE; |
|
else |
|
*action = QUAD8_SYNAPSE_ACTION_NONE; |
|
|
|
return 0; |
|
} |
|
|
|
err = quad8_function_get(counter, count, &function); |
|
if (err) |
|
return err; |
|
|
|
/* Default action mode */ |
|
*action = QUAD8_SYNAPSE_ACTION_NONE; |
|
|
|
/* Determine action mode based on current count function mode */ |
|
switch (function) { |
|
case QUAD8_COUNT_FUNCTION_PULSE_DIRECTION: |
|
if (synapse->signal->id == signal_a_id) |
|
*action = QUAD8_SYNAPSE_ACTION_RISING_EDGE; |
|
break; |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X1: |
|
if (synapse->signal->id == signal_a_id) { |
|
quad8_direction_get(counter, count, &direction); |
|
|
|
if (direction == COUNTER_COUNT_DIRECTION_FORWARD) |
|
*action = QUAD8_SYNAPSE_ACTION_RISING_EDGE; |
|
else |
|
*action = QUAD8_SYNAPSE_ACTION_FALLING_EDGE; |
|
} |
|
break; |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X2: |
|
if (synapse->signal->id == signal_a_id) |
|
*action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES; |
|
break; |
|
case QUAD8_COUNT_FUNCTION_QUADRATURE_X4: |
|
*action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES; |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct counter_ops quad8_ops = { |
|
.signal_read = quad8_signal_read, |
|
.count_read = quad8_count_read, |
|
.count_write = quad8_count_write, |
|
.function_get = quad8_function_get, |
|
.function_set = quad8_function_set, |
|
.action_get = quad8_action_get |
|
}; |
|
|
|
static int quad8_index_polarity_get(struct counter_device *counter, |
|
struct counter_signal *signal, size_t *index_polarity) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id - 16; |
|
|
|
*index_polarity = priv->index_polarity[channel_id]; |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_index_polarity_set(struct counter_device *counter, |
|
struct counter_signal *signal, size_t index_polarity) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id - 16; |
|
const int base_offset = priv->base + 2 * channel_id + 1; |
|
unsigned int idr_cfg = index_polarity << 1; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
idr_cfg |= priv->synchronous_mode[channel_id]; |
|
|
|
priv->index_polarity[channel_id] = index_polarity; |
|
|
|
/* Load Index Control configuration to Index Control Register */ |
|
outb(QUAD8_CTR_IDR | idr_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static struct counter_signal_enum_ext quad8_index_pol_enum = { |
|
.items = quad8_index_polarity_modes, |
|
.num_items = ARRAY_SIZE(quad8_index_polarity_modes), |
|
.get = quad8_index_polarity_get, |
|
.set = quad8_index_polarity_set |
|
}; |
|
|
|
static int quad8_synchronous_mode_get(struct counter_device *counter, |
|
struct counter_signal *signal, size_t *synchronous_mode) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id - 16; |
|
|
|
*synchronous_mode = priv->synchronous_mode[channel_id]; |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_synchronous_mode_set(struct counter_device *counter, |
|
struct counter_signal *signal, size_t synchronous_mode) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id - 16; |
|
const int base_offset = priv->base + 2 * channel_id + 1; |
|
unsigned int idr_cfg = synchronous_mode; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
idr_cfg |= priv->index_polarity[channel_id] << 1; |
|
|
|
/* Index function must be non-synchronous in non-quadrature mode */ |
|
if (synchronous_mode && !priv->quadrature_mode[channel_id]) { |
|
mutex_unlock(&priv->lock); |
|
return -EINVAL; |
|
} |
|
|
|
priv->synchronous_mode[channel_id] = synchronous_mode; |
|
|
|
/* Load Index Control configuration to Index Control Register */ |
|
outb(QUAD8_CTR_IDR | idr_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static struct counter_signal_enum_ext quad8_syn_mode_enum = { |
|
.items = quad8_synchronous_modes, |
|
.num_items = ARRAY_SIZE(quad8_synchronous_modes), |
|
.get = quad8_synchronous_mode_get, |
|
.set = quad8_synchronous_mode_set |
|
}; |
|
|
|
static ssize_t quad8_count_floor_read(struct counter_device *counter, |
|
struct counter_count *count, void *private, char *buf) |
|
{ |
|
/* Only a floor of 0 is supported */ |
|
return sprintf(buf, "0\n"); |
|
} |
|
|
|
static int quad8_count_mode_get(struct counter_device *counter, |
|
struct counter_count *count, size_t *cnt_mode) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
|
|
/* Map 104-QUAD-8 count mode to Generic Counter count mode */ |
|
switch (priv->count_mode[count->id]) { |
|
case 0: |
|
*cnt_mode = COUNTER_COUNT_MODE_NORMAL; |
|
break; |
|
case 1: |
|
*cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT; |
|
break; |
|
case 2: |
|
*cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE; |
|
break; |
|
case 3: |
|
*cnt_mode = COUNTER_COUNT_MODE_MODULO_N; |
|
break; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int quad8_count_mode_set(struct counter_device *counter, |
|
struct counter_count *count, size_t cnt_mode) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
unsigned int mode_cfg; |
|
const int base_offset = priv->base + 2 * count->id + 1; |
|
|
|
/* Map Generic Counter count mode to 104-QUAD-8 count mode */ |
|
switch (cnt_mode) { |
|
case COUNTER_COUNT_MODE_NORMAL: |
|
cnt_mode = 0; |
|
break; |
|
case COUNTER_COUNT_MODE_RANGE_LIMIT: |
|
cnt_mode = 1; |
|
break; |
|
case COUNTER_COUNT_MODE_NON_RECYCLE: |
|
cnt_mode = 2; |
|
break; |
|
case COUNTER_COUNT_MODE_MODULO_N: |
|
cnt_mode = 3; |
|
break; |
|
} |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
priv->count_mode[count->id] = cnt_mode; |
|
|
|
/* Set count mode configuration value */ |
|
mode_cfg = cnt_mode << 1; |
|
|
|
/* Add quadrature mode configuration */ |
|
if (priv->quadrature_mode[count->id]) |
|
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; |
|
|
|
/* Load mode configuration to Counter Mode Register */ |
|
outb(QUAD8_CTR_CMR | mode_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return 0; |
|
} |
|
|
|
static struct counter_count_enum_ext quad8_cnt_mode_enum = { |
|
.items = counter_count_mode_str, |
|
.num_items = ARRAY_SIZE(counter_count_mode_str), |
|
.get = quad8_count_mode_get, |
|
.set = quad8_count_mode_set |
|
}; |
|
|
|
static ssize_t quad8_count_direction_read(struct counter_device *counter, |
|
struct counter_count *count, void *priv, char *buf) |
|
{ |
|
enum counter_count_direction dir; |
|
|
|
quad8_direction_get(counter, count, &dir); |
|
|
|
return sprintf(buf, "%s\n", counter_count_direction_str[dir]); |
|
} |
|
|
|
static ssize_t quad8_count_enable_read(struct counter_device *counter, |
|
struct counter_count *count, void *private, char *buf) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
|
|
return sprintf(buf, "%u\n", priv->ab_enable[count->id]); |
|
} |
|
|
|
static ssize_t quad8_count_enable_write(struct counter_device *counter, |
|
struct counter_count *count, void *private, const char *buf, size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int base_offset = priv->base + 2 * count->id; |
|
int err; |
|
bool ab_enable; |
|
unsigned int ior_cfg; |
|
|
|
err = kstrtobool(buf, &ab_enable); |
|
if (err) |
|
return err; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
priv->ab_enable[count->id] = ab_enable; |
|
|
|
ior_cfg = ab_enable | priv->preset_enable[count->id] << 1; |
|
|
|
/* Load I/O control configuration */ |
|
outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static int quad8_error_noise_get(struct counter_device *counter, |
|
struct counter_count *count, size_t *noise_error) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
const int base_offset = priv->base + 2 * count->id + 1; |
|
|
|
*noise_error = !!(inb(base_offset) & QUAD8_FLAG_E); |
|
|
|
return 0; |
|
} |
|
|
|
static struct counter_count_enum_ext quad8_error_noise_enum = { |
|
.items = quad8_noise_error_states, |
|
.num_items = ARRAY_SIZE(quad8_noise_error_states), |
|
.get = quad8_error_noise_get |
|
}; |
|
|
|
static ssize_t quad8_count_preset_read(struct counter_device *counter, |
|
struct counter_count *count, void *private, char *buf) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
|
|
return sprintf(buf, "%u\n", priv->preset[count->id]); |
|
} |
|
|
|
static void quad8_preset_register_set(struct quad8_iio *quad8iio, int id, |
|
unsigned int preset) |
|
{ |
|
const unsigned int base_offset = quad8iio->base + 2 * id; |
|
int i; |
|
|
|
quad8iio->preset[id] = preset; |
|
|
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
|
|
/* Set Preset Register */ |
|
for (i = 0; i < 3; i++) |
|
outb(preset >> (8 * i), base_offset); |
|
} |
|
|
|
static ssize_t quad8_count_preset_write(struct counter_device *counter, |
|
struct counter_count *count, void *private, const char *buf, size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
unsigned int preset; |
|
int ret; |
|
|
|
ret = kstrtouint(buf, 0, &preset); |
|
if (ret) |
|
return ret; |
|
|
|
/* Only 24-bit values are supported */ |
|
if (preset > 0xFFFFFF) |
|
return -EINVAL; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
quad8_preset_register_set(priv, count->id, preset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static ssize_t quad8_count_ceiling_read(struct counter_device *counter, |
|
struct counter_count *count, void *private, char *buf) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
/* Range Limit and Modulo-N count modes use preset value as ceiling */ |
|
switch (priv->count_mode[count->id]) { |
|
case 1: |
|
case 3: |
|
mutex_unlock(&priv->lock); |
|
return sprintf(buf, "%u\n", priv->preset[count->id]); |
|
} |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */ |
|
return sprintf(buf, "33554431\n"); |
|
} |
|
|
|
static ssize_t quad8_count_ceiling_write(struct counter_device *counter, |
|
struct counter_count *count, void *private, const char *buf, size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
unsigned int ceiling; |
|
int ret; |
|
|
|
ret = kstrtouint(buf, 0, &ceiling); |
|
if (ret) |
|
return ret; |
|
|
|
/* Only 24-bit values are supported */ |
|
if (ceiling > 0xFFFFFF) |
|
return -EINVAL; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
/* Range Limit and Modulo-N count modes use preset value as ceiling */ |
|
switch (priv->count_mode[count->id]) { |
|
case 1: |
|
case 3: |
|
quad8_preset_register_set(priv, count->id, ceiling); |
|
break; |
|
} |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static ssize_t quad8_count_preset_enable_read(struct counter_device *counter, |
|
struct counter_count *count, void *private, char *buf) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
|
|
return sprintf(buf, "%u\n", !priv->preset_enable[count->id]); |
|
} |
|
|
|
static ssize_t quad8_count_preset_enable_write(struct counter_device *counter, |
|
struct counter_count *count, void *private, const char *buf, size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const int base_offset = priv->base + 2 * count->id + 1; |
|
bool preset_enable; |
|
int ret; |
|
unsigned int ior_cfg; |
|
|
|
ret = kstrtobool(buf, &preset_enable); |
|
if (ret) |
|
return ret; |
|
|
|
/* Preset enable is active low in Input/Output Control register */ |
|
preset_enable = !preset_enable; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
priv->preset_enable[count->id] = preset_enable; |
|
|
|
ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1; |
|
|
|
/* Load I/O control configuration to Input / Output Control Register */ |
|
outb(QUAD8_CTR_IOR | ior_cfg, base_offset); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static ssize_t quad8_signal_cable_fault_read(struct counter_device *counter, |
|
struct counter_signal *signal, |
|
void *private, char *buf) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id / 2; |
|
bool disabled; |
|
unsigned int status; |
|
unsigned int fault; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
disabled = !(priv->cable_fault_enable & BIT(channel_id)); |
|
|
|
if (disabled) { |
|
mutex_unlock(&priv->lock); |
|
return -EINVAL; |
|
} |
|
|
|
/* Logic 0 = cable fault */ |
|
status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
/* Mask respective channel and invert logic */ |
|
fault = !(status & BIT(channel_id)); |
|
|
|
return sprintf(buf, "%u\n", fault); |
|
} |
|
|
|
static ssize_t quad8_signal_cable_fault_enable_read( |
|
struct counter_device *counter, struct counter_signal *signal, |
|
void *private, char *buf) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id / 2; |
|
const unsigned int enb = !!(priv->cable_fault_enable & BIT(channel_id)); |
|
|
|
return sprintf(buf, "%u\n", enb); |
|
} |
|
|
|
static ssize_t quad8_signal_cable_fault_enable_write( |
|
struct counter_device *counter, struct counter_signal *signal, |
|
void *private, const char *buf, size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id / 2; |
|
bool enable; |
|
int ret; |
|
unsigned int cable_fault_enable; |
|
|
|
ret = kstrtobool(buf, &enable); |
|
if (ret) |
|
return ret; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
if (enable) |
|
priv->cable_fault_enable |= BIT(channel_id); |
|
else |
|
priv->cable_fault_enable &= ~BIT(channel_id); |
|
|
|
/* Enable is active low in Differential Encoder Cable Status register */ |
|
cable_fault_enable = ~priv->cable_fault_enable; |
|
|
|
outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static ssize_t quad8_signal_fck_prescaler_read(struct counter_device *counter, |
|
struct counter_signal *signal, void *private, char *buf) |
|
{ |
|
const struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id / 2; |
|
|
|
return sprintf(buf, "%u\n", priv->fck_prescaler[channel_id]); |
|
} |
|
|
|
static ssize_t quad8_signal_fck_prescaler_write(struct counter_device *counter, |
|
struct counter_signal *signal, void *private, const char *buf, |
|
size_t len) |
|
{ |
|
struct quad8_iio *const priv = counter->priv; |
|
const size_t channel_id = signal->id / 2; |
|
const int base_offset = priv->base + 2 * channel_id; |
|
u8 prescaler; |
|
int ret; |
|
|
|
ret = kstrtou8(buf, 0, &prescaler); |
|
if (ret) |
|
return ret; |
|
|
|
mutex_lock(&priv->lock); |
|
|
|
priv->fck_prescaler[channel_id] = prescaler; |
|
|
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
|
|
/* Set filter clock factor */ |
|
outb(prescaler, base_offset); |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, |
|
base_offset + 1); |
|
|
|
mutex_unlock(&priv->lock); |
|
|
|
return len; |
|
} |
|
|
|
static const struct counter_signal_ext quad8_signal_ext[] = { |
|
{ |
|
.name = "cable_fault", |
|
.read = quad8_signal_cable_fault_read |
|
}, |
|
{ |
|
.name = "cable_fault_enable", |
|
.read = quad8_signal_cable_fault_enable_read, |
|
.write = quad8_signal_cable_fault_enable_write |
|
}, |
|
{ |
|
.name = "filter_clock_prescaler", |
|
.read = quad8_signal_fck_prescaler_read, |
|
.write = quad8_signal_fck_prescaler_write |
|
} |
|
}; |
|
|
|
static const struct counter_signal_ext quad8_index_ext[] = { |
|
COUNTER_SIGNAL_ENUM("index_polarity", &quad8_index_pol_enum), |
|
COUNTER_SIGNAL_ENUM_AVAILABLE("index_polarity", &quad8_index_pol_enum), |
|
COUNTER_SIGNAL_ENUM("synchronous_mode", &quad8_syn_mode_enum), |
|
COUNTER_SIGNAL_ENUM_AVAILABLE("synchronous_mode", &quad8_syn_mode_enum) |
|
}; |
|
|
|
#define QUAD8_QUAD_SIGNAL(_id, _name) { \ |
|
.id = (_id), \ |
|
.name = (_name), \ |
|
.ext = quad8_signal_ext, \ |
|
.num_ext = ARRAY_SIZE(quad8_signal_ext) \ |
|
} |
|
|
|
#define QUAD8_INDEX_SIGNAL(_id, _name) { \ |
|
.id = (_id), \ |
|
.name = (_name), \ |
|
.ext = quad8_index_ext, \ |
|
.num_ext = ARRAY_SIZE(quad8_index_ext) \ |
|
} |
|
|
|
static struct counter_signal quad8_signals[] = { |
|
QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"), |
|
QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"), |
|
QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"), |
|
QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"), |
|
QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"), |
|
QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"), |
|
QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"), |
|
QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"), |
|
QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"), |
|
QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"), |
|
QUAD8_INDEX_SIGNAL(23, "Channel 8 Index") |
|
}; |
|
|
|
#define QUAD8_COUNT_SYNAPSES(_id) { \ |
|
{ \ |
|
.actions_list = quad8_synapse_actions_list, \ |
|
.num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \ |
|
.signal = quad8_signals + 2 * (_id) \ |
|
}, \ |
|
{ \ |
|
.actions_list = quad8_synapse_actions_list, \ |
|
.num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \ |
|
.signal = quad8_signals + 2 * (_id) + 1 \ |
|
}, \ |
|
{ \ |
|
.actions_list = quad8_index_actions_list, \ |
|
.num_actions = ARRAY_SIZE(quad8_index_actions_list), \ |
|
.signal = quad8_signals + 2 * (_id) + 16 \ |
|
} \ |
|
} |
|
|
|
static struct counter_synapse quad8_count_synapses[][3] = { |
|
QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1), |
|
QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3), |
|
QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5), |
|
QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7) |
|
}; |
|
|
|
static const struct counter_count_ext quad8_count_ext[] = { |
|
{ |
|
.name = "ceiling", |
|
.read = quad8_count_ceiling_read, |
|
.write = quad8_count_ceiling_write |
|
}, |
|
{ |
|
.name = "floor", |
|
.read = quad8_count_floor_read |
|
}, |
|
COUNTER_COUNT_ENUM("count_mode", &quad8_cnt_mode_enum), |
|
COUNTER_COUNT_ENUM_AVAILABLE("count_mode", &quad8_cnt_mode_enum), |
|
{ |
|
.name = "direction", |
|
.read = quad8_count_direction_read |
|
}, |
|
{ |
|
.name = "enable", |
|
.read = quad8_count_enable_read, |
|
.write = quad8_count_enable_write |
|
}, |
|
COUNTER_COUNT_ENUM("error_noise", &quad8_error_noise_enum), |
|
COUNTER_COUNT_ENUM_AVAILABLE("error_noise", &quad8_error_noise_enum), |
|
{ |
|
.name = "preset", |
|
.read = quad8_count_preset_read, |
|
.write = quad8_count_preset_write |
|
}, |
|
{ |
|
.name = "preset_enable", |
|
.read = quad8_count_preset_enable_read, |
|
.write = quad8_count_preset_enable_write |
|
} |
|
}; |
|
|
|
#define QUAD8_COUNT(_id, _cntname) { \ |
|
.id = (_id), \ |
|
.name = (_cntname), \ |
|
.functions_list = quad8_count_functions_list, \ |
|
.num_functions = ARRAY_SIZE(quad8_count_functions_list), \ |
|
.synapses = quad8_count_synapses[(_id)], \ |
|
.num_synapses = 2, \ |
|
.ext = quad8_count_ext, \ |
|
.num_ext = ARRAY_SIZE(quad8_count_ext) \ |
|
} |
|
|
|
static struct counter_count quad8_counts[] = { |
|
QUAD8_COUNT(0, "Channel 1 Count"), |
|
QUAD8_COUNT(1, "Channel 2 Count"), |
|
QUAD8_COUNT(2, "Channel 3 Count"), |
|
QUAD8_COUNT(3, "Channel 4 Count"), |
|
QUAD8_COUNT(4, "Channel 5 Count"), |
|
QUAD8_COUNT(5, "Channel 6 Count"), |
|
QUAD8_COUNT(6, "Channel 7 Count"), |
|
QUAD8_COUNT(7, "Channel 8 Count") |
|
}; |
|
|
|
static int quad8_probe(struct device *dev, unsigned int id) |
|
{ |
|
struct iio_dev *indio_dev; |
|
struct quad8_iio *quad8iio; |
|
int i, j; |
|
unsigned int base_offset; |
|
int err; |
|
|
|
if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { |
|
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n", |
|
base[id], base[id] + QUAD8_EXTENT); |
|
return -EBUSY; |
|
} |
|
|
|
/* Allocate IIO device; this also allocates driver data structure */ |
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*quad8iio)); |
|
if (!indio_dev) |
|
return -ENOMEM; |
|
|
|
/* Initialize IIO device */ |
|
indio_dev->info = &quad8_info; |
|
indio_dev->modes = INDIO_DIRECT_MODE; |
|
indio_dev->num_channels = ARRAY_SIZE(quad8_channels); |
|
indio_dev->channels = quad8_channels; |
|
indio_dev->name = dev_name(dev); |
|
|
|
/* Initialize Counter device and driver data */ |
|
quad8iio = iio_priv(indio_dev); |
|
quad8iio->counter.name = dev_name(dev); |
|
quad8iio->counter.parent = dev; |
|
quad8iio->counter.ops = &quad8_ops; |
|
quad8iio->counter.counts = quad8_counts; |
|
quad8iio->counter.num_counts = ARRAY_SIZE(quad8_counts); |
|
quad8iio->counter.signals = quad8_signals; |
|
quad8iio->counter.num_signals = ARRAY_SIZE(quad8_signals); |
|
quad8iio->counter.priv = quad8iio; |
|
quad8iio->base = base[id]; |
|
|
|
/* Initialize mutex */ |
|
mutex_init(&quad8iio->lock); |
|
|
|
/* Reset all counters and disable interrupt function */ |
|
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); |
|
/* Set initial configuration for all counters */ |
|
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) { |
|
base_offset = base[id] + 2 * i; |
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
/* Reset filter clock factor */ |
|
outb(0, base_offset); |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, |
|
base_offset + 1); |
|
/* Reset Byte Pointer */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); |
|
/* Reset Preset Register */ |
|
for (j = 0; j < 3; j++) |
|
outb(0x00, base_offset); |
|
/* Reset Borrow, Carry, Compare, and Sign flags */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); |
|
/* Reset Error flag */ |
|
outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); |
|
/* Binary encoding; Normal count; non-quadrature mode */ |
|
outb(QUAD8_CTR_CMR, base_offset + 1); |
|
/* Disable A and B inputs; preset on index; FLG1 as Carry */ |
|
outb(QUAD8_CTR_IOR, base_offset + 1); |
|
/* Disable index function; negative index polarity */ |
|
outb(QUAD8_CTR_IDR, base_offset + 1); |
|
} |
|
/* Disable Differential Encoder Cable Status for all channels */ |
|
outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS); |
|
/* Enable all counters */ |
|
outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); |
|
|
|
/* Register IIO device */ |
|
err = devm_iio_device_register(dev, indio_dev); |
|
if (err) |
|
return err; |
|
|
|
/* Register Counter device */ |
|
return devm_counter_register(dev, &quad8iio->counter); |
|
} |
|
|
|
static struct isa_driver quad8_driver = { |
|
.probe = quad8_probe, |
|
.driver = { |
|
.name = "104-quad-8" |
|
} |
|
}; |
|
|
|
module_isa_driver(quad8_driver, num_quad8); |
|
|
|
MODULE_AUTHOR("William Breathitt Gray <[email protected]>"); |
|
MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|