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550 lines
13 KiB
550 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* HP zx1 AGPGART routines. |
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* |
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* (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P. |
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* Bjorn Helgaas <[email protected]> |
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*/ |
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|
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#include <linux/acpi.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/agp_backend.h> |
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#include <linux/log2.h> |
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#include <linux/slab.h> |
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#include <asm/acpi-ext.h> |
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#include "agp.h" |
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#define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ |
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|
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/* HP ZX1 IOC registers */ |
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#define HP_ZX1_IBASE 0x300 |
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#define HP_ZX1_IMASK 0x308 |
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#define HP_ZX1_PCOM 0x310 |
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#define HP_ZX1_TCNFG 0x318 |
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#define HP_ZX1_PDIR_BASE 0x320 |
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#define HP_ZX1_IOVA_BASE GB(1UL) |
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#define HP_ZX1_IOVA_SIZE GB(1UL) |
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#define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2) |
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#define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL |
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#define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL |
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#define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift) |
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#define AGP8X_MODE_BIT 3 |
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#define AGP8X_MODE (1 << AGP8X_MODE_BIT) |
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/* AGP bridge need not be PCI device, but DRM thinks it is. */ |
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static struct pci_dev fake_bridge_dev; |
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static int hp_zx1_gart_found; |
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static struct aper_size_info_fixed hp_zx1_sizes[] = |
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{ |
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{0, 0, 0}, /* filled in by hp_zx1_fetch_size() */ |
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}; |
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static struct gatt_mask hp_zx1_masks[] = |
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{ |
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{.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0} |
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}; |
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static struct _hp_private { |
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volatile u8 __iomem *ioc_regs; |
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volatile u8 __iomem *lba_regs; |
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int lba_cap_offset; |
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u64 *io_pdir; // PDIR for entire IOVA |
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u64 *gatt; // PDIR just for GART (subset of above) |
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u64 gatt_entries; |
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u64 iova_base; |
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u64 gart_base; |
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u64 gart_size; |
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u64 io_pdir_size; |
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int io_pdir_owner; // do we own it, or share it with sba_iommu? |
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int io_page_size; |
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int io_tlb_shift; |
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int io_tlb_ps; // IOC ps config |
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int io_pages_per_kpage; |
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} hp_private; |
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static int __init hp_zx1_ioc_shared(void) |
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{ |
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struct _hp_private *hp = &hp_private; |
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printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n"); |
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/* |
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* IOC already configured by sba_iommu module; just use |
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* its setup. We assume: |
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* - IOVA space is 1Gb in size |
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* - first 512Mb is IOMMU, second 512Mb is GART |
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*/ |
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hp->io_tlb_ps = readq(hp->ioc_regs+HP_ZX1_TCNFG); |
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switch (hp->io_tlb_ps) { |
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case 0: hp->io_tlb_shift = 12; break; |
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case 1: hp->io_tlb_shift = 13; break; |
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case 2: hp->io_tlb_shift = 14; break; |
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case 3: hp->io_tlb_shift = 16; break; |
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default: |
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printk(KERN_ERR PFX "Invalid IOTLB page size " |
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"configuration 0x%x\n", hp->io_tlb_ps); |
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hp->gatt = NULL; |
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hp->gatt_entries = 0; |
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return -ENODEV; |
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} |
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hp->io_page_size = 1 << hp->io_tlb_shift; |
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hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size; |
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hp->iova_base = readq(hp->ioc_regs+HP_ZX1_IBASE) & ~0x1; |
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hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE; |
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hp->gart_size = HP_ZX1_GART_SIZE; |
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hp->gatt_entries = hp->gart_size / hp->io_page_size; |
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hp->io_pdir = phys_to_virt(readq(hp->ioc_regs+HP_ZX1_PDIR_BASE)); |
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hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)]; |
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if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) { |
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/* Normal case when no AGP device in system */ |
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hp->gatt = NULL; |
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hp->gatt_entries = 0; |
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printk(KERN_ERR PFX "No reserved IO PDIR entry found; " |
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"GART disabled\n"); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static int __init |
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hp_zx1_ioc_owner (void) |
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{ |
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struct _hp_private *hp = &hp_private; |
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printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n"); |
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/* |
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* Select an IOV page size no larger than system page size. |
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*/ |
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if (PAGE_SIZE >= KB(64)) { |
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hp->io_tlb_shift = 16; |
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hp->io_tlb_ps = 3; |
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} else if (PAGE_SIZE >= KB(16)) { |
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hp->io_tlb_shift = 14; |
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hp->io_tlb_ps = 2; |
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} else if (PAGE_SIZE >= KB(8)) { |
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hp->io_tlb_shift = 13; |
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hp->io_tlb_ps = 1; |
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} else { |
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hp->io_tlb_shift = 12; |
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hp->io_tlb_ps = 0; |
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} |
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hp->io_page_size = 1 << hp->io_tlb_shift; |
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hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size; |
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hp->iova_base = HP_ZX1_IOVA_BASE; |
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hp->gart_size = HP_ZX1_GART_SIZE; |
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hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size; |
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hp->gatt_entries = hp->gart_size / hp->io_page_size; |
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hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64); |
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return 0; |
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} |
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static int __init |
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hp_zx1_ioc_init (u64 hpa) |
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{ |
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struct _hp_private *hp = &hp_private; |
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hp->ioc_regs = ioremap(hpa, 1024); |
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if (!hp->ioc_regs) |
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return -ENOMEM; |
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/* |
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* If the IOTLB is currently disabled, we can take it over. |
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* Otherwise, we have to share with sba_iommu. |
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*/ |
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hp->io_pdir_owner = (readq(hp->ioc_regs+HP_ZX1_IBASE) & 0x1) == 0; |
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if (hp->io_pdir_owner) |
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return hp_zx1_ioc_owner(); |
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return hp_zx1_ioc_shared(); |
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} |
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static int |
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hp_zx1_lba_find_capability (volatile u8 __iomem *hpa, int cap) |
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{ |
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u16 status; |
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u8 pos, id; |
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int ttl = 48; |
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status = readw(hpa+PCI_STATUS); |
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if (!(status & PCI_STATUS_CAP_LIST)) |
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return 0; |
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pos = readb(hpa+PCI_CAPABILITY_LIST); |
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while (ttl-- && pos >= 0x40) { |
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pos &= ~3; |
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id = readb(hpa+pos+PCI_CAP_LIST_ID); |
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if (id == 0xff) |
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break; |
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if (id == cap) |
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return pos; |
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pos = readb(hpa+pos+PCI_CAP_LIST_NEXT); |
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} |
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return 0; |
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} |
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static int __init |
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hp_zx1_lba_init (u64 hpa) |
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{ |
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struct _hp_private *hp = &hp_private; |
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int cap; |
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hp->lba_regs = ioremap(hpa, 256); |
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if (!hp->lba_regs) |
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return -ENOMEM; |
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hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP); |
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cap = readl(hp->lba_regs+hp->lba_cap_offset) & 0xff; |
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if (cap != PCI_CAP_ID_AGP) { |
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printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n", |
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cap, hp->lba_cap_offset); |
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iounmap(hp->lba_regs); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static int |
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hp_zx1_fetch_size(void) |
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{ |
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int size; |
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size = hp_private.gart_size / MB(1); |
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hp_zx1_sizes[0].size = size; |
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agp_bridge->current_size = (void *) &hp_zx1_sizes[0]; |
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return size; |
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} |
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static int |
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hp_zx1_configure (void) |
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{ |
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struct _hp_private *hp = &hp_private; |
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agp_bridge->gart_bus_addr = hp->gart_base; |
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agp_bridge->capndx = hp->lba_cap_offset; |
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agp_bridge->mode = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS); |
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if (hp->io_pdir_owner) { |
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writel(virt_to_phys(hp->io_pdir), hp->ioc_regs+HP_ZX1_PDIR_BASE); |
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readl(hp->ioc_regs+HP_ZX1_PDIR_BASE); |
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writel(hp->io_tlb_ps, hp->ioc_regs+HP_ZX1_TCNFG); |
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readl(hp->ioc_regs+HP_ZX1_TCNFG); |
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writel((unsigned int)(~(HP_ZX1_IOVA_SIZE-1)), hp->ioc_regs+HP_ZX1_IMASK); |
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readl(hp->ioc_regs+HP_ZX1_IMASK); |
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writel(hp->iova_base|1, hp->ioc_regs+HP_ZX1_IBASE); |
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readl(hp->ioc_regs+HP_ZX1_IBASE); |
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writel(hp->iova_base|ilog2(HP_ZX1_IOVA_SIZE), hp->ioc_regs+HP_ZX1_PCOM); |
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readl(hp->ioc_regs+HP_ZX1_PCOM); |
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} |
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return 0; |
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} |
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static void |
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hp_zx1_cleanup (void) |
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{ |
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struct _hp_private *hp = &hp_private; |
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if (hp->ioc_regs) { |
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if (hp->io_pdir_owner) { |
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writeq(0, hp->ioc_regs+HP_ZX1_IBASE); |
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readq(hp->ioc_regs+HP_ZX1_IBASE); |
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} |
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iounmap(hp->ioc_regs); |
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} |
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if (hp->lba_regs) |
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iounmap(hp->lba_regs); |
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} |
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static void |
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hp_zx1_tlbflush (struct agp_memory *mem) |
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{ |
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struct _hp_private *hp = &hp_private; |
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writeq(hp->gart_base | ilog2(hp->gart_size), hp->ioc_regs+HP_ZX1_PCOM); |
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readq(hp->ioc_regs+HP_ZX1_PCOM); |
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} |
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static int |
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hp_zx1_create_gatt_table (struct agp_bridge_data *bridge) |
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{ |
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struct _hp_private *hp = &hp_private; |
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int i; |
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if (hp->io_pdir_owner) { |
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hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL, |
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get_order(hp->io_pdir_size)); |
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if (!hp->io_pdir) { |
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printk(KERN_ERR PFX "Couldn't allocate contiguous " |
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"memory for I/O PDIR\n"); |
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hp->gatt = NULL; |
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hp->gatt_entries = 0; |
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return -ENOMEM; |
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} |
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memset(hp->io_pdir, 0, hp->io_pdir_size); |
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hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)]; |
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} |
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for (i = 0; i < hp->gatt_entries; i++) { |
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hp->gatt[i] = (unsigned long) agp_bridge->scratch_page; |
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} |
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return 0; |
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} |
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static int |
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hp_zx1_free_gatt_table (struct agp_bridge_data *bridge) |
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{ |
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struct _hp_private *hp = &hp_private; |
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if (hp->io_pdir_owner) |
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free_pages((unsigned long) hp->io_pdir, |
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get_order(hp->io_pdir_size)); |
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else |
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hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE; |
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return 0; |
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} |
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static int |
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hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type) |
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{ |
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struct _hp_private *hp = &hp_private; |
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int i, k; |
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off_t j, io_pg_start; |
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int io_pg_count; |
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if (type != mem->type || |
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
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return -EINVAL; |
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} |
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io_pg_start = hp->io_pages_per_kpage * pg_start; |
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io_pg_count = hp->io_pages_per_kpage * mem->page_count; |
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if ((io_pg_start + io_pg_count) > hp->gatt_entries) { |
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return -EINVAL; |
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} |
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j = io_pg_start; |
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while (j < (io_pg_start + io_pg_count)) { |
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if (hp->gatt[j]) { |
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return -EBUSY; |
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} |
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j++; |
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} |
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if (!mem->is_flushed) { |
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global_cache_flush(); |
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mem->is_flushed = true; |
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} |
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for (i = 0, j = io_pg_start; i < mem->page_count; i++) { |
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unsigned long paddr; |
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paddr = page_to_phys(mem->pages[i]); |
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for (k = 0; |
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k < hp->io_pages_per_kpage; |
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k++, j++, paddr += hp->io_page_size) { |
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hp->gatt[j] = HP_ZX1_PDIR_VALID_BIT | paddr; |
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} |
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} |
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agp_bridge->driver->tlb_flush(mem); |
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return 0; |
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} |
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static int |
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hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type) |
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{ |
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struct _hp_private *hp = &hp_private; |
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int i, io_pg_start, io_pg_count; |
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if (type != mem->type || |
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
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return -EINVAL; |
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} |
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io_pg_start = hp->io_pages_per_kpage * pg_start; |
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io_pg_count = hp->io_pages_per_kpage * mem->page_count; |
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for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { |
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hp->gatt[i] = agp_bridge->scratch_page; |
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} |
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agp_bridge->driver->tlb_flush(mem); |
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return 0; |
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} |
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static unsigned long |
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hp_zx1_mask_memory (struct agp_bridge_data *bridge, dma_addr_t addr, int type) |
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{ |
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return HP_ZX1_PDIR_VALID_BIT | addr; |
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} |
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static void |
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hp_zx1_enable (struct agp_bridge_data *bridge, u32 mode) |
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{ |
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struct _hp_private *hp = &hp_private; |
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u32 command; |
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command = readl(hp->lba_regs+hp->lba_cap_offset+PCI_AGP_STATUS); |
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command = agp_collect_device_status(bridge, mode, command); |
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command |= 0x00000100; |
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writel(command, hp->lba_regs+hp->lba_cap_offset+PCI_AGP_COMMAND); |
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agp_device_command(command, (mode & AGP8X_MODE) != 0); |
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} |
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const struct agp_bridge_driver hp_zx1_driver = { |
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.owner = THIS_MODULE, |
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.size_type = FIXED_APER_SIZE, |
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.configure = hp_zx1_configure, |
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.fetch_size = hp_zx1_fetch_size, |
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.cleanup = hp_zx1_cleanup, |
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.tlb_flush = hp_zx1_tlbflush, |
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.mask_memory = hp_zx1_mask_memory, |
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.masks = hp_zx1_masks, |
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.agp_enable = hp_zx1_enable, |
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.cache_flush = global_cache_flush, |
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.create_gatt_table = hp_zx1_create_gatt_table, |
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.free_gatt_table = hp_zx1_free_gatt_table, |
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.insert_memory = hp_zx1_insert_memory, |
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.remove_memory = hp_zx1_remove_memory, |
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.alloc_by_type = agp_generic_alloc_by_type, |
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.free_by_type = agp_generic_free_by_type, |
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.agp_alloc_page = agp_generic_alloc_page, |
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.agp_alloc_pages = agp_generic_alloc_pages, |
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.agp_destroy_page = agp_generic_destroy_page, |
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.agp_destroy_pages = agp_generic_destroy_pages, |
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.agp_type_to_mask_type = agp_generic_type_to_mask_type, |
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.cant_use_aperture = true, |
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}; |
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static int __init |
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hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa) |
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{ |
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struct agp_bridge_data *bridge; |
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int error = 0; |
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error = hp_zx1_ioc_init(ioc_hpa); |
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if (error) |
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goto fail; |
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error = hp_zx1_lba_init(lba_hpa); |
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if (error) |
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goto fail; |
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bridge = agp_alloc_bridge(); |
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if (!bridge) { |
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error = -ENOMEM; |
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goto fail; |
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} |
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bridge->driver = &hp_zx1_driver; |
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fake_bridge_dev.vendor = PCI_VENDOR_ID_HP; |
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fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA; |
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bridge->dev = &fake_bridge_dev; |
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error = agp_add_bridge(bridge); |
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fail: |
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if (error) |
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hp_zx1_cleanup(); |
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return error; |
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} |
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static acpi_status __init |
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zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret) |
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{ |
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acpi_handle handle, parent; |
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acpi_status status; |
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struct acpi_device_info *info; |
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u64 lba_hpa, sba_hpa, length; |
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int match; |
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status = hp_acpi_csr_space(obj, &lba_hpa, &length); |
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if (ACPI_FAILURE(status)) |
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return AE_OK; /* keep looking for another bridge */ |
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/* Look for an enclosing IOC scope and find its CSR space */ |
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handle = obj; |
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do { |
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status = acpi_get_object_info(handle, &info); |
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if (ACPI_SUCCESS(status) && (info->valid & ACPI_VALID_HID)) { |
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/* TBD check _CID also */ |
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match = (strcmp(info->hardware_id.string, "HWP0001") == 0); |
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kfree(info); |
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if (match) { |
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status = hp_acpi_csr_space(handle, &sba_hpa, &length); |
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if (ACPI_SUCCESS(status)) |
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break; |
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else { |
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printk(KERN_ERR PFX "Detected HP ZX1 " |
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"AGP LBA but no IOC.\n"); |
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return AE_OK; |
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} |
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} |
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} |
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status = acpi_get_parent(handle, &parent); |
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handle = parent; |
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} while (ACPI_SUCCESS(status)); |
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if (ACPI_FAILURE(status)) |
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return AE_OK; /* found no enclosing IOC */ |
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if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa)) |
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return AE_OK; |
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printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset " |
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"(ioc=%llx, lba=%llx)\n", (char *)context, |
|
sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa); |
|
|
|
hp_zx1_gart_found = 1; |
|
return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */ |
|
} |
|
|
|
static int __init |
|
agp_hp_init (void) |
|
{ |
|
if (agp_off) |
|
return -EINVAL; |
|
|
|
acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL); |
|
if (hp_zx1_gart_found) |
|
return 0; |
|
|
|
acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL); |
|
if (hp_zx1_gart_found) |
|
return 0; |
|
|
|
return -ENODEV; |
|
} |
|
|
|
static void __exit |
|
agp_hp_cleanup (void) |
|
{ |
|
} |
|
|
|
module_init(agp_hp_init); |
|
module_exit(agp_hp_cleanup); |
|
|
|
MODULE_LICENSE("GPL and additional rights");
|
|
|