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584 lines
19 KiB
584 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $ |
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* |
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* newport.h: Defines and register layout for NEWPORT graphics |
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* hardware. |
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* |
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* Copyright (C) 1996 David S. Miller ([email protected]) |
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* |
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* Ulf Carlsson - Compatibility with the IRIX structures added |
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*/ |
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#ifndef _SGI_NEWPORT_H |
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#define _SGI_NEWPORT_H |
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typedef volatile unsigned int npireg_t; |
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union npfloat { |
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volatile float flt; |
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npireg_t word; |
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}; |
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typedef union npfloat npfreg_t; |
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union np_dcb { |
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npireg_t byword; |
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struct { volatile unsigned short s0, s1; } byshort; |
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struct { volatile unsigned char b0, b1, b2, b3; } bybytes; |
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}; |
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struct newport_rexregs { |
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npireg_t drawmode1; /* GL extra mode bits */ |
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#define DM1_PLANES 0x00000007 |
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#define DM1_NOPLANES 0x00000000 |
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#define DM1_RGBPLANES 0x00000001 |
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#define DM1_RGBAPLANES 0x00000002 |
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#define DM1_OLAYPLANES 0x00000004 |
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#define DM1_PUPPLANES 0x00000005 |
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#define DM1_CIDPLANES 0x00000006 |
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#define NPORT_DMODE1_DDMASK 0x00000018 |
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#define NPORT_DMODE1_DD4 0x00000000 |
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#define NPORT_DMODE1_DD8 0x00000008 |
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#define NPORT_DMODE1_DD12 0x00000010 |
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#define NPORT_DMODE1_DD24 0x00000018 |
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#define NPORT_DMODE1_DSRC 0x00000020 |
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#define NPORT_DMODE1_YFLIP 0x00000040 |
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#define NPORT_DMODE1_RWPCKD 0x00000080 |
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#define NPORT_DMODE1_HDMASK 0x00000300 |
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#define NPORT_DMODE1_HD4 0x00000000 |
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#define NPORT_DMODE1_HD8 0x00000100 |
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#define NPORT_DMODE1_HD12 0x00000200 |
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#define NPORT_DMODE1_HD32 0x00000300 |
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#define NPORT_DMODE1_RWDBL 0x00000400 |
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#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */ |
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#define NPORT_DMODE1_CCMASK 0x00007000 |
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#define NPORT_DMODE1_CCLT 0x00001000 |
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#define NPORT_DMODE1_CCEQ 0x00002000 |
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#define NPORT_DMODE1_CCGT 0x00004000 |
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#define NPORT_DMODE1_RGBMD 0x00008000 |
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#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */ |
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#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */ |
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#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */ |
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#define NPORT_DMODE1_SFMASK 0x00380000 |
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#define NPORT_DMODE1_SF0 0x00000000 |
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#define NPORT_DMODE1_SF1 0x00080000 |
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#define NPORT_DMODE1_SFDC 0x00100000 |
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#define NPORT_DMODE1_SFMDC 0x00180000 |
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#define NPORT_DMODE1_SFSA 0x00200000 |
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#define NPORT_DMODE1_SFMSA 0x00280000 |
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#define NPORT_DMODE1_DFMASK 0x01c00000 |
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#define NPORT_DMODE1_DF0 0x00000000 |
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#define NPORT_DMODE1_DF1 0x00400000 |
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#define NPORT_DMODE1_DFSC 0x00800000 |
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#define NPORT_DMODE1_DFMSC 0x00c00000 |
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#define NPORT_DMODE1_DFSA 0x01000000 |
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#define NPORT_DMODE1_DFMSA 0x01400000 |
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#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */ |
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#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */ |
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#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */ |
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#define NPORT_DMODE1_LOMASK 0xf0000000 |
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#define NPORT_DMODE1_LOZERO 0x00000000 |
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#define NPORT_DMODE1_LOAND 0x10000000 |
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#define NPORT_DMODE1_LOANDR 0x20000000 |
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#define NPORT_DMODE1_LOSRC 0x30000000 |
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#define NPORT_DMODE1_LOANDI 0x40000000 |
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#define NPORT_DMODE1_LODST 0x50000000 |
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#define NPORT_DMODE1_LOXOR 0x60000000 |
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#define NPORT_DMODE1_LOOR 0x70000000 |
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#define NPORT_DMODE1_LONOR 0x80000000 |
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#define NPORT_DMODE1_LOXNOR 0x90000000 |
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#define NPORT_DMODE1_LONDST 0xa0000000 |
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#define NPORT_DMODE1_LOORR 0xb0000000 |
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#define NPORT_DMODE1_LONSRC 0xc0000000 |
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#define NPORT_DMODE1_LOORI 0xd0000000 |
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#define NPORT_DMODE1_LONAND 0xe0000000 |
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#define NPORT_DMODE1_LOONE 0xf0000000 |
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npireg_t drawmode0; /* REX command register */ |
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/* These bits define the graphics opcode being performed. */ |
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#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */ |
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#define NPORT_DMODE0_NOP 0x00000000 /* No operation */ |
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#define NPORT_DMODE0_RD 0x00000001 /* Read operation */ |
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#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */ |
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#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */ |
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/* The following decide what addressing mode(s) are to be used */ |
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#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */ |
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#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */ |
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#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */ |
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#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */ |
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#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */ |
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#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */ |
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#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */ |
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#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */ |
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/* And now some misc. operation control bits. */ |
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#define NPORT_DMODE0_DOSETUP 0x00000020 |
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#define NPORT_DMODE0_CHOST 0x00000040 |
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#define NPORT_DMODE0_AHOST 0x00000080 |
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#define NPORT_DMODE0_STOPX 0x00000100 |
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#define NPORT_DMODE0_STOPY 0x00000200 |
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#define NPORT_DMODE0_SK1ST 0x00000400 |
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#define NPORT_DMODE0_SKLST 0x00000800 |
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#define NPORT_DMODE0_ZPENAB 0x00001000 |
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#define NPORT_DMODE0_LISPENAB 0x00002000 |
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#define NPORT_DMODE0_LISLST 0x00004000 |
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#define NPORT_DMODE0_L32 0x00008000 |
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#define NPORT_DMODE0_ZOPQ 0x00010000 |
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#define NPORT_DMODE0_LISOPQ 0x00020000 |
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#define NPORT_DMODE0_SHADE 0x00040000 |
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#define NPORT_DMODE0_LRONLY 0x00080000 |
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#define NPORT_DMODE0_XYOFF 0x00100000 |
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#define NPORT_DMODE0_CLAMP 0x00200000 |
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#define NPORT_DMODE0_ENDPF 0x00400000 |
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#define NPORT_DMODE0_YSTR 0x00800000 |
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npireg_t lsmode; /* Mode for line stipple ops */ |
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npireg_t lspattern; /* Pattern for line stipple ops */ |
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npireg_t lspatsave; /* Backup save pattern */ |
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npireg_t zpattern; /* Pixel zpattern */ |
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npireg_t colorback; /* Background color */ |
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npireg_t colorvram; /* Clear color for fast vram */ |
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npireg_t alpharef; /* Reference value for afunctions */ |
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unsigned int pad0; |
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npireg_t smask0x; /* Window GL relative screen mask 0 */ |
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npireg_t smask0y; /* Window GL relative screen mask 0 */ |
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npireg_t _setup; |
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npireg_t _stepz; |
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npireg_t _lsrestore; |
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npireg_t _lssave; |
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unsigned int _pad1[0x30]; |
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/* Iterators, full state for context switch */ |
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npfreg_t _xstart; /* X-start point (current) */ |
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npfreg_t _ystart; /* Y-start point (current) */ |
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npfreg_t _xend; /* x-end point */ |
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npfreg_t _yend; /* y-end point */ |
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npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */ |
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npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */ |
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npfreg_t bresd; |
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npfreg_t bress1; |
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npireg_t bresoctinc1; |
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volatile int bresrndinc2; |
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npireg_t brese1; |
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npireg_t bress2; |
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npireg_t aweight0; |
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npireg_t aweight1; |
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npfreg_t xstartf; |
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npfreg_t ystartf; |
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npfreg_t xendf; |
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npfreg_t yendf; |
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npireg_t xstarti; |
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npfreg_t xendf1; |
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npireg_t xystarti; |
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npireg_t xyendi; |
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npireg_t xstartendi; |
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unsigned int _unused2[0x29]; |
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npfreg_t colorred; |
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npfreg_t coloralpha; |
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npfreg_t colorgrn; |
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npfreg_t colorblue; |
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npfreg_t slopered; |
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npfreg_t slopealpha; |
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npfreg_t slopegrn; |
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npfreg_t slopeblue; |
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npireg_t wrmask; |
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npireg_t colori; |
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npfreg_t colorx; |
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npfreg_t slopered1; |
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npireg_t hostrw0; |
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npireg_t hostrw1; |
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npireg_t dcbmode; |
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#define NPORT_DMODE_WMASK 0x00000003 |
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#define NPORT_DMODE_W4 0x00000000 |
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#define NPORT_DMODE_W1 0x00000001 |
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#define NPORT_DMODE_W2 0x00000002 |
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#define NPORT_DMODE_W3 0x00000003 |
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#define NPORT_DMODE_EDPACK 0x00000004 |
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#define NPORT_DMODE_ECINC 0x00000008 |
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#define NPORT_DMODE_CMASK 0x00000070 |
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#define NPORT_DMODE_AMASK 0x00000780 |
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#define NPORT_DMODE_AVC2 0x00000000 |
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#define NPORT_DMODE_ACMALL 0x00000080 |
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#define NPORT_DMODE_ACM0 0x00000100 |
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#define NPORT_DMODE_ACM1 0x00000180 |
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#define NPORT_DMODE_AXMALL 0x00000200 |
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#define NPORT_DMODE_AXM0 0x00000280 |
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#define NPORT_DMODE_AXM1 0x00000300 |
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#define NPORT_DMODE_ABT 0x00000380 |
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#define NPORT_DMODE_AVCC1 0x00000400 |
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#define NPORT_DMODE_AVAB1 0x00000480 |
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#define NPORT_DMODE_ALG3V0 0x00000500 |
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#define NPORT_DMODE_A1562 0x00000580 |
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#define NPORT_DMODE_ESACK 0x00000800 |
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#define NPORT_DMODE_EASACK 0x00001000 |
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#define NPORT_DMODE_CWMASK 0x0003e000 |
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#define NPORT_DMODE_CHMASK 0x007c0000 |
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#define NPORT_DMODE_CSMASK 0x0f800000 |
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#define NPORT_DMODE_SENDIAN 0x10000000 |
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unsigned int _unused3; |
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union np_dcb dcbdata0; |
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npireg_t dcbdata1; |
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}; |
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struct newport_cregs { |
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npireg_t smask1x; |
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npireg_t smask1y; |
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npireg_t smask2x; |
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npireg_t smask2y; |
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npireg_t smask3x; |
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npireg_t smask3y; |
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npireg_t smask4x; |
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npireg_t smask4y; |
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npireg_t topscan; |
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npireg_t xywin; |
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npireg_t clipmode; |
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#define NPORT_CMODE_SM0 0x00000001 |
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#define NPORT_CMODE_SM1 0x00000002 |
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#define NPORT_CMODE_SM2 0x00000004 |
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#define NPORT_CMODE_SM3 0x00000008 |
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#define NPORT_CMODE_SM4 0x00000010 |
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#define NPORT_CMODE_CMSK 0x00001e00 |
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unsigned int _unused0; |
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unsigned int config; |
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#define NPORT_CFG_G32MD 0x00000001 |
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#define NPORT_CFG_BWIDTH 0x00000002 |
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#define NPORT_CFG_ERCVR 0x00000004 |
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#define NPORT_CFG_BDMSK 0x00000078 |
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#define NPORT_CFG_BFAINT 0x00000080 |
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#define NPORT_CFG_GDMSK 0x00001f80 |
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#define NPORT_CFG_GD0 0x00000100 |
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#define NPORT_CFG_GD1 0x00000200 |
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#define NPORT_CFG_GD2 0x00000400 |
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#define NPORT_CFG_GD3 0x00000800 |
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#define NPORT_CFG_GD4 0x00001000 |
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#define NPORT_CFG_GFAINT 0x00002000 |
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#define NPORT_CFG_TOMSK 0x0001c000 |
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#define NPORT_CFG_VRMSK 0x000e0000 |
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#define NPORT_CFG_FBTYP 0x00100000 |
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npireg_t _unused1; |
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npireg_t status; |
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#define NPORT_STAT_VERS 0x00000007 |
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#define NPORT_STAT_GBUSY 0x00000008 |
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#define NPORT_STAT_BBUSY 0x00000010 |
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#define NPORT_STAT_VRINT 0x00000020 |
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#define NPORT_STAT_VIDINT 0x00000040 |
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#define NPORT_STAT_GLMSK 0x00001f80 |
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#define NPORT_STAT_BLMSK 0x0007e000 |
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#define NPORT_STAT_BFIRQ 0x00080000 |
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#define NPORT_STAT_GFIRQ 0x00100000 |
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npireg_t ustatus; |
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npireg_t dcbreset; |
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}; |
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struct newport_regs { |
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struct newport_rexregs set; |
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unsigned int _unused0[0x16e]; |
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struct newport_rexregs go; |
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unsigned int _unused1[0x22e]; |
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struct newport_cregs cset; |
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unsigned int _unused2[0x1ef]; |
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struct newport_cregs cgo; |
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}; |
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typedef struct { |
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unsigned int drawmode1; |
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unsigned int drawmode0; |
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unsigned int lsmode; |
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unsigned int lspattern; |
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unsigned int lspatsave; |
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unsigned int zpattern; |
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unsigned int colorback; |
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unsigned int colorvram; |
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unsigned int alpharef; |
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unsigned int smask0x; |
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unsigned int smask0y; |
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unsigned int _xstart; |
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unsigned int _ystart; |
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unsigned int _xend; |
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unsigned int _yend; |
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unsigned int xsave; |
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unsigned int xymove; |
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unsigned int bresd; |
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unsigned int bress1; |
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unsigned int bresoctinc1; |
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unsigned int bresrndinc2; |
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unsigned int brese1; |
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unsigned int bress2; |
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unsigned int aweight0; |
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unsigned int aweight1; |
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unsigned int colorred; |
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unsigned int coloralpha; |
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unsigned int colorgrn; |
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unsigned int colorblue; |
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unsigned int slopered; |
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unsigned int slopealpha; |
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unsigned int slopegrn; |
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unsigned int slopeblue; |
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unsigned int wrmask; |
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unsigned int hostrw0; |
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unsigned int hostrw1; |
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/* configregs */ |
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unsigned int smask1x; |
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unsigned int smask1y; |
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unsigned int smask2x; |
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unsigned int smask2y; |
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unsigned int smask3x; |
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unsigned int smask3y; |
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unsigned int smask4x; |
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unsigned int smask4y; |
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unsigned int topscan; |
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unsigned int xywin; |
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unsigned int clipmode; |
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unsigned int config; |
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/* dcb registers */ |
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unsigned int dcbmode; |
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unsigned int dcbdata0; |
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unsigned int dcbdata1; |
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} newport_ctx; |
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/* Reading/writing VC2 registers. */ |
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#define VC2_REGADDR_INDEX 0x00000000 |
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#define VC2_REGADDR_IREG 0x00000010 |
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#define VC2_REGADDR_RAM 0x00000030 |
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#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000) |
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#define VC2_VLINET_ADDR 0x000 |
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#define VC2_VFRAMET_ADDR 0x400 |
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#define VC2_CGLYPH_ADDR 0x500 |
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/* Now the Indexed registers of the VC2. */ |
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#define VC2_IREG_VENTRY 0x00 |
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#define VC2_IREG_CENTRY 0x01 |
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#define VC2_IREG_CURSX 0x02 |
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#define VC2_IREG_CURSY 0x03 |
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#define VC2_IREG_CCURSX 0x04 |
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#define VC2_IREG_DENTRY 0x05 |
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#define VC2_IREG_SLEN 0x06 |
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#define VC2_IREG_RADDR 0x07 |
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#define VC2_IREG_VFPTR 0x08 |
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#define VC2_IREG_VLSPTR 0x09 |
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#define VC2_IREG_VLIR 0x0a |
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#define VC2_IREG_VLCTR 0x0b |
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#define VC2_IREG_CTPTR 0x0c |
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#define VC2_IREG_WCURSY 0x0d |
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#define VC2_IREG_DFPTR 0x0e |
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#define VC2_IREG_DLTPTR 0x0f |
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#define VC2_IREG_CONTROL 0x10 |
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#define VC2_IREG_CONFIG 0x20 |
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static inline void newport_vc2_set(struct newport_regs *regs, |
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unsigned char vc2ireg, |
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unsigned short val) |
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{ |
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regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 | |
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NPORT_DMODE_ECINC | VC2_PROTOCOL); |
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regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8); |
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} |
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static inline unsigned short newport_vc2_get(struct newport_regs *regs, |
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unsigned char vc2ireg) |
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{ |
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regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 | |
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NPORT_DMODE_ECINC | VC2_PROTOCOL); |
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regs->set.dcbdata0.bybytes.b3 = vc2ireg; |
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regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 | |
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NPORT_DMODE_ECINC | VC2_PROTOCOL); |
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return regs->set.dcbdata0.byshort.s1; |
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} |
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/* VC2 Control register bits */ |
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#define VC2_CTRL_EVIRQ 0x0001 |
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#define VC2_CTRL_EDISP 0x0002 |
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#define VC2_CTRL_EVIDEO 0x0004 |
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#define VC2_CTRL_EDIDS 0x0008 |
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#define VC2_CTRL_ECURS 0x0010 |
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#define VC2_CTRL_EGSYNC 0x0020 |
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#define VC2_CTRL_EILACE 0x0040 |
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#define VC2_CTRL_ECDISP 0x0080 |
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#define VC2_CTRL_ECCURS 0x0100 |
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#define VC2_CTRL_ECG64 0x0200 |
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#define VC2_CTRL_GLSEL 0x0400 |
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/* Controlling the color map on NEWPORT. */ |
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#define NCMAP_REGADDR_AREG 0x00000000 |
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#define NCMAP_REGADDR_ALO 0x00000000 |
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#define NCMAP_REGADDR_AHI 0x00000010 |
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#define NCMAP_REGADDR_PBUF 0x00000020 |
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#define NCMAP_REGADDR_CREG 0x00000030 |
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#define NCMAP_REGADDR_SREG 0x00000040 |
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#define NCMAP_REGADDR_RREG 0x00000060 |
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#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000) |
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static __inline__ void newport_cmap_setaddr(struct newport_regs *regs, |
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unsigned short addr) |
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{ |
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regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | |
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NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC | |
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NCMAP_REGADDR_AREG | NPORT_DMODE_W2); |
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regs->set.dcbdata0.byshort.s1 = addr; |
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regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | |
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NCMAP_REGADDR_PBUF | NPORT_DMODE_W3); |
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} |
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static __inline__ void newport_cmap_setrgb(struct newport_regs *regs, |
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unsigned char red, |
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unsigned char green, |
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unsigned char blue) |
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{ |
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regs->set.dcbdata0.byword = |
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(red << 24) | |
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(green << 16) | |
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(blue << 8); |
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} |
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/* Miscellaneous NEWPORT routines. */ |
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#define BUSY_TIMEOUT 100000 |
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static __inline__ int newport_wait(struct newport_regs *regs) |
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{ |
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int t = BUSY_TIMEOUT; |
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while (--t) |
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if (!(regs->cset.status & NPORT_STAT_GBUSY)) |
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break; |
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return !t; |
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} |
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static __inline__ int newport_bfwait(struct newport_regs *regs) |
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{ |
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int t = BUSY_TIMEOUT; |
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while (--t) |
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if(!(regs->cset.status & NPORT_STAT_BBUSY)) |
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break; |
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return !t; |
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} |
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/* |
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* DCBMODE register defines: |
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*/ |
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/* Width of the data being transferred for each DCBDATA[01] word */ |
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#define DCB_DATAWIDTH_4 0x0 |
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#define DCB_DATAWIDTH_1 0x1 |
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#define DCB_DATAWIDTH_2 0x2 |
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#define DCB_DATAWIDTH_3 0x3 |
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/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */ |
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#define DCB_ENDATAPACK (1 << 2) |
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/* Enables DCBCRS auto increment after each DCB transfer */ |
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#define DCB_ENCRSINC (1 << 3) |
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/* shift for accessing the control register select address (DBCCRS, 3 bits) */ |
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#define DCB_CRS_SHIFT 4 |
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/* DCBADDR (4 bits): display bus slave address */ |
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#define DCB_ADDR_SHIFT 7 |
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#define DCB_VC2 (0 << DCB_ADDR_SHIFT) |
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#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT) |
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#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT) |
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#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT) |
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#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT) |
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#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT) |
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#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT) |
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#define DCB_BT445 (7 << DCB_ADDR_SHIFT) |
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#define DCB_VCC1 (8 << DCB_ADDR_SHIFT) |
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#define DCB_VAB1 (9 << DCB_ADDR_SHIFT) |
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#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT) |
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#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT) |
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#define DCB_RESERVED (15 << DCB_ADDR_SHIFT) |
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/* DCB protocol ack types */ |
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#define DCB_ENSYNCACK (1 << 11) |
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#define DCB_ENASYNCACK (1 << 12) |
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#define DCB_CSWIDTH_SHIFT 13 |
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#define DCB_CSHOLD_SHIFT 18 |
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#define DCB_CSSETUP_SHIFT 23 |
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/* XMAP9 specific defines */ |
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/* XMAP9 -- registers as seen on the DCBMODE register*/ |
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# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT) |
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# define XM9_PUPMODE (1 << 0) |
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# define XM9_ODD_PIXEL (1 << 1) |
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# define XM9_8_BITPLANES (1 << 2) |
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# define XM9_SLOW_DCB (1 << 3) |
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# define XM9_VIDEO_RGBMAP_MASK (3 << 4) |
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# define XM9_EXPRESS_VIDEO (1 << 6) |
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# define XM9_VIDEO_OPTION (1 << 7) |
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# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT) |
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# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT) |
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# define XM9_FIFO_0_AVAIL 0 |
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# define XM9_FIFO_1_AVAIL 1 |
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# define XM9_FIFO_2_AVAIL 3 |
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# define XM9_FIFO_3_AVAIL 2 |
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# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL |
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# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL |
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# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT) |
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# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT) |
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# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT) |
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# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT) |
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#define DCB_CYCLES(setup,hold,width) \ |
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((hold << DCB_CSHOLD_SHIFT) | \ |
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(setup << DCB_CSSETUP_SHIFT)| \ |
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(width << DCB_CSWIDTH_SHIFT)) |
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#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0) |
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#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0) |
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#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0) |
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#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3) |
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static __inline__ void |
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xmap9FIFOWait (struct newport_regs *rex) |
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{ |
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rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | |
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DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; |
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newport_bfwait (rex); |
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while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) |
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; |
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} |
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static __inline__ void |
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xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq) |
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{ |
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if (cfreq > 119) |
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rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | |
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DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL; |
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else if (cfreq > 59) |
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rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | |
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DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL; |
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else |
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rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | |
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DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; |
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rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff); |
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} |
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#define BT445_PROTOCOL DCB_CYCLES(1,1,3) |
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#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT) |
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#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT) |
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#define BT445_REVISION_REG 0x01 |
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#endif /* !(_SGI_NEWPORT_H) */ |
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