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1329 lines
37 KiB
1329 lines
37 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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/* |
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* Performance events: |
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* |
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* Copyright (C) 2008-2009, Thomas Gleixner <[email protected]> |
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* Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar |
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* Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra |
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* |
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* Data type definitions, declarations, prototypes. |
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* |
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* Started by: Thomas Gleixner and Ingo Molnar |
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* |
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* For licencing details see kernel-base/COPYING |
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*/ |
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#ifndef _UAPI_LINUX_PERF_EVENT_H |
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#define _UAPI_LINUX_PERF_EVENT_H |
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|
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#include <linux/types.h> |
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#include <linux/ioctl.h> |
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#include <asm/byteorder.h> |
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|
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/* |
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* User-space ABI bits: |
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*/ |
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|
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/* |
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* attr.type |
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*/ |
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enum perf_type_id { |
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PERF_TYPE_HARDWARE = 0, |
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PERF_TYPE_SOFTWARE = 1, |
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PERF_TYPE_TRACEPOINT = 2, |
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PERF_TYPE_HW_CACHE = 3, |
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PERF_TYPE_RAW = 4, |
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PERF_TYPE_BREAKPOINT = 5, |
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PERF_TYPE_MAX, /* non-ABI */ |
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}; |
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|
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/* |
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* Generalized performance event event_id types, used by the |
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* attr.event_id parameter of the sys_perf_event_open() |
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* syscall: |
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*/ |
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enum perf_hw_id { |
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/* |
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* Common hardware events, generalized by the kernel: |
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*/ |
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PERF_COUNT_HW_CPU_CYCLES = 0, |
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PERF_COUNT_HW_INSTRUCTIONS = 1, |
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PERF_COUNT_HW_CACHE_REFERENCES = 2, |
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PERF_COUNT_HW_CACHE_MISSES = 3, |
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PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, |
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PERF_COUNT_HW_BRANCH_MISSES = 5, |
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PERF_COUNT_HW_BUS_CYCLES = 6, |
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PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, |
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PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, |
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PERF_COUNT_HW_REF_CPU_CYCLES = 9, |
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PERF_COUNT_HW_MAX, /* non-ABI */ |
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}; |
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|
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/* |
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* Generalized hardware cache events: |
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* |
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* { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x |
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* { read, write, prefetch } x |
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* { accesses, misses } |
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*/ |
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enum perf_hw_cache_id { |
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PERF_COUNT_HW_CACHE_L1D = 0, |
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PERF_COUNT_HW_CACHE_L1I = 1, |
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PERF_COUNT_HW_CACHE_LL = 2, |
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PERF_COUNT_HW_CACHE_DTLB = 3, |
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PERF_COUNT_HW_CACHE_ITLB = 4, |
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PERF_COUNT_HW_CACHE_BPU = 5, |
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PERF_COUNT_HW_CACHE_NODE = 6, |
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PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ |
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}; |
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enum perf_hw_cache_op_id { |
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PERF_COUNT_HW_CACHE_OP_READ = 0, |
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PERF_COUNT_HW_CACHE_OP_WRITE = 1, |
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PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, |
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PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ |
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}; |
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enum perf_hw_cache_op_result_id { |
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PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, |
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PERF_COUNT_HW_CACHE_RESULT_MISS = 1, |
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PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ |
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}; |
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/* |
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* Special "software" events provided by the kernel, even if the hardware |
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* does not support performance events. These events measure various |
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* physical and sw events of the kernel (and allow the profiling of them as |
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* well): |
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*/ |
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enum perf_sw_ids { |
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PERF_COUNT_SW_CPU_CLOCK = 0, |
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PERF_COUNT_SW_TASK_CLOCK = 1, |
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PERF_COUNT_SW_PAGE_FAULTS = 2, |
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PERF_COUNT_SW_CONTEXT_SWITCHES = 3, |
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PERF_COUNT_SW_CPU_MIGRATIONS = 4, |
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PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, |
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PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, |
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PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, |
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PERF_COUNT_SW_EMULATION_FAULTS = 8, |
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PERF_COUNT_SW_DUMMY = 9, |
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PERF_COUNT_SW_BPF_OUTPUT = 10, |
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PERF_COUNT_SW_MAX, /* non-ABI */ |
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}; |
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/* |
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* Bits that can be set in attr.sample_type to request information |
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* in the overflow packets. |
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*/ |
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enum perf_event_sample_format { |
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PERF_SAMPLE_IP = 1U << 0, |
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PERF_SAMPLE_TID = 1U << 1, |
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PERF_SAMPLE_TIME = 1U << 2, |
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PERF_SAMPLE_ADDR = 1U << 3, |
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PERF_SAMPLE_READ = 1U << 4, |
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PERF_SAMPLE_CALLCHAIN = 1U << 5, |
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PERF_SAMPLE_ID = 1U << 6, |
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PERF_SAMPLE_CPU = 1U << 7, |
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PERF_SAMPLE_PERIOD = 1U << 8, |
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PERF_SAMPLE_STREAM_ID = 1U << 9, |
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PERF_SAMPLE_RAW = 1U << 10, |
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PERF_SAMPLE_BRANCH_STACK = 1U << 11, |
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PERF_SAMPLE_REGS_USER = 1U << 12, |
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PERF_SAMPLE_STACK_USER = 1U << 13, |
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PERF_SAMPLE_WEIGHT = 1U << 14, |
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PERF_SAMPLE_DATA_SRC = 1U << 15, |
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PERF_SAMPLE_IDENTIFIER = 1U << 16, |
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PERF_SAMPLE_TRANSACTION = 1U << 17, |
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PERF_SAMPLE_REGS_INTR = 1U << 18, |
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PERF_SAMPLE_PHYS_ADDR = 1U << 19, |
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PERF_SAMPLE_AUX = 1U << 20, |
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PERF_SAMPLE_CGROUP = 1U << 21, |
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PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, |
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PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, |
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PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, |
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PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ |
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__PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ |
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}; |
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#define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) |
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/* |
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* values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set |
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* |
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* If the user does not pass priv level information via branch_sample_type, |
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* the kernel uses the event's priv level. Branch and event priv levels do |
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* not have to match. Branch priv level is checked for permissions. |
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* |
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* The branch types can be combined, however BRANCH_ANY covers all types |
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* of branches and therefore it supersedes all the other types. |
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*/ |
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enum perf_branch_sample_type_shift { |
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PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ |
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PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ |
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PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ |
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PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ |
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PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ |
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PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ |
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PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ |
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PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ |
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PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ |
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PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ |
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PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ |
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PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ |
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PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ |
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PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ |
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PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ |
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PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ |
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PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ |
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PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ |
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PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ |
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}; |
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enum perf_branch_sample_type { |
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PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, |
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PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, |
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PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, |
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PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, |
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PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, |
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PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, |
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PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, |
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PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, |
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PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, |
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PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, |
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PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, |
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PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, |
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PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, |
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PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, |
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PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, |
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PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, |
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PERF_SAMPLE_BRANCH_TYPE_SAVE = |
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1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, |
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PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, |
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PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, |
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}; |
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/* |
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* Common flow change classification |
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*/ |
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enum { |
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PERF_BR_UNKNOWN = 0, /* unknown */ |
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PERF_BR_COND = 1, /* conditional */ |
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PERF_BR_UNCOND = 2, /* unconditional */ |
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PERF_BR_IND = 3, /* indirect */ |
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PERF_BR_CALL = 4, /* function call */ |
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PERF_BR_IND_CALL = 5, /* indirect function call */ |
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PERF_BR_RET = 6, /* function return */ |
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PERF_BR_SYSCALL = 7, /* syscall */ |
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PERF_BR_SYSRET = 8, /* syscall return */ |
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PERF_BR_COND_CALL = 9, /* conditional function call */ |
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PERF_BR_COND_RET = 10, /* conditional function return */ |
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PERF_BR_MAX, |
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}; |
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#define PERF_SAMPLE_BRANCH_PLM_ALL \ |
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(PERF_SAMPLE_BRANCH_USER|\ |
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PERF_SAMPLE_BRANCH_KERNEL|\ |
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PERF_SAMPLE_BRANCH_HV) |
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/* |
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* Values to determine ABI of the registers dump. |
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*/ |
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enum perf_sample_regs_abi { |
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PERF_SAMPLE_REGS_ABI_NONE = 0, |
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PERF_SAMPLE_REGS_ABI_32 = 1, |
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PERF_SAMPLE_REGS_ABI_64 = 2, |
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}; |
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/* |
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* Values for the memory transaction event qualifier, mostly for |
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* abort events. Multiple bits can be set. |
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*/ |
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enum { |
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PERF_TXN_ELISION = (1 << 0), /* From elision */ |
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PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ |
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PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ |
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PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ |
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PERF_TXN_RETRY = (1 << 4), /* Retry possible */ |
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PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ |
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PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ |
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PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ |
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PERF_TXN_MAX = (1 << 8), /* non-ABI */ |
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/* bits 32..63 are reserved for the abort code */ |
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PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), |
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PERF_TXN_ABORT_SHIFT = 32, |
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}; |
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/* |
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* The format of the data returned by read() on a perf event fd, |
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* as specified by attr.read_format: |
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* |
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* struct read_format { |
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* { u64 value; |
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* { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED |
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* { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING |
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* { u64 id; } && PERF_FORMAT_ID |
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* } && !PERF_FORMAT_GROUP |
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* |
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* { u64 nr; |
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* { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED |
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* { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING |
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* { u64 value; |
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* { u64 id; } && PERF_FORMAT_ID |
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* } cntr[nr]; |
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* } && PERF_FORMAT_GROUP |
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* }; |
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*/ |
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enum perf_event_read_format { |
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PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, |
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PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, |
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PERF_FORMAT_ID = 1U << 2, |
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PERF_FORMAT_GROUP = 1U << 3, |
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PERF_FORMAT_MAX = 1U << 4, /* non-ABI */ |
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}; |
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#define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ |
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#define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ |
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#define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ |
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#define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ |
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/* add: sample_stack_user */ |
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#define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ |
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#define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ |
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#define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ |
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/* |
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* Hardware event_id to monitor via a performance monitoring event: |
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* |
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* @sample_max_stack: Max number of frame pointers in a callchain, |
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* should be < /proc/sys/kernel/perf_event_max_stack |
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*/ |
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struct perf_event_attr { |
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/* |
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* Major type: hardware/software/tracepoint/etc. |
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*/ |
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__u32 type; |
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/* |
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* Size of the attr structure, for fwd/bwd compat. |
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*/ |
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__u32 size; |
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/* |
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* Type specific configuration information. |
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*/ |
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__u64 config; |
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union { |
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__u64 sample_period; |
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__u64 sample_freq; |
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}; |
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__u64 sample_type; |
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__u64 read_format; |
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__u64 disabled : 1, /* off by default */ |
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inherit : 1, /* children inherit it */ |
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pinned : 1, /* must always be on PMU */ |
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exclusive : 1, /* only group on PMU */ |
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exclude_user : 1, /* don't count user */ |
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exclude_kernel : 1, /* ditto kernel */ |
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exclude_hv : 1, /* ditto hypervisor */ |
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exclude_idle : 1, /* don't count when idle */ |
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mmap : 1, /* include mmap data */ |
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comm : 1, /* include comm data */ |
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freq : 1, /* use freq, not period */ |
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inherit_stat : 1, /* per task counts */ |
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enable_on_exec : 1, /* next exec enables */ |
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task : 1, /* trace fork/exit */ |
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watermark : 1, /* wakeup_watermark */ |
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/* |
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* precise_ip: |
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* |
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* 0 - SAMPLE_IP can have arbitrary skid |
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* 1 - SAMPLE_IP must have constant skid |
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* 2 - SAMPLE_IP requested to have 0 skid |
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* 3 - SAMPLE_IP must have 0 skid |
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* |
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* See also PERF_RECORD_MISC_EXACT_IP |
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*/ |
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precise_ip : 2, /* skid constraint */ |
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mmap_data : 1, /* non-exec mmap data */ |
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sample_id_all : 1, /* sample_type all events */ |
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exclude_host : 1, /* don't count in host */ |
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exclude_guest : 1, /* don't count in guest */ |
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exclude_callchain_kernel : 1, /* exclude kernel callchains */ |
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exclude_callchain_user : 1, /* exclude user callchains */ |
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mmap2 : 1, /* include mmap with inode data */ |
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comm_exec : 1, /* flag comm events that are due to an exec */ |
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use_clockid : 1, /* use @clockid for time fields */ |
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context_switch : 1, /* context switch data */ |
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write_backward : 1, /* Write ring buffer from end to beginning */ |
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namespaces : 1, /* include namespaces data */ |
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ksymbol : 1, /* include ksymbol events */ |
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bpf_event : 1, /* include bpf events */ |
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aux_output : 1, /* generate AUX records instead of events */ |
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cgroup : 1, /* include cgroup events */ |
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text_poke : 1, /* include text poke events */ |
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build_id : 1, /* use build id in mmap2 events */ |
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__reserved_1 : 29; |
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union { |
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__u32 wakeup_events; /* wakeup every n events */ |
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__u32 wakeup_watermark; /* bytes before wakeup */ |
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}; |
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__u32 bp_type; |
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union { |
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__u64 bp_addr; |
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__u64 kprobe_func; /* for perf_kprobe */ |
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__u64 uprobe_path; /* for perf_uprobe */ |
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__u64 config1; /* extension of config */ |
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}; |
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union { |
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__u64 bp_len; |
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__u64 kprobe_addr; /* when kprobe_func == NULL */ |
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__u64 probe_offset; /* for perf_[k,u]probe */ |
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__u64 config2; /* extension of config1 */ |
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}; |
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__u64 branch_sample_type; /* enum perf_branch_sample_type */ |
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|
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/* |
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* Defines set of user regs to dump on samples. |
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* See asm/perf_regs.h for details. |
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*/ |
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__u64 sample_regs_user; |
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|
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/* |
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* Defines size of the user stack to dump on samples. |
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*/ |
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__u32 sample_stack_user; |
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|
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__s32 clockid; |
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/* |
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* Defines set of regs to dump for each sample |
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* state captured on: |
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* - precise = 0: PMU interrupt |
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* - precise > 0: sampled instruction |
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* |
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* See asm/perf_regs.h for details. |
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*/ |
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__u64 sample_regs_intr; |
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|
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/* |
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* Wakeup watermark for AUX area |
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*/ |
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__u32 aux_watermark; |
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__u16 sample_max_stack; |
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__u16 __reserved_2; |
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__u32 aux_sample_size; |
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__u32 __reserved_3; |
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}; |
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|
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/* |
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* Structure used by below PERF_EVENT_IOC_QUERY_BPF command |
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* to query bpf programs attached to the same perf tracepoint |
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* as the given perf event. |
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*/ |
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struct perf_event_query_bpf { |
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/* |
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* The below ids array length |
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*/ |
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__u32 ids_len; |
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/* |
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* Set by the kernel to indicate the number of |
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* available programs |
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*/ |
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__u32 prog_cnt; |
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/* |
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* User provided buffer to store program ids |
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*/ |
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__u32 ids[0]; |
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}; |
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|
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/* |
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* Ioctls that can be done on a perf event fd: |
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*/ |
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#define PERF_EVENT_IOC_ENABLE _IO ('$', 0) |
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#define PERF_EVENT_IOC_DISABLE _IO ('$', 1) |
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#define PERF_EVENT_IOC_REFRESH _IO ('$', 2) |
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#define PERF_EVENT_IOC_RESET _IO ('$', 3) |
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#define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) |
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#define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) |
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#define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) |
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#define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) |
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#define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) |
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#define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) |
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#define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) |
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#define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) |
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|
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enum perf_event_ioc_flags { |
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PERF_IOC_FLAG_GROUP = 1U << 0, |
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}; |
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|
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/* |
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* Structure of the page that can be mapped via mmap |
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*/ |
|
struct perf_event_mmap_page { |
|
__u32 version; /* version number of this structure */ |
|
__u32 compat_version; /* lowest version this is compat with */ |
|
|
|
/* |
|
* Bits needed to read the hw events in user-space. |
|
* |
|
* u32 seq, time_mult, time_shift, index, width; |
|
* u64 count, enabled, running; |
|
* u64 cyc, time_offset; |
|
* s64 pmc = 0; |
|
* |
|
* do { |
|
* seq = pc->lock; |
|
* barrier() |
|
* |
|
* enabled = pc->time_enabled; |
|
* running = pc->time_running; |
|
* |
|
* if (pc->cap_usr_time && enabled != running) { |
|
* cyc = rdtsc(); |
|
* time_offset = pc->time_offset; |
|
* time_mult = pc->time_mult; |
|
* time_shift = pc->time_shift; |
|
* } |
|
* |
|
* index = pc->index; |
|
* count = pc->offset; |
|
* if (pc->cap_user_rdpmc && index) { |
|
* width = pc->pmc_width; |
|
* pmc = rdpmc(index - 1); |
|
* } |
|
* |
|
* barrier(); |
|
* } while (pc->lock != seq); |
|
* |
|
* NOTE: for obvious reason this only works on self-monitoring |
|
* processes. |
|
*/ |
|
__u32 lock; /* seqlock for synchronization */ |
|
__u32 index; /* hardware event identifier */ |
|
__s64 offset; /* add to hardware event value */ |
|
__u64 time_enabled; /* time event active */ |
|
__u64 time_running; /* time event on cpu */ |
|
union { |
|
__u64 capabilities; |
|
struct { |
|
__u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ |
|
cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ |
|
|
|
cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ |
|
cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ |
|
cap_user_time_zero : 1, /* The time_zero field is used */ |
|
cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ |
|
cap_____res : 58; |
|
}; |
|
}; |
|
|
|
/* |
|
* If cap_user_rdpmc this field provides the bit-width of the value |
|
* read using the rdpmc() or equivalent instruction. This can be used |
|
* to sign extend the result like: |
|
* |
|
* pmc <<= 64 - width; |
|
* pmc >>= 64 - width; // signed shift right |
|
* count += pmc; |
|
*/ |
|
__u16 pmc_width; |
|
|
|
/* |
|
* If cap_usr_time the below fields can be used to compute the time |
|
* delta since time_enabled (in ns) using rdtsc or similar. |
|
* |
|
* u64 quot, rem; |
|
* u64 delta; |
|
* |
|
* quot = (cyc >> time_shift); |
|
* rem = cyc & (((u64)1 << time_shift) - 1); |
|
* delta = time_offset + quot * time_mult + |
|
* ((rem * time_mult) >> time_shift); |
|
* |
|
* Where time_offset,time_mult,time_shift and cyc are read in the |
|
* seqcount loop described above. This delta can then be added to |
|
* enabled and possible running (if index), improving the scaling: |
|
* |
|
* enabled += delta; |
|
* if (index) |
|
* running += delta; |
|
* |
|
* quot = count / running; |
|
* rem = count % running; |
|
* count = quot * enabled + (rem * enabled) / running; |
|
*/ |
|
__u16 time_shift; |
|
__u32 time_mult; |
|
__u64 time_offset; |
|
/* |
|
* If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated |
|
* from sample timestamps. |
|
* |
|
* time = timestamp - time_zero; |
|
* quot = time / time_mult; |
|
* rem = time % time_mult; |
|
* cyc = (quot << time_shift) + (rem << time_shift) / time_mult; |
|
* |
|
* And vice versa: |
|
* |
|
* quot = cyc >> time_shift; |
|
* rem = cyc & (((u64)1 << time_shift) - 1); |
|
* timestamp = time_zero + quot * time_mult + |
|
* ((rem * time_mult) >> time_shift); |
|
*/ |
|
__u64 time_zero; |
|
|
|
__u32 size; /* Header size up to __reserved[] fields. */ |
|
__u32 __reserved_1; |
|
|
|
/* |
|
* If cap_usr_time_short, the hardware clock is less than 64bit wide |
|
* and we must compute the 'cyc' value, as used by cap_usr_time, as: |
|
* |
|
* cyc = time_cycles + ((cyc - time_cycles) & time_mask) |
|
* |
|
* NOTE: this form is explicitly chosen such that cap_usr_time_short |
|
* is a correction on top of cap_usr_time, and code that doesn't |
|
* know about cap_usr_time_short still works under the assumption |
|
* the counter doesn't wrap. |
|
*/ |
|
__u64 time_cycles; |
|
__u64 time_mask; |
|
|
|
/* |
|
* Hole for extension of the self monitor capabilities |
|
*/ |
|
|
|
__u8 __reserved[116*8]; /* align to 1k. */ |
|
|
|
/* |
|
* Control data for the mmap() data buffer. |
|
* |
|
* User-space reading the @data_head value should issue an smp_rmb(), |
|
* after reading this value. |
|
* |
|
* When the mapping is PROT_WRITE the @data_tail value should be |
|
* written by userspace to reflect the last read data, after issueing |
|
* an smp_mb() to separate the data read from the ->data_tail store. |
|
* In this case the kernel will not over-write unread data. |
|
* |
|
* See perf_output_put_handle() for the data ordering. |
|
* |
|
* data_{offset,size} indicate the location and size of the perf record |
|
* buffer within the mmapped area. |
|
*/ |
|
__u64 data_head; /* head in the data section */ |
|
__u64 data_tail; /* user-space written tail */ |
|
__u64 data_offset; /* where the buffer starts */ |
|
__u64 data_size; /* data buffer size */ |
|
|
|
/* |
|
* AUX area is defined by aux_{offset,size} fields that should be set |
|
* by the userspace, so that |
|
* |
|
* aux_offset >= data_offset + data_size |
|
* |
|
* prior to mmap()ing it. Size of the mmap()ed area should be aux_size. |
|
* |
|
* Ring buffer pointers aux_{head,tail} have the same semantics as |
|
* data_{head,tail} and same ordering rules apply. |
|
*/ |
|
__u64 aux_head; |
|
__u64 aux_tail; |
|
__u64 aux_offset; |
|
__u64 aux_size; |
|
}; |
|
|
|
/* |
|
* The current state of perf_event_header::misc bits usage: |
|
* ('|' used bit, '-' unused bit) |
|
* |
|
* 012 CDEF |
|
* |||---------|||| |
|
* |
|
* Where: |
|
* 0-2 CPUMODE_MASK |
|
* |
|
* C PROC_MAP_PARSE_TIMEOUT |
|
* D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT |
|
* E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT |
|
* F (reserved) |
|
*/ |
|
|
|
#define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) |
|
#define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) |
|
#define PERF_RECORD_MISC_KERNEL (1 << 0) |
|
#define PERF_RECORD_MISC_USER (2 << 0) |
|
#define PERF_RECORD_MISC_HYPERVISOR (3 << 0) |
|
#define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) |
|
#define PERF_RECORD_MISC_GUEST_USER (5 << 0) |
|
|
|
/* |
|
* Indicates that /proc/PID/maps parsing are truncated by time out. |
|
*/ |
|
#define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) |
|
/* |
|
* Following PERF_RECORD_MISC_* are used on different |
|
* events, so can reuse the same bit position: |
|
* |
|
* PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events |
|
* PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event |
|
* PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) |
|
* PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events |
|
*/ |
|
#define PERF_RECORD_MISC_MMAP_DATA (1 << 13) |
|
#define PERF_RECORD_MISC_COMM_EXEC (1 << 13) |
|
#define PERF_RECORD_MISC_FORK_EXEC (1 << 13) |
|
#define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) |
|
/* |
|
* These PERF_RECORD_MISC_* flags below are safely reused |
|
* for the following events: |
|
* |
|
* PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events |
|
* PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events |
|
* PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event |
|
* |
|
* |
|
* PERF_RECORD_MISC_EXACT_IP: |
|
* Indicates that the content of PERF_SAMPLE_IP points to |
|
* the actual instruction that triggered the event. See also |
|
* perf_event_attr::precise_ip. |
|
* |
|
* PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: |
|
* Indicates that thread was preempted in TASK_RUNNING state. |
|
* |
|
* PERF_RECORD_MISC_MMAP_BUILD_ID: |
|
* Indicates that mmap2 event carries build id data. |
|
*/ |
|
#define PERF_RECORD_MISC_EXACT_IP (1 << 14) |
|
#define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) |
|
#define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) |
|
/* |
|
* Reserve the last bit to indicate some extended misc field |
|
*/ |
|
#define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) |
|
|
|
struct perf_event_header { |
|
__u32 type; |
|
__u16 misc; |
|
__u16 size; |
|
}; |
|
|
|
struct perf_ns_link_info { |
|
__u64 dev; |
|
__u64 ino; |
|
}; |
|
|
|
enum { |
|
NET_NS_INDEX = 0, |
|
UTS_NS_INDEX = 1, |
|
IPC_NS_INDEX = 2, |
|
PID_NS_INDEX = 3, |
|
USER_NS_INDEX = 4, |
|
MNT_NS_INDEX = 5, |
|
CGROUP_NS_INDEX = 6, |
|
|
|
NR_NAMESPACES, /* number of available namespaces */ |
|
}; |
|
|
|
enum perf_event_type { |
|
|
|
/* |
|
* If perf_event_attr.sample_id_all is set then all event types will |
|
* have the sample_type selected fields related to where/when |
|
* (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, |
|
* IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed |
|
* just after the perf_event_header and the fields already present for |
|
* the existing fields, i.e. at the end of the payload. That way a newer |
|
* perf.data file will be supported by older perf tools, with these new |
|
* optional fields being ignored. |
|
* |
|
* struct sample_id { |
|
* { u32 pid, tid; } && PERF_SAMPLE_TID |
|
* { u64 time; } && PERF_SAMPLE_TIME |
|
* { u64 id; } && PERF_SAMPLE_ID |
|
* { u64 stream_id;} && PERF_SAMPLE_STREAM_ID |
|
* { u32 cpu, res; } && PERF_SAMPLE_CPU |
|
* { u64 id; } && PERF_SAMPLE_IDENTIFIER |
|
* } && perf_event_attr::sample_id_all |
|
* |
|
* Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The |
|
* advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed |
|
* relative to header.size. |
|
*/ |
|
|
|
/* |
|
* The MMAP events record the PROT_EXEC mappings so that we can |
|
* correlate userspace IPs to code. They have the following structure: |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* u32 pid, tid; |
|
* u64 addr; |
|
* u64 len; |
|
* u64 pgoff; |
|
* char filename[]; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_MMAP = 1, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u64 id; |
|
* u64 lost; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_LOST = 2, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* u32 pid, tid; |
|
* char comm[]; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_COMM = 3, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 pid, ppid; |
|
* u32 tid, ptid; |
|
* u64 time; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_EXIT = 4, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u64 time; |
|
* u64 id; |
|
* u64 stream_id; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_THROTTLE = 5, |
|
PERF_RECORD_UNTHROTTLE = 6, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 pid, ppid; |
|
* u32 tid, ptid; |
|
* u64 time; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_FORK = 7, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 pid, tid; |
|
* |
|
* struct read_format values; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_READ = 8, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* # |
|
* # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. |
|
* # The advantage of PERF_SAMPLE_IDENTIFIER is that its position |
|
* # is fixed relative to header. |
|
* # |
|
* |
|
* { u64 id; } && PERF_SAMPLE_IDENTIFIER |
|
* { u64 ip; } && PERF_SAMPLE_IP |
|
* { u32 pid, tid; } && PERF_SAMPLE_TID |
|
* { u64 time; } && PERF_SAMPLE_TIME |
|
* { u64 addr; } && PERF_SAMPLE_ADDR |
|
* { u64 id; } && PERF_SAMPLE_ID |
|
* { u64 stream_id;} && PERF_SAMPLE_STREAM_ID |
|
* { u32 cpu, res; } && PERF_SAMPLE_CPU |
|
* { u64 period; } && PERF_SAMPLE_PERIOD |
|
* |
|
* { struct read_format values; } && PERF_SAMPLE_READ |
|
* |
|
* { u64 nr, |
|
* u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN |
|
* |
|
* # |
|
* # The RAW record below is opaque data wrt the ABI |
|
* # |
|
* # That is, the ABI doesn't make any promises wrt to |
|
* # the stability of its content, it may vary depending |
|
* # on event, hardware, kernel version and phase of |
|
* # the moon. |
|
* # |
|
* # In other words, PERF_SAMPLE_RAW contents are not an ABI. |
|
* # |
|
* |
|
* { u32 size; |
|
* char data[size];}&& PERF_SAMPLE_RAW |
|
* |
|
* { u64 nr; |
|
* { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX |
|
* { u64 from, to, flags } lbr[nr]; |
|
* } && PERF_SAMPLE_BRANCH_STACK |
|
* |
|
* { u64 abi; # enum perf_sample_regs_abi |
|
* u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER |
|
* |
|
* { u64 size; |
|
* char data[size]; |
|
* u64 dyn_size; } && PERF_SAMPLE_STACK_USER |
|
* |
|
* { union perf_sample_weight |
|
* { |
|
* u64 full; && PERF_SAMPLE_WEIGHT |
|
* #if defined(__LITTLE_ENDIAN_BITFIELD) |
|
* struct { |
|
* u32 var1_dw; |
|
* u16 var2_w; |
|
* u16 var3_w; |
|
* } && PERF_SAMPLE_WEIGHT_STRUCT |
|
* #elif defined(__BIG_ENDIAN_BITFIELD) |
|
* struct { |
|
* u16 var3_w; |
|
* u16 var2_w; |
|
* u32 var1_dw; |
|
* } && PERF_SAMPLE_WEIGHT_STRUCT |
|
* #endif |
|
* } |
|
* } |
|
* { u64 data_src; } && PERF_SAMPLE_DATA_SRC |
|
* { u64 transaction; } && PERF_SAMPLE_TRANSACTION |
|
* { u64 abi; # enum perf_sample_regs_abi |
|
* u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR |
|
* { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR |
|
* { u64 size; |
|
* char data[size]; } && PERF_SAMPLE_AUX |
|
* { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE |
|
* { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE |
|
* }; |
|
*/ |
|
PERF_RECORD_SAMPLE = 9, |
|
|
|
/* |
|
* The MMAP2 records are an augmented version of MMAP, they add |
|
* maj, min, ino numbers to be used to uniquely identify each mapping |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* u32 pid, tid; |
|
* u64 addr; |
|
* u64 len; |
|
* u64 pgoff; |
|
* union { |
|
* struct { |
|
* u32 maj; |
|
* u32 min; |
|
* u64 ino; |
|
* u64 ino_generation; |
|
* }; |
|
* struct { |
|
* u8 build_id_size; |
|
* u8 __reserved_1; |
|
* u16 __reserved_2; |
|
* u8 build_id[20]; |
|
* }; |
|
* }; |
|
* u32 prot, flags; |
|
* char filename[]; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_MMAP2 = 10, |
|
|
|
/* |
|
* Records that new data landed in the AUX buffer part. |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* u64 aux_offset; |
|
* u64 aux_size; |
|
* u64 flags; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_AUX = 11, |
|
|
|
/* |
|
* Indicates that instruction trace has started |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 pid; |
|
* u32 tid; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_ITRACE_START = 12, |
|
|
|
/* |
|
* Records the dropped/lost sample number. |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* |
|
* u64 lost; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_LOST_SAMPLES = 13, |
|
|
|
/* |
|
* Records a context switch in or out (flagged by |
|
* PERF_RECORD_MISC_SWITCH_OUT). See also |
|
* PERF_RECORD_SWITCH_CPU_WIDE. |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_SWITCH = 14, |
|
|
|
/* |
|
* CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and |
|
* next_prev_tid that are the next (switching out) or previous |
|
* (switching in) pid/tid. |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 next_prev_pid; |
|
* u32 next_prev_tid; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_SWITCH_CPU_WIDE = 15, |
|
|
|
/* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u32 pid; |
|
* u32 tid; |
|
* u64 nr_namespaces; |
|
* { u64 dev, inode; } [nr_namespaces]; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_NAMESPACES = 16, |
|
|
|
/* |
|
* Record ksymbol register/unregister events: |
|
* |
|
* struct { |
|
* struct perf_event_header header; |
|
* u64 addr; |
|
* u32 len; |
|
* u16 ksym_type; |
|
* u16 flags; |
|
* char name[]; |
|
* struct sample_id sample_id; |
|
* }; |
|
*/ |
|
PERF_RECORD_KSYMBOL = 17, |
|
|
|
/* |
|
* Record bpf events: |
|
* enum perf_bpf_event_type { |
|
* PERF_BPF_EVENT_UNKNOWN = 0, |
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* PERF_BPF_EVENT_PROG_LOAD = 1, |
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* PERF_BPF_EVENT_PROG_UNLOAD = 2, |
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* }; |
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* |
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* struct { |
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* struct perf_event_header header; |
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* u16 type; |
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* u16 flags; |
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* u32 id; |
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* u8 tag[BPF_TAG_SIZE]; |
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* struct sample_id sample_id; |
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* }; |
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*/ |
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PERF_RECORD_BPF_EVENT = 18, |
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|
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/* |
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* struct { |
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* struct perf_event_header header; |
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* u64 id; |
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* char path[]; |
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* struct sample_id sample_id; |
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* }; |
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*/ |
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PERF_RECORD_CGROUP = 19, |
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|
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/* |
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* Records changes to kernel text i.e. self-modified code. 'old_len' is |
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* the number of old bytes, 'new_len' is the number of new bytes. Either |
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* 'old_len' or 'new_len' may be zero to indicate, for example, the |
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* addition or removal of a trampoline. 'bytes' contains the old bytes |
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* followed immediately by the new bytes. |
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* |
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* struct { |
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* struct perf_event_header header; |
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* u64 addr; |
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* u16 old_len; |
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* u16 new_len; |
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* u8 bytes[]; |
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* struct sample_id sample_id; |
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* }; |
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*/ |
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PERF_RECORD_TEXT_POKE = 20, |
|
|
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PERF_RECORD_MAX, /* non-ABI */ |
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}; |
|
|
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enum perf_record_ksymbol_type { |
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PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, |
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PERF_RECORD_KSYMBOL_TYPE_BPF = 1, |
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/* |
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* Out of line code such as kprobe-replaced instructions or optimized |
|
* kprobes or ftrace trampolines. |
|
*/ |
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PERF_RECORD_KSYMBOL_TYPE_OOL = 2, |
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PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ |
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}; |
|
|
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#define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) |
|
|
|
enum perf_bpf_event_type { |
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PERF_BPF_EVENT_UNKNOWN = 0, |
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PERF_BPF_EVENT_PROG_LOAD = 1, |
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PERF_BPF_EVENT_PROG_UNLOAD = 2, |
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PERF_BPF_EVENT_MAX, /* non-ABI */ |
|
}; |
|
|
|
#define PERF_MAX_STACK_DEPTH 127 |
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#define PERF_MAX_CONTEXTS_PER_STACK 8 |
|
|
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enum perf_callchain_context { |
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PERF_CONTEXT_HV = (__u64)-32, |
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PERF_CONTEXT_KERNEL = (__u64)-128, |
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PERF_CONTEXT_USER = (__u64)-512, |
|
|
|
PERF_CONTEXT_GUEST = (__u64)-2048, |
|
PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, |
|
PERF_CONTEXT_GUEST_USER = (__u64)-2560, |
|
|
|
PERF_CONTEXT_MAX = (__u64)-4095, |
|
}; |
|
|
|
/** |
|
* PERF_RECORD_AUX::flags bits |
|
*/ |
|
#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ |
|
#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ |
|
#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ |
|
#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ |
|
|
|
#define PERF_FLAG_FD_NO_GROUP (1UL << 0) |
|
#define PERF_FLAG_FD_OUTPUT (1UL << 1) |
|
#define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ |
|
#define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ |
|
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD) |
|
union perf_mem_data_src { |
|
__u64 val; |
|
struct { |
|
__u64 mem_op:5, /* type of opcode */ |
|
mem_lvl:14, /* memory hierarchy level */ |
|
mem_snoop:5, /* snoop mode */ |
|
mem_lock:2, /* lock instr */ |
|
mem_dtlb:7, /* tlb access */ |
|
mem_lvl_num:4, /* memory hierarchy level number */ |
|
mem_remote:1, /* remote */ |
|
mem_snoopx:2, /* snoop mode, ext */ |
|
mem_blk:3, /* access blocked */ |
|
mem_rsvd:21; |
|
}; |
|
}; |
|
#elif defined(__BIG_ENDIAN_BITFIELD) |
|
union perf_mem_data_src { |
|
__u64 val; |
|
struct { |
|
__u64 mem_rsvd:21, |
|
mem_blk:3, /* access blocked */ |
|
mem_snoopx:2, /* snoop mode, ext */ |
|
mem_remote:1, /* remote */ |
|
mem_lvl_num:4, /* memory hierarchy level number */ |
|
mem_dtlb:7, /* tlb access */ |
|
mem_lock:2, /* lock instr */ |
|
mem_snoop:5, /* snoop mode */ |
|
mem_lvl:14, /* memory hierarchy level */ |
|
mem_op:5; /* type of opcode */ |
|
}; |
|
}; |
|
#else |
|
#error "Unknown endianness" |
|
#endif |
|
|
|
/* type of opcode (load/store/prefetch,code) */ |
|
#define PERF_MEM_OP_NA 0x01 /* not available */ |
|
#define PERF_MEM_OP_LOAD 0x02 /* load instruction */ |
|
#define PERF_MEM_OP_STORE 0x04 /* store instruction */ |
|
#define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ |
|
#define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ |
|
#define PERF_MEM_OP_SHIFT 0 |
|
|
|
/* memory hierarchy (memory level, hit or miss) */ |
|
#define PERF_MEM_LVL_NA 0x01 /* not available */ |
|
#define PERF_MEM_LVL_HIT 0x02 /* hit level */ |
|
#define PERF_MEM_LVL_MISS 0x04 /* miss level */ |
|
#define PERF_MEM_LVL_L1 0x08 /* L1 */ |
|
#define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ |
|
#define PERF_MEM_LVL_L2 0x20 /* L2 */ |
|
#define PERF_MEM_LVL_L3 0x40 /* L3 */ |
|
#define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ |
|
#define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ |
|
#define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ |
|
#define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ |
|
#define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ |
|
#define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ |
|
#define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ |
|
#define PERF_MEM_LVL_SHIFT 5 |
|
|
|
#define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ |
|
#define PERF_MEM_REMOTE_SHIFT 37 |
|
|
|
#define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ |
|
#define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ |
|
#define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ |
|
#define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ |
|
/* 5-0xa available */ |
|
#define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ |
|
#define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ |
|
#define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ |
|
#define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ |
|
#define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ |
|
|
|
#define PERF_MEM_LVLNUM_SHIFT 33 |
|
|
|
/* snoop mode */ |
|
#define PERF_MEM_SNOOP_NA 0x01 /* not available */ |
|
#define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ |
|
#define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ |
|
#define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ |
|
#define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ |
|
#define PERF_MEM_SNOOP_SHIFT 19 |
|
|
|
#define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ |
|
/* 1 free */ |
|
#define PERF_MEM_SNOOPX_SHIFT 38 |
|
|
|
/* locked instruction */ |
|
#define PERF_MEM_LOCK_NA 0x01 /* not available */ |
|
#define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ |
|
#define PERF_MEM_LOCK_SHIFT 24 |
|
|
|
/* TLB access */ |
|
#define PERF_MEM_TLB_NA 0x01 /* not available */ |
|
#define PERF_MEM_TLB_HIT 0x02 /* hit level */ |
|
#define PERF_MEM_TLB_MISS 0x04 /* miss level */ |
|
#define PERF_MEM_TLB_L1 0x08 /* L1 */ |
|
#define PERF_MEM_TLB_L2 0x10 /* L2 */ |
|
#define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ |
|
#define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ |
|
#define PERF_MEM_TLB_SHIFT 26 |
|
|
|
/* Access blocked */ |
|
#define PERF_MEM_BLK_NA 0x01 /* not available */ |
|
#define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ |
|
#define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ |
|
#define PERF_MEM_BLK_SHIFT 40 |
|
|
|
#define PERF_MEM_S(a, s) \ |
|
(((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) |
|
|
|
/* |
|
* single taken branch record layout: |
|
* |
|
* from: source instruction (may not always be a branch insn) |
|
* to: branch target |
|
* mispred: branch target was mispredicted |
|
* predicted: branch target was predicted |
|
* |
|
* support for mispred, predicted is optional. In case it |
|
* is not supported mispred = predicted = 0. |
|
* |
|
* in_tx: running in a hardware transaction |
|
* abort: aborting a hardware transaction |
|
* cycles: cycles from last branch (or 0 if not supported) |
|
* type: branch type |
|
*/ |
|
struct perf_branch_entry { |
|
__u64 from; |
|
__u64 to; |
|
__u64 mispred:1, /* target mispredicted */ |
|
predicted:1,/* target predicted */ |
|
in_tx:1, /* in transaction */ |
|
abort:1, /* transaction abort */ |
|
cycles:16, /* cycle count to last branch */ |
|
type:4, /* branch type */ |
|
reserved:40; |
|
}; |
|
|
|
union perf_sample_weight { |
|
__u64 full; |
|
#if defined(__LITTLE_ENDIAN_BITFIELD) |
|
struct { |
|
__u32 var1_dw; |
|
__u16 var2_w; |
|
__u16 var3_w; |
|
}; |
|
#elif defined(__BIG_ENDIAN_BITFIELD) |
|
struct { |
|
__u16 var3_w; |
|
__u16 var2_w; |
|
__u32 var1_dw; |
|
}; |
|
#else |
|
#error "Unknown endianness" |
|
#endif |
|
}; |
|
|
|
#endif /* _UAPI_LINUX_PERF_EVENT_H */
|
|
|