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341 lines
12 KiB
341 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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/* |
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* IOMMU user API definitions |
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*/ |
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#ifndef _UAPI_IOMMU_H |
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#define _UAPI_IOMMU_H |
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#include <linux/types.h> |
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#define IOMMU_FAULT_PERM_READ (1 << 0) /* read */ |
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#define IOMMU_FAULT_PERM_WRITE (1 << 1) /* write */ |
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#define IOMMU_FAULT_PERM_EXEC (1 << 2) /* exec */ |
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#define IOMMU_FAULT_PERM_PRIV (1 << 3) /* privileged */ |
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/* Generic fault types, can be expanded IRQ remapping fault */ |
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enum iommu_fault_type { |
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IOMMU_FAULT_DMA_UNRECOV = 1, /* unrecoverable fault */ |
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IOMMU_FAULT_PAGE_REQ, /* page request fault */ |
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}; |
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enum iommu_fault_reason { |
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IOMMU_FAULT_REASON_UNKNOWN = 0, |
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/* Could not access the PASID table (fetch caused external abort) */ |
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IOMMU_FAULT_REASON_PASID_FETCH, |
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/* PASID entry is invalid or has configuration errors */ |
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IOMMU_FAULT_REASON_BAD_PASID_ENTRY, |
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/* |
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* PASID is out of range (e.g. exceeds the maximum PASID |
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* supported by the IOMMU) or disabled. |
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*/ |
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IOMMU_FAULT_REASON_PASID_INVALID, |
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/* |
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* An external abort occurred fetching (or updating) a translation |
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* table descriptor |
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*/ |
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IOMMU_FAULT_REASON_WALK_EABT, |
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/* |
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* Could not access the page table entry (Bad address), |
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* actual translation fault |
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*/ |
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IOMMU_FAULT_REASON_PTE_FETCH, |
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/* Protection flag check failed */ |
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IOMMU_FAULT_REASON_PERMISSION, |
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/* access flag check failed */ |
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IOMMU_FAULT_REASON_ACCESS, |
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/* Output address of a translation stage caused Address Size fault */ |
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IOMMU_FAULT_REASON_OOR_ADDRESS, |
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}; |
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/** |
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* struct iommu_fault_unrecoverable - Unrecoverable fault data |
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* @reason: reason of the fault, from &enum iommu_fault_reason |
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* @flags: parameters of this fault (IOMMU_FAULT_UNRECOV_* values) |
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* @pasid: Process Address Space ID |
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* @perm: requested permission access using by the incoming transaction |
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* (IOMMU_FAULT_PERM_* values) |
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* @addr: offending page address |
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* @fetch_addr: address that caused a fetch abort, if any |
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*/ |
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struct iommu_fault_unrecoverable { |
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__u32 reason; |
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#define IOMMU_FAULT_UNRECOV_PASID_VALID (1 << 0) |
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#define IOMMU_FAULT_UNRECOV_ADDR_VALID (1 << 1) |
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#define IOMMU_FAULT_UNRECOV_FETCH_ADDR_VALID (1 << 2) |
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__u32 flags; |
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__u32 pasid; |
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__u32 perm; |
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__u64 addr; |
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__u64 fetch_addr; |
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}; |
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/** |
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* struct iommu_fault_page_request - Page Request data |
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* @flags: encodes whether the corresponding fields are valid and whether this |
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* is the last page in group (IOMMU_FAULT_PAGE_REQUEST_* values). |
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* When IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID is set, the page response |
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* must have the same PASID value as the page request. When it is clear, |
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* the page response should not have a PASID. |
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* @pasid: Process Address Space ID |
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* @grpid: Page Request Group Index |
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* @perm: requested page permissions (IOMMU_FAULT_PERM_* values) |
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* @addr: page address |
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* @private_data: device-specific private information |
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*/ |
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struct iommu_fault_page_request { |
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#define IOMMU_FAULT_PAGE_REQUEST_PASID_VALID (1 << 0) |
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#define IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE (1 << 1) |
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#define IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA (1 << 2) |
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#define IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID (1 << 3) |
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__u32 flags; |
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__u32 pasid; |
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__u32 grpid; |
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__u32 perm; |
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__u64 addr; |
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__u64 private_data[2]; |
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}; |
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/** |
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* struct iommu_fault - Generic fault data |
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* @type: fault type from &enum iommu_fault_type |
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* @padding: reserved for future use (should be zero) |
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* @event: fault event, when @type is %IOMMU_FAULT_DMA_UNRECOV |
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* @prm: Page Request message, when @type is %IOMMU_FAULT_PAGE_REQ |
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* @padding2: sets the fault size to allow for future extensions |
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*/ |
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struct iommu_fault { |
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__u32 type; |
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__u32 padding; |
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union { |
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struct iommu_fault_unrecoverable event; |
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struct iommu_fault_page_request prm; |
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__u8 padding2[56]; |
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}; |
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}; |
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/** |
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* enum iommu_page_response_code - Return status of fault handlers |
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* @IOMMU_PAGE_RESP_SUCCESS: Fault has been handled and the page tables |
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* populated, retry the access. This is "Success" in PCI PRI. |
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* @IOMMU_PAGE_RESP_FAILURE: General error. Drop all subsequent faults from |
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* this device if possible. This is "Response Failure" in PCI PRI. |
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* @IOMMU_PAGE_RESP_INVALID: Could not handle this fault, don't retry the |
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* access. This is "Invalid Request" in PCI PRI. |
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*/ |
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enum iommu_page_response_code { |
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IOMMU_PAGE_RESP_SUCCESS = 0, |
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IOMMU_PAGE_RESP_INVALID, |
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IOMMU_PAGE_RESP_FAILURE, |
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}; |
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/** |
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* struct iommu_page_response - Generic page response information |
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* @argsz: User filled size of this data |
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* @version: API version of this structure |
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* @flags: encodes whether the corresponding fields are valid |
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* (IOMMU_FAULT_PAGE_RESPONSE_* values) |
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* @pasid: Process Address Space ID |
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* @grpid: Page Request Group Index |
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* @code: response code from &enum iommu_page_response_code |
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*/ |
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struct iommu_page_response { |
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__u32 argsz; |
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#define IOMMU_PAGE_RESP_VERSION_1 1 |
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__u32 version; |
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#define IOMMU_PAGE_RESP_PASID_VALID (1 << 0) |
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__u32 flags; |
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__u32 pasid; |
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__u32 grpid; |
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__u32 code; |
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}; |
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/* defines the granularity of the invalidation */ |
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enum iommu_inv_granularity { |
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IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ |
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IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */ |
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IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ |
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IOMMU_INV_GRANU_NR, /* number of invalidation granularities */ |
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}; |
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/** |
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* struct iommu_inv_addr_info - Address Selective Invalidation Structure |
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* |
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* @flags: indicates the granularity of the address-selective invalidation |
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* - If the PASID bit is set, the @pasid field is populated and the invalidation |
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* relates to cache entries tagged with this PASID and matching the address |
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* range. |
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* - If ARCHID bit is set, @archid is populated and the invalidation relates |
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* to cache entries tagged with this architecture specific ID and matching |
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* the address range. |
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* - Both PASID and ARCHID can be set as they may tag different caches. |
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* - If neither PASID or ARCHID is set, global addr invalidation applies. |
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* - The LEAF flag indicates whether only the leaf PTE caching needs to be |
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* invalidated and other paging structure caches can be preserved. |
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* @pasid: process address space ID |
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* @archid: architecture-specific ID |
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* @addr: first stage/level input address |
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* @granule_size: page/block size of the mapping in bytes |
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* @nb_granules: number of contiguous granules to be invalidated |
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*/ |
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struct iommu_inv_addr_info { |
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#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) |
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#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) |
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#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) |
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__u32 flags; |
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__u32 archid; |
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__u64 pasid; |
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__u64 addr; |
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__u64 granule_size; |
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__u64 nb_granules; |
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}; |
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/** |
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* struct iommu_inv_pasid_info - PASID Selective Invalidation Structure |
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* |
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* @flags: indicates the granularity of the PASID-selective invalidation |
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* - If the PASID bit is set, the @pasid field is populated and the invalidation |
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* relates to cache entries tagged with this PASID and matching the address |
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* range. |
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* - If the ARCHID bit is set, the @archid is populated and the invalidation |
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* relates to cache entries tagged with this architecture specific ID and |
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* matching the address range. |
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* - Both PASID and ARCHID can be set as they may tag different caches. |
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* - At least one of PASID or ARCHID must be set. |
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* @pasid: process address space ID |
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* @archid: architecture-specific ID |
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*/ |
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struct iommu_inv_pasid_info { |
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#define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) |
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#define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) |
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__u32 flags; |
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__u32 archid; |
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__u64 pasid; |
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}; |
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/** |
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* struct iommu_cache_invalidate_info - First level/stage invalidation |
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* information |
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* @argsz: User filled size of this data |
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* @version: API version of this structure |
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* @cache: bitfield that allows to select which caches to invalidate |
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* @granularity: defines the lowest granularity used for the invalidation: |
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* domain > PASID > addr |
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* @padding: reserved for future use (should be zero) |
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* @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID |
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* @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR |
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* |
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* Not all the combinations of cache/granularity are valid: |
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* |
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* +--------------+---------------+---------------+---------------+ |
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* | type / | DEV_IOTLB | IOTLB | PASID | |
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* | granularity | | | cache | |
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* +==============+===============+===============+===============+ |
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* | DOMAIN | N/A | Y | Y | |
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* +--------------+---------------+---------------+---------------+ |
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* | PASID | Y | Y | Y | |
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* +--------------+---------------+---------------+---------------+ |
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* | ADDR | Y | Y | N/A | |
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* +--------------+---------------+---------------+---------------+ |
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* |
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* Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than |
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* @version and @cache. |
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* |
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* If multiple cache types are invalidated simultaneously, they all |
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* must support the used granularity. |
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*/ |
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struct iommu_cache_invalidate_info { |
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__u32 argsz; |
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#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 |
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__u32 version; |
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/* IOMMU paging structure cache */ |
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#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ |
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#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ |
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#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ |
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#define IOMMU_CACHE_INV_TYPE_NR (3) |
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__u8 cache; |
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__u8 granularity; |
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__u8 padding[6]; |
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union { |
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struct iommu_inv_pasid_info pasid_info; |
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struct iommu_inv_addr_info addr_info; |
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} granu; |
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}; |
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/** |
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* struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest |
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* SVA binding. |
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* |
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* @flags: VT-d PASID table entry attributes |
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* @pat: Page attribute table data to compute effective memory type |
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* @emt: Extended memory type |
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* |
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* Only guest vIOMMU selectable and effective options are passed down to |
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* the host IOMMU. |
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*/ |
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struct iommu_gpasid_bind_data_vtd { |
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#define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */ |
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#define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */ |
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#define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */ |
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#define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */ |
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#define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */ |
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#define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */ |
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#define IOMMU_SVA_VTD_GPASID_LAST (1 << 6) |
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__u64 flags; |
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__u32 pat; |
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__u32 emt; |
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}; |
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#define IOMMU_SVA_VTD_GPASID_MTS_MASK (IOMMU_SVA_VTD_GPASID_CD | \ |
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IOMMU_SVA_VTD_GPASID_EMTE | \ |
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IOMMU_SVA_VTD_GPASID_PCD | \ |
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IOMMU_SVA_VTD_GPASID_PWT) |
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/** |
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* struct iommu_gpasid_bind_data - Information about device and guest PASID binding |
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* @argsz: User filled size of this data |
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* @version: Version of this data structure |
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* @format: PASID table entry format |
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* @flags: Additional information on guest bind request |
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* @gpgd: Guest page directory base of the guest mm to bind |
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* @hpasid: Process address space ID used for the guest mm in host IOMMU |
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* @gpasid: Process address space ID used for the guest mm in guest IOMMU |
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* @addr_width: Guest virtual address width |
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* @padding: Reserved for future use (should be zero) |
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* @vtd: Intel VT-d specific data |
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* |
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* Guest to host PASID mapping can be an identity or non-identity, where guest |
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* has its own PASID space. For non-identify mapping, guest to host PASID lookup |
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* is needed when VM programs guest PASID into an assigned device. VMM may |
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* trap such PASID programming then request host IOMMU driver to convert guest |
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* PASID to host PASID based on this bind data. |
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*/ |
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struct iommu_gpasid_bind_data { |
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__u32 argsz; |
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#define IOMMU_GPASID_BIND_VERSION_1 1 |
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__u32 version; |
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#define IOMMU_PASID_FORMAT_INTEL_VTD 1 |
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#define IOMMU_PASID_FORMAT_LAST 2 |
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__u32 format; |
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__u32 addr_width; |
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#define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */ |
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__u64 flags; |
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__u64 gpgd; |
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__u64 hpasid; |
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__u64 gpasid; |
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__u8 padding[8]; |
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/* Vendor specific data */ |
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union { |
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struct iommu_gpasid_bind_data_vtd vtd; |
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} vendor; |
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}; |
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#endif /* _UAPI_IOMMU_H */
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