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49 lines
1.0 KiB
49 lines
1.0 KiB
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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/* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* Copyright(c) 2018 Intel Corporation. All rights reserved. |
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*/ |
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#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__ |
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#define __INCLUDE_SOUND_SOF_XTENSA_H__ |
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#include <sound/sof/header.h> |
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/* |
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* Architecture specific debug |
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*/ |
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/* Xtensa Firmware Oops data */ |
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struct sof_ipc_dsp_oops_xtensa { |
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struct sof_ipc_dsp_oops_arch_hdr arch_hdr; |
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struct sof_ipc_dsp_oops_plat_hdr plat_hdr; |
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uint32_t exccause; |
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uint32_t excvaddr; |
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uint32_t ps; |
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uint32_t epc1; |
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uint32_t epc2; |
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uint32_t epc3; |
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uint32_t epc4; |
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uint32_t epc5; |
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uint32_t epc6; |
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uint32_t epc7; |
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uint32_t eps2; |
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uint32_t eps3; |
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uint32_t eps4; |
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uint32_t eps5; |
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uint32_t eps6; |
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uint32_t eps7; |
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uint32_t depc; |
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uint32_t intenable; |
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uint32_t interrupt; |
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uint32_t sar; |
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uint32_t debugcause; |
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uint32_t windowbase; |
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uint32_t windowstart; |
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uint32_t excsave1; |
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uint32_t ar[]; |
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} __packed; |
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#endif
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