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41 lines
1.4 KiB
41 lines
1.4 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
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* Digitizer with Horizontal PLL registers |
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* |
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* Copyright (C) 2009 Texas Instruments Inc |
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* Author: Santiago Nunez-Corrales <[email protected]> |
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* |
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* This code is partially based upon the TVP5150 driver |
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* written by Mauro Carvalho Chehab <[email protected]>, |
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* the TVP514x driver written by Vaibhav Hiremath <[email protected]> |
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* and the TVP7002 driver in the TI LSP 2.10.00.14 |
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*/ |
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#ifndef _TVP7002_H_ |
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#define _TVP7002_H_ |
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#define TVP7002_MODULE_NAME "tvp7002" |
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/** |
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* struct tvp7002_config - Platform dependent data |
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*@clk_polarity: Clock polarity |
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* 0 - Data clocked out on rising edge of DATACLK signal |
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* 1 - Data clocked out on falling edge of DATACLK signal |
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*@hs_polarity: HSYNC polarity |
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* 0 - Active low HSYNC output, 1 - Active high HSYNC output |
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*@vs_polarity: VSYNC Polarity |
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* 0 - Active low VSYNC output, 1 - Active high VSYNC output |
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*@fid_polarity: Active-high Field ID polarity. |
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* 0 - The field ID output is set to logic 1 for an odd field |
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* (field 1) and set to logic 0 for an even field (field 0). |
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* 1 - Operation with polarity inverted. |
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*@sog_polarity: Active high Sync on Green output polarity. |
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* 0 - Normal operation, 1 - Operation with polarity inverted |
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*/ |
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struct tvp7002_config { |
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bool clk_polarity; |
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bool hs_polarity; |
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bool vs_polarity; |
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bool fid_polarity; |
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bool sog_polarity; |
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}; |
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#endif
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