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47 lines
1.6 KiB
47 lines
1.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* board initialization code should put one of these into dev->platform_data |
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* and place the isp1362 onto platform_bus. |
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*/ |
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#ifndef __LINUX_USB_ISP1362_H__ |
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#define __LINUX_USB_ISP1362_H__ |
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struct isp1362_platform_data { |
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/* Enable internal pulldown resistors on downstream ports */ |
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unsigned sel15Kres:1; |
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/* Clock cannot be stopped */ |
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unsigned clknotstop:1; |
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/* On-chip overcurrent protection */ |
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unsigned oc_enable:1; |
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/* INT output polarity */ |
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unsigned int_act_high:1; |
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/* INT edge or level triggered */ |
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unsigned int_edge_triggered:1; |
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/* DREQ output polarity */ |
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unsigned dreq_act_high:1; |
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/* DACK input polarity */ |
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unsigned dack_act_high:1; |
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/* chip can be resumed via H_WAKEUP pin */ |
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unsigned remote_wakeup_connected:1; |
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/* Switch or not to switch (keep always powered) */ |
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unsigned no_power_switching:1; |
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/* Ganged port power switching (0) or individual port power switching (1) */ |
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unsigned power_switching_mode:1; |
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/* Given port_power, msec/2 after power on till power good */ |
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u8 potpg; |
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/* Hardware reset set/clear */ |
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void (*reset) (struct device *dev, int set); |
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/* Clock start/stop */ |
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void (*clock) (struct device *dev, int start); |
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/* Inter-io delay (ns). The chip is picky about access timings; it |
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* expects at least: |
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* 110ns delay between consecutive accesses to DATA_REG, |
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* 300ns delay between access to ADDR_REG and DATA_REG (registers) |
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* 462ns delay between access to ADDR_REG and DATA_REG (buffer memory) |
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* WE MUST NOT be activated during these intervals (even without CS!) |
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*/ |
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void (*delay) (struct device *dev, unsigned int delay); |
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}; |
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#endif
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