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207 lines
5.3 KiB
207 lines
5.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/******************************************************************************* |
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Header file for stmmac platform data |
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Copyright (C) 2009 STMicroelectronics Ltd |
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Author: Giuseppe Cavallaro <[email protected]> |
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*******************************************************************************/ |
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#ifndef __STMMAC_PLATFORM_DATA |
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#define __STMMAC_PLATFORM_DATA |
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#include <linux/platform_device.h> |
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#include <linux/phy.h> |
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#define MTL_MAX_RX_QUEUES 8 |
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#define MTL_MAX_TX_QUEUES 8 |
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#define STMMAC_CH_MAX 8 |
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#define STMMAC_RX_COE_NONE 0 |
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#define STMMAC_RX_COE_TYPE1 1 |
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#define STMMAC_RX_COE_TYPE2 2 |
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/* Define the macros for CSR clock range parameters to be passed by |
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* platform code. |
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* This could also be configured at run time using CPU freq framework. */ |
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/* MDC Clock Selection define*/ |
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#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ |
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#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ |
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#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ |
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#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ |
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#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ |
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#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ |
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/* MTL algorithms identifiers */ |
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#define MTL_TX_ALGORITHM_WRR 0x0 |
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#define MTL_TX_ALGORITHM_WFQ 0x1 |
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#define MTL_TX_ALGORITHM_DWRR 0x2 |
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#define MTL_TX_ALGORITHM_SP 0x3 |
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#define MTL_RX_ALGORITHM_SP 0x4 |
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#define MTL_RX_ALGORITHM_WSP 0x5 |
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/* RX/TX Queue Mode */ |
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#define MTL_QUEUE_AVB 0x0 |
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#define MTL_QUEUE_DCB 0x1 |
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/* The MDC clock could be set higher than the IEEE 802.3 |
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* specified frequency limit 0f 2.5 MHz, by programming a clock divider |
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* of value different than the above defined values. The resultant MDIO |
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* clock frequency of 12.5 MHz is applicable for the interfacing chips |
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* supporting higher MDC clocks. |
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* The MDC clock selection macros need to be defined for MDC clock rate |
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* of 12.5 MHz, corresponding to the following selection. |
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*/ |
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#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ |
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#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ |
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#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ |
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#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ |
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#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ |
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#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ |
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#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ |
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#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ |
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/* AXI DMA Burst length supported */ |
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#define DMA_AXI_BLEN_4 (1 << 1) |
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#define DMA_AXI_BLEN_8 (1 << 2) |
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#define DMA_AXI_BLEN_16 (1 << 3) |
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#define DMA_AXI_BLEN_32 (1 << 4) |
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#define DMA_AXI_BLEN_64 (1 << 5) |
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#define DMA_AXI_BLEN_128 (1 << 6) |
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#define DMA_AXI_BLEN_256 (1 << 7) |
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#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ |
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| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ |
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| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) |
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/* Platfrom data for platform device structure's platform_data field */ |
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struct stmmac_mdio_bus_data { |
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unsigned int phy_mask; |
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unsigned int has_xpcs; |
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int *irqs; |
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int probed_phy_irq; |
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bool needs_reset; |
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}; |
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struct stmmac_dma_cfg { |
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int pbl; |
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int txpbl; |
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int rxpbl; |
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bool pblx8; |
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int fixed_burst; |
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int mixed_burst; |
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bool aal; |
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bool eame; |
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}; |
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#define AXI_BLEN 7 |
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struct stmmac_axi { |
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bool axi_lpi_en; |
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bool axi_xit_frm; |
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u32 axi_wr_osr_lmt; |
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u32 axi_rd_osr_lmt; |
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bool axi_kbbe; |
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u32 axi_blen[AXI_BLEN]; |
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bool axi_fb; |
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bool axi_mb; |
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bool axi_rb; |
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}; |
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#define EST_GCL 1024 |
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struct stmmac_est { |
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int enable; |
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u32 btr_offset[2]; |
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u32 btr[2]; |
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u32 ctr[2]; |
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u32 ter; |
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u32 gcl_unaligned[EST_GCL]; |
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u32 gcl[EST_GCL]; |
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u32 gcl_size; |
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}; |
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struct stmmac_rxq_cfg { |
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u8 mode_to_use; |
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u32 chan; |
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u8 pkt_route; |
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bool use_prio; |
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u32 prio; |
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}; |
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struct stmmac_txq_cfg { |
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u32 weight; |
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u8 mode_to_use; |
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/* Credit Base Shaper parameters */ |
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u32 send_slope; |
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u32 idle_slope; |
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u32 high_credit; |
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u32 low_credit; |
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bool use_prio; |
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u32 prio; |
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int tbs_en; |
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}; |
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struct plat_stmmacenet_data { |
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int bus_id; |
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int phy_addr; |
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int interface; |
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phy_interface_t phy_interface; |
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struct stmmac_mdio_bus_data *mdio_bus_data; |
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struct device_node *phy_node; |
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struct device_node *phylink_node; |
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struct device_node *mdio_node; |
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struct stmmac_dma_cfg *dma_cfg; |
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struct stmmac_est *est; |
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int clk_csr; |
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int has_gmac; |
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int enh_desc; |
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int tx_coe; |
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int rx_coe; |
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int bugged_jumbo; |
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int pmt; |
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int force_sf_dma_mode; |
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int force_thresh_dma_mode; |
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int riwt_off; |
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int max_speed; |
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int maxmtu; |
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int multicast_filter_bins; |
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int unicast_filter_entries; |
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int tx_fifo_size; |
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int rx_fifo_size; |
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u32 addr64; |
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u32 rx_queues_to_use; |
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u32 tx_queues_to_use; |
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u8 rx_sched_algorithm; |
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u8 tx_sched_algorithm; |
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struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; |
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struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; |
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void (*fix_mac_speed)(void *priv, unsigned int speed); |
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int (*serdes_powerup)(struct net_device *ndev, void *priv); |
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void (*serdes_powerdown)(struct net_device *ndev, void *priv); |
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int (*init)(struct platform_device *pdev, void *priv); |
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void (*exit)(struct platform_device *pdev, void *priv); |
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struct mac_device_info *(*setup)(void *priv); |
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void *bsp_priv; |
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struct clk *stmmac_clk; |
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struct clk *pclk; |
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struct clk *clk_ptp_ref; |
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unsigned int clk_ptp_rate; |
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unsigned int clk_ref_rate; |
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s32 ptp_max_adj; |
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struct reset_control *stmmac_rst; |
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struct stmmac_axi *axi; |
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int has_gmac4; |
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bool has_sun8i; |
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bool tso_en; |
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int rss_en; |
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int mac_port_sel_speed; |
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bool en_tx_lpi_clockgating; |
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int has_xgmac; |
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bool vlan_fail_q_en; |
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u8 vlan_fail_q; |
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unsigned int eee_usecs_rate; |
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struct pci_dev *pdev; |
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}; |
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#endif
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