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682 lines
20 KiB
682 lines
20 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef LINUX_SSB_H_ |
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#define LINUX_SSB_H_ |
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#include <linux/device.h> |
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#include <linux/list.h> |
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#include <linux/types.h> |
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#include <linux/spinlock.h> |
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#include <linux/pci.h> |
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#include <linux/gpio.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/platform_device.h> |
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#include <linux/ssb/ssb_regs.h> |
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struct pcmcia_device; |
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struct ssb_bus; |
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struct ssb_driver; |
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struct ssb_sprom_core_pwr_info { |
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u8 itssi_2g, itssi_5g; |
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u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; |
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u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; |
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}; |
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struct ssb_sprom { |
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u8 revision; |
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u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ |
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u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ |
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u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ |
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u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */ |
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u8 et0phyaddr; /* MII address for enet0 */ |
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u8 et1phyaddr; /* MII address for enet1 */ |
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u8 et2phyaddr; /* MII address for enet2 */ |
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u8 et0mdcport; /* MDIO for enet0 */ |
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u8 et1mdcport; /* MDIO for enet1 */ |
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u8 et2mdcport; /* MDIO for enet2 */ |
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u16 dev_id; /* Device ID overriding e.g. PCI ID */ |
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u16 board_rev; /* Board revision number from SPROM. */ |
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u16 board_num; /* Board number from SPROM. */ |
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u16 board_type; /* Board type from SPROM. */ |
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u8 country_code; /* Country Code */ |
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char alpha2[2]; /* Country Code as two chars like EU or US */ |
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u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ |
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u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ |
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u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ |
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u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ |
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u16 pa0b0; |
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u16 pa0b1; |
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u16 pa0b2; |
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u16 pa1b0; |
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u16 pa1b1; |
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u16 pa1b2; |
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u16 pa1lob0; |
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u16 pa1lob1; |
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u16 pa1lob2; |
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u16 pa1hib0; |
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u16 pa1hib1; |
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u16 pa1hib2; |
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u8 gpio0; /* GPIO pin 0 */ |
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u8 gpio1; /* GPIO pin 1 */ |
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u8 gpio2; /* GPIO pin 2 */ |
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u8 gpio3; /* GPIO pin 3 */ |
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u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ |
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u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ |
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u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ |
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u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ |
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u8 itssi_a; /* Idle TSSI Target for A-PHY */ |
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u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ |
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u8 tri2g; /* 2.4GHz TX isolation */ |
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u8 tri5gl; /* 5.2GHz TX isolation */ |
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u8 tri5g; /* 5.3GHz TX isolation */ |
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u8 tri5gh; /* 5.8GHz TX isolation */ |
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u8 txpid2g[4]; /* 2GHz TX power index */ |
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u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ |
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u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ |
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u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ |
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s8 rxpo2g; /* 2GHz RX power offset */ |
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s8 rxpo5g; /* 5GHz RX power offset */ |
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u8 rssisav2g; /* 2GHz RSSI params */ |
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u8 rssismc2g; |
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u8 rssismf2g; |
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u8 bxa2g; /* 2GHz BX arch */ |
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u8 rssisav5g; /* 5GHz RSSI params */ |
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u8 rssismc5g; |
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u8 rssismf5g; |
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u8 bxa5g; /* 5GHz BX arch */ |
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u16 cck2gpo; /* CCK power offset */ |
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u32 ofdm2gpo; /* 2.4GHz OFDM power offset */ |
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u32 ofdm5glpo; /* 5.2GHz OFDM power offset */ |
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u32 ofdm5gpo; /* 5.3GHz OFDM power offset */ |
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u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */ |
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u32 boardflags; |
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u32 boardflags2; |
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u32 boardflags3; |
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/* TODO: Switch all drivers to new u32 fields and drop below ones */ |
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u16 boardflags_lo; /* Board flags (bits 0-15) */ |
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u16 boardflags_hi; /* Board flags (bits 16-31) */ |
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u16 boardflags2_lo; /* Board flags (bits 32-47) */ |
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u16 boardflags2_hi; /* Board flags (bits 48-63) */ |
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struct ssb_sprom_core_pwr_info core_pwr_info[4]; |
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/* Antenna gain values for up to 4 antennas |
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* on each band. Values in dBm/4 (Q5.2). Negative gain means the |
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* loss in the connectors is bigger than the gain. */ |
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struct { |
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s8 a0, a1, a2, a3; |
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} antenna_gain; |
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struct { |
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struct { |
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u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; |
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} ghz2; |
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struct { |
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u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; |
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} ghz5; |
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} fem; |
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u16 mcs2gpo[8]; |
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u16 mcs5gpo[8]; |
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u16 mcs5glpo[8]; |
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u16 mcs5ghpo[8]; |
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u8 opo; |
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u8 rxgainerr2ga[3]; |
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u8 rxgainerr5gla[3]; |
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u8 rxgainerr5gma[3]; |
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u8 rxgainerr5gha[3]; |
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u8 rxgainerr5gua[3]; |
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u8 noiselvl2ga[3]; |
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u8 noiselvl5gla[3]; |
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u8 noiselvl5gma[3]; |
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u8 noiselvl5gha[3]; |
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u8 noiselvl5gua[3]; |
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u8 regrev; |
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u8 txchain; |
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u8 rxchain; |
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u8 antswitch; |
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u16 cddpo; |
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u16 stbcpo; |
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u16 bw40po; |
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u16 bwduppo; |
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u8 tempthresh; |
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u8 tempoffset; |
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u16 rawtempsense; |
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u8 measpower; |
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u8 tempsense_slope; |
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u8 tempcorrx; |
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u8 tempsense_option; |
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u8 freqoffset_corr; |
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u8 iqcal_swp_dis; |
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u8 hw_iqcal_en; |
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u8 elna2g; |
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u8 elna5g; |
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u8 phycal_tempdelta; |
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u8 temps_period; |
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u8 temps_hysteresis; |
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u8 measpower1; |
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u8 measpower2; |
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u8 pcieingress_war; |
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/* power per rate from sromrev 9 */ |
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u16 cckbw202gpo; |
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u16 cckbw20ul2gpo; |
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u32 legofdmbw202gpo; |
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u32 legofdmbw20ul2gpo; |
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u32 legofdmbw205glpo; |
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u32 legofdmbw20ul5glpo; |
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u32 legofdmbw205gmpo; |
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u32 legofdmbw20ul5gmpo; |
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u32 legofdmbw205ghpo; |
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u32 legofdmbw20ul5ghpo; |
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u32 mcsbw202gpo; |
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u32 mcsbw20ul2gpo; |
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u32 mcsbw402gpo; |
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u32 mcsbw205glpo; |
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u32 mcsbw20ul5glpo; |
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u32 mcsbw405glpo; |
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u32 mcsbw205gmpo; |
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u32 mcsbw20ul5gmpo; |
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u32 mcsbw405gmpo; |
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u32 mcsbw205ghpo; |
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u32 mcsbw20ul5ghpo; |
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u32 mcsbw405ghpo; |
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u16 mcs32po; |
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u16 legofdm40duppo; |
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u8 sar2g; |
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u8 sar5g; |
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}; |
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/* Information about the PCB the circuitry is soldered on. */ |
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struct ssb_boardinfo { |
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u16 vendor; |
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u16 type; |
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}; |
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struct ssb_device; |
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/* Lowlevel read/write operations on the device MMIO. |
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* Internal, don't use that outside of ssb. */ |
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struct ssb_bus_ops { |
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u8 (*read8)(struct ssb_device *dev, u16 offset); |
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u16 (*read16)(struct ssb_device *dev, u16 offset); |
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u32 (*read32)(struct ssb_device *dev, u16 offset); |
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void (*write8)(struct ssb_device *dev, u16 offset, u8 value); |
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void (*write16)(struct ssb_device *dev, u16 offset, u16 value); |
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void (*write32)(struct ssb_device *dev, u16 offset, u32 value); |
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#ifdef CONFIG_SSB_BLOCKIO |
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void (*block_read)(struct ssb_device *dev, void *buffer, |
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size_t count, u16 offset, u8 reg_width); |
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void (*block_write)(struct ssb_device *dev, const void *buffer, |
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size_t count, u16 offset, u8 reg_width); |
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#endif |
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}; |
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/* Core-ID values. */ |
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#define SSB_DEV_CHIPCOMMON 0x800 |
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#define SSB_DEV_ILINE20 0x801 |
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#define SSB_DEV_SDRAM 0x803 |
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#define SSB_DEV_PCI 0x804 |
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#define SSB_DEV_MIPS 0x805 |
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#define SSB_DEV_ETHERNET 0x806 |
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#define SSB_DEV_V90 0x807 |
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#define SSB_DEV_USB11_HOSTDEV 0x808 |
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#define SSB_DEV_ADSL 0x809 |
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#define SSB_DEV_ILINE100 0x80A |
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#define SSB_DEV_IPSEC 0x80B |
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#define SSB_DEV_PCMCIA 0x80D |
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#define SSB_DEV_INTERNAL_MEM 0x80E |
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#define SSB_DEV_MEMC_SDRAM 0x80F |
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#define SSB_DEV_EXTIF 0x811 |
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#define SSB_DEV_80211 0x812 |
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#define SSB_DEV_MIPS_3302 0x816 |
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#define SSB_DEV_USB11_HOST 0x817 |
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#define SSB_DEV_USB11_DEV 0x818 |
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#define SSB_DEV_USB20_HOST 0x819 |
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#define SSB_DEV_USB20_DEV 0x81A |
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#define SSB_DEV_SDIO_HOST 0x81B |
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#define SSB_DEV_ROBOSWITCH 0x81C |
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#define SSB_DEV_PARA_ATA 0x81D |
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#define SSB_DEV_SATA_XORDMA 0x81E |
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#define SSB_DEV_ETHERNET_GBIT 0x81F |
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#define SSB_DEV_PCIE 0x820 |
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#define SSB_DEV_MIMO_PHY 0x821 |
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#define SSB_DEV_SRAM_CTRLR 0x822 |
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#define SSB_DEV_MINI_MACPHY 0x823 |
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#define SSB_DEV_ARM_1176 0x824 |
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#define SSB_DEV_ARM_7TDMI 0x825 |
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#define SSB_DEV_ARM_CM3 0x82A |
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/* Vendor-ID values */ |
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#define SSB_VENDOR_BROADCOM 0x4243 |
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/* Some kernel subsystems poke with dev->drvdata, so we must use the |
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* following ugly workaround to get from struct device to struct ssb_device */ |
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struct __ssb_dev_wrapper { |
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struct device dev; |
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struct ssb_device *sdev; |
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}; |
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struct ssb_device { |
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/* Having a copy of the ops pointer in each dev struct |
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* is an optimization. */ |
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const struct ssb_bus_ops *ops; |
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struct device *dev, *dma_dev; |
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struct ssb_bus *bus; |
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struct ssb_device_id id; |
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u8 core_index; |
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unsigned int irq; |
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/* Internal-only stuff follows. */ |
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void *drvdata; /* Per-device data */ |
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void *devtypedata; /* Per-devicetype (eg 802.11) data */ |
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}; |
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/* Go from struct device to struct ssb_device. */ |
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static inline |
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struct ssb_device * dev_to_ssb_dev(struct device *dev) |
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{ |
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struct __ssb_dev_wrapper *wrap; |
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wrap = container_of(dev, struct __ssb_dev_wrapper, dev); |
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return wrap->sdev; |
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} |
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/* Device specific user data */ |
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static inline |
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void ssb_set_drvdata(struct ssb_device *dev, void *data) |
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{ |
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dev->drvdata = data; |
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} |
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static inline |
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void * ssb_get_drvdata(struct ssb_device *dev) |
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{ |
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return dev->drvdata; |
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} |
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/* Devicetype specific user data. This is per device-type (not per device) */ |
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void ssb_set_devtypedata(struct ssb_device *dev, void *data); |
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static inline |
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void * ssb_get_devtypedata(struct ssb_device *dev) |
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{ |
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return dev->devtypedata; |
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} |
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struct ssb_driver { |
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const char *name; |
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const struct ssb_device_id *id_table; |
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int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id); |
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void (*remove)(struct ssb_device *dev); |
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int (*suspend)(struct ssb_device *dev, pm_message_t state); |
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int (*resume)(struct ssb_device *dev); |
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void (*shutdown)(struct ssb_device *dev); |
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struct device_driver drv; |
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}; |
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#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) |
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extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); |
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#define ssb_driver_register(drv) \ |
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__ssb_driver_register(drv, THIS_MODULE) |
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extern void ssb_driver_unregister(struct ssb_driver *drv); |
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enum ssb_bustype { |
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SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ |
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SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ |
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SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */ |
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SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */ |
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}; |
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/* board_vendor */ |
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#define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */ |
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#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */ |
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#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */ |
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/* board_type */ |
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#define SSB_BOARD_BCM94301CB 0x0406 |
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#define SSB_BOARD_BCM94301MP 0x0407 |
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#define SSB_BOARD_BU4309 0x040A |
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#define SSB_BOARD_BCM94309CB 0x040B |
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#define SSB_BOARD_BCM4309MP 0x040C |
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#define SSB_BOARD_BU4306 0x0416 |
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#define SSB_BOARD_BCM94306MP 0x0418 |
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#define SSB_BOARD_BCM4309G 0x0421 |
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#define SSB_BOARD_BCM4306CB 0x0417 |
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#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ |
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#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */ |
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#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */ |
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#define SSB_BOARD_BU4704SD 0x042E /* with sdram */ |
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#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */ |
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#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */ |
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#define SSB_BOARD_BU4318 0x0447 |
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#define SSB_BOARD_CB4318 0x0448 |
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#define SSB_BOARD_MPG4318 0x0449 |
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#define SSB_BOARD_MP4318 0x044A |
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#define SSB_BOARD_SD4318 0x044B |
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#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */ |
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#define SSB_BOARD_BCM94303MP 0x044E |
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#define SSB_BOARD_BCM94306MPM 0x0450 |
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#define SSB_BOARD_BCM94306MPL 0x0453 |
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#define SSB_BOARD_PC4303 0x0454 /* pcmcia */ |
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#define SSB_BOARD_BCM94306MPLNA 0x0457 |
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#define SSB_BOARD_BCM94306MPH 0x045B |
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#define SSB_BOARD_BCM94306PCIV 0x045C |
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#define SSB_BOARD_BCM94318MPGH 0x0463 |
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#define SSB_BOARD_BU4311 0x0464 |
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#define SSB_BOARD_BCM94311MC 0x0465 |
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#define SSB_BOARD_BCM94311MCAG 0x0466 |
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/* 4321 boards */ |
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#define SSB_BOARD_BU4321 0x046B |
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#define SSB_BOARD_BU4321E 0x047C |
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#define SSB_BOARD_MP4321 0x046C |
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#define SSB_BOARD_CB2_4321 0x046D |
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#define SSB_BOARD_CB2_4321_AG 0x0066 |
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#define SSB_BOARD_MC4321 0x046E |
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/* 4325 boards */ |
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#define SSB_BOARD_BCM94325DEVBU 0x0490 |
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#define SSB_BOARD_BCM94325BGABU 0x0491 |
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#define SSB_BOARD_BCM94325SDGWB 0x0492 |
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#define SSB_BOARD_BCM94325SDGMDL 0x04AA |
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#define SSB_BOARD_BCM94325SDGMDL2 0x04C6 |
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#define SSB_BOARD_BCM94325SDGMDL3 0x04C9 |
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#define SSB_BOARD_BCM94325SDABGWBA 0x04E1 |
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/* 4322 boards */ |
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#define SSB_BOARD_BCM94322MC 0x04A4 |
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#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */ |
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#define SSB_BOARD_BCM94322HM 0x04B0 |
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#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */ |
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/* 4312 boards */ |
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#define SSB_BOARD_BU4312 0x048A |
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#define SSB_BOARD_BCM4312MCGSG 0x04B5 |
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/* chip_package */ |
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#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ |
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#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */ |
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#define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */ |
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#include <linux/ssb/ssb_driver_chipcommon.h> |
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#include <linux/ssb/ssb_driver_mips.h> |
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#include <linux/ssb/ssb_driver_extif.h> |
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#include <linux/ssb/ssb_driver_pci.h> |
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struct ssb_bus { |
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/* The MMIO area. */ |
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void __iomem *mmio; |
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const struct ssb_bus_ops *ops; |
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/* The core currently mapped into the MMIO window. |
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* Not valid on all host-buses. So don't use outside of SSB. */ |
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struct ssb_device *mapped_device; |
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union { |
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/* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ |
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u8 mapped_pcmcia_seg; |
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/* Current SSB base address window for SDIO. */ |
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u32 sdio_sbaddr; |
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}; |
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/* Lock for core and segment switching. |
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* On PCMCIA-host busses this is used to protect the whole MMIO access. */ |
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spinlock_t bar_lock; |
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/* The host-bus this backplane is running on. */ |
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enum ssb_bustype bustype; |
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/* Pointers to the host-bus. Check bustype before using any of these pointers. */ |
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union { |
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/* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ |
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struct pci_dev *host_pci; |
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/* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ |
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struct pcmcia_device *host_pcmcia; |
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/* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ |
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struct sdio_func *host_sdio; |
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}; |
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/* See enum ssb_quirks */ |
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unsigned int quirks; |
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#ifdef CONFIG_SSB_SPROM |
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/* Mutex to protect the SPROM writing. */ |
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struct mutex sprom_mutex; |
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#endif |
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/* ID information about the Chip. */ |
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u16 chip_id; |
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u8 chip_rev; |
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u16 sprom_offset; |
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u16 sprom_size; /* number of words in sprom */ |
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u8 chip_package; |
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/* List of devices (cores) on the backplane. */ |
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struct ssb_device devices[SSB_MAX_NR_CORES]; |
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u8 nr_devices; |
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/* Software ID number for this bus. */ |
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unsigned int busnumber; |
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/* The ChipCommon device (if available). */ |
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struct ssb_chipcommon chipco; |
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/* The PCI-core device (if available). */ |
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struct ssb_pcicore pcicore; |
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/* The MIPS-core device (if available). */ |
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struct ssb_mipscore mipscore; |
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/* The EXTif-core device (if available). */ |
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struct ssb_extif extif; |
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|
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/* The following structure elements are not available in early |
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* SSB initialization. Though, they are available for regular |
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* registered drivers at any stage. So be careful when |
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* using them in the ssb core code. */ |
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|
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/* ID information about the PCB. */ |
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struct ssb_boardinfo boardinfo; |
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/* Contents of the SPROM. */ |
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struct ssb_sprom sprom; |
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/* If the board has a cardbus slot, this is set to true. */ |
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bool has_cardbus_slot; |
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|
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#ifdef CONFIG_SSB_EMBEDDED |
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/* Lock for GPIO register access. */ |
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spinlock_t gpio_lock; |
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struct platform_device *watchdog; |
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#endif /* EMBEDDED */ |
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#ifdef CONFIG_SSB_DRIVER_GPIO |
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struct gpio_chip gpio; |
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struct irq_domain *irq_domain; |
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#endif /* DRIVER_GPIO */ |
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|
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/* Internal-only stuff follows. Do not touch. */ |
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struct list_head list; |
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/* Is the bus already powered up? */ |
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bool powered_up; |
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int power_warn_count; |
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}; |
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|
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enum ssb_quirks { |
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/* SDIO connected card requires performing a read after writing a 32-bit value */ |
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SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0), |
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}; |
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|
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/* The initialization-invariants. */ |
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struct ssb_init_invariants { |
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/* Versioning information about the PCB. */ |
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struct ssb_boardinfo boardinfo; |
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/* The SPROM information. That's either stored in an |
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* EEPROM or NVRAM on the board. */ |
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struct ssb_sprom sprom; |
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/* If the board has a cardbus slot, this is set to true. */ |
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bool has_cardbus_slot; |
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}; |
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/* Type of function to fetch the invariants. */ |
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typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus, |
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struct ssb_init_invariants *iv); |
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|
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/* Register SoC bus. */ |
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extern int ssb_bus_host_soc_register(struct ssb_bus *bus, |
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unsigned long baseaddr); |
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#ifdef CONFIG_SSB_PCIHOST |
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extern int ssb_bus_pcibus_register(struct ssb_bus *bus, |
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struct pci_dev *host_pci); |
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#endif /* CONFIG_SSB_PCIHOST */ |
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#ifdef CONFIG_SSB_PCMCIAHOST |
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extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus, |
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struct pcmcia_device *pcmcia_dev, |
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unsigned long baseaddr); |
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#endif /* CONFIG_SSB_PCMCIAHOST */ |
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#ifdef CONFIG_SSB_SDIOHOST |
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extern int ssb_bus_sdiobus_register(struct ssb_bus *bus, |
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struct sdio_func *sdio_func, |
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unsigned int quirks); |
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#endif /* CONFIG_SSB_SDIOHOST */ |
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|
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extern void ssb_bus_unregister(struct ssb_bus *bus); |
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|
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/* Does the device have an SPROM? */ |
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extern bool ssb_is_sprom_available(struct ssb_bus *bus); |
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|
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/* Set a fallback SPROM. |
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* See kdoc at the function definition for complete documentation. */ |
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extern int ssb_arch_register_fallback_sprom( |
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int (*sprom_callback)(struct ssb_bus *bus, |
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struct ssb_sprom *out)); |
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|
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/* Suspend a SSB bus. |
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* Call this from the parent bus suspend routine. */ |
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extern int ssb_bus_suspend(struct ssb_bus *bus); |
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/* Resume a SSB bus. |
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* Call this from the parent bus resume routine. */ |
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extern int ssb_bus_resume(struct ssb_bus *bus); |
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|
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extern u32 ssb_clockspeed(struct ssb_bus *bus); |
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|
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/* Is the device enabled in hardware? */ |
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int ssb_device_is_enabled(struct ssb_device *dev); |
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/* Enable a device and pass device-specific SSB_TMSLOW flags. |
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* If no device-specific flags are available, use 0. */ |
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void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags); |
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/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */ |
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void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags); |
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|
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|
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/* Device MMIO register read/write functions. */ |
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static inline u8 ssb_read8(struct ssb_device *dev, u16 offset) |
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{ |
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return dev->ops->read8(dev, offset); |
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} |
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static inline u16 ssb_read16(struct ssb_device *dev, u16 offset) |
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{ |
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return dev->ops->read16(dev, offset); |
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} |
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static inline u32 ssb_read32(struct ssb_device *dev, u16 offset) |
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{ |
|
return dev->ops->read32(dev, offset); |
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} |
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static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value) |
|
{ |
|
dev->ops->write8(dev, offset, value); |
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} |
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static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value) |
|
{ |
|
dev->ops->write16(dev, offset, value); |
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} |
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static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value) |
|
{ |
|
dev->ops->write32(dev, offset, value); |
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} |
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#ifdef CONFIG_SSB_BLOCKIO |
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static inline void ssb_block_read(struct ssb_device *dev, void *buffer, |
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size_t count, u16 offset, u8 reg_width) |
|
{ |
|
dev->ops->block_read(dev, buffer, count, offset, reg_width); |
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} |
|
|
|
static inline void ssb_block_write(struct ssb_device *dev, const void *buffer, |
|
size_t count, u16 offset, u8 reg_width) |
|
{ |
|
dev->ops->block_write(dev, buffer, count, offset, reg_width); |
|
} |
|
#endif /* CONFIG_SSB_BLOCKIO */ |
|
|
|
|
|
/* The SSB DMA API. Use this API for any DMA operation on the device. |
|
* This API basically is a wrapper that calls the correct DMA API for |
|
* the host device type the SSB device is attached to. */ |
|
|
|
/* Translation (routing) bits that need to be ORed to DMA |
|
* addresses before they are given to a device. */ |
|
extern u32 ssb_dma_translation(struct ssb_device *dev); |
|
#define SSB_DMA_TRANSLATION_MASK 0xC0000000 |
|
#define SSB_DMA_TRANSLATION_SHIFT 30 |
|
|
|
static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev) |
|
{ |
|
#ifdef CONFIG_SSB_DEBUG |
|
printk(KERN_ERR "SSB: BUG! Calling DMA API for " |
|
"unsupported bustype %d\n", dev->bus->bustype); |
|
#endif /* DEBUG */ |
|
} |
|
|
|
#ifdef CONFIG_SSB_PCIHOST |
|
/* PCI-host wrapper driver */ |
|
extern int ssb_pcihost_register(struct pci_driver *driver); |
|
static inline void ssb_pcihost_unregister(struct pci_driver *driver) |
|
{ |
|
pci_unregister_driver(driver); |
|
} |
|
|
|
static inline |
|
void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state) |
|
{ |
|
if (sdev->bus->bustype == SSB_BUSTYPE_PCI) |
|
pci_set_power_state(sdev->bus->host_pci, state); |
|
} |
|
#else |
|
static inline void ssb_pcihost_unregister(struct pci_driver *driver) |
|
{ |
|
} |
|
|
|
static inline |
|
void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state) |
|
{ |
|
} |
|
#endif /* CONFIG_SSB_PCIHOST */ |
|
|
|
|
|
/* If a driver is shutdown or suspended, call this to signal |
|
* that the bus may be completely powered down. SSB will decide, |
|
* if it's really time to power down the bus, based on if there |
|
* are other devices that want to run. */ |
|
extern int ssb_bus_may_powerdown(struct ssb_bus *bus); |
|
/* Before initializing and enabling a device, call this to power-up the bus. |
|
* If you want to allow use of dynamic-power-control, pass the flag. |
|
* Otherwise static always-on powercontrol will be used. */ |
|
extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); |
|
|
|
extern void ssb_commit_settings(struct ssb_bus *bus); |
|
|
|
/* Various helper functions */ |
|
extern u32 ssb_admatch_base(u32 adm); |
|
extern u32 ssb_admatch_size(u32 adm); |
|
|
|
/* PCI device mapping and fixup routines. |
|
* Called from the architecture pcibios init code. |
|
* These are only available on SSB_EMBEDDED configurations. */ |
|
#ifdef CONFIG_SSB_EMBEDDED |
|
int ssb_pcibios_plat_dev_init(struct pci_dev *dev); |
|
int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); |
|
#endif /* CONFIG_SSB_EMBEDDED */ |
|
|
|
#endif /* LINUX_SSB_H_ */
|
|
|