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135 lines
4.8 KiB
135 lines
4.8 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* include/linux/spi/mxs-spi.h |
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* |
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* Freescale i.MX233/i.MX28 SPI controller register definition |
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* |
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* Copyright 2008 Embedded Alley Solutions, Inc. |
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* Copyright 2009-2011 Freescale Semiconductor, Inc. |
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*/ |
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#ifndef __LINUX_SPI_MXS_SPI_H__ |
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#define __LINUX_SPI_MXS_SPI_H__ |
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#include <linux/dmaengine.h> |
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#define ssp_is_old(host) ((host)->devid == IMX23_SSP) |
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/* SSP registers */ |
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#define HW_SSP_CTRL0 0x000 |
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#define BM_SSP_CTRL0_RUN (1 << 29) |
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#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) |
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#define BM_SSP_CTRL0_LOCK_CS (1 << 27) |
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#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) |
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#define BM_SSP_CTRL0_READ (1 << 25) |
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#define BM_SSP_CTRL0_DATA_XFER (1 << 24) |
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#define BP_SSP_CTRL0_BUS_WIDTH 22 |
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#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) |
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#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) |
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#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20) |
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#define BM_SSP_CTRL0_LONG_RESP (1 << 19) |
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#define BM_SSP_CTRL0_GET_RESP (1 << 17) |
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#define BM_SSP_CTRL0_ENABLE (1 << 16) |
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#define BP_SSP_CTRL0_XFER_COUNT 0 |
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#define BM_SSP_CTRL0_XFER_COUNT 0xffff |
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#define HW_SSP_CMD0 0x010 |
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#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) |
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#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) |
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#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) |
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#define BM_SSP_CMD0_APPEND_8CYC (1 << 20) |
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#define BP_SSP_CMD0_BLOCK_SIZE 16 |
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#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) |
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#define BP_SSP_CMD0_BLOCK_COUNT 8 |
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#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) |
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#define BP_SSP_CMD0_CMD 0 |
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#define BM_SSP_CMD0_CMD 0xff |
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#define HW_SSP_CMD1 0x020 |
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#define HW_SSP_XFER_SIZE 0x030 |
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#define HW_SSP_BLOCK_SIZE 0x040 |
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#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4 |
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#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) |
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#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0 |
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#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf |
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#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070) |
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#define BP_SSP_TIMING_TIMEOUT 16 |
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#define BM_SSP_TIMING_TIMEOUT (0xffff << 16) |
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#define BP_SSP_TIMING_CLOCK_DIVIDE 8 |
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#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) |
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#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ |
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(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) |
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#define BP_SSP_TIMING_CLOCK_RATE 0 |
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#define BM_SSP_TIMING_CLOCK_RATE 0xff |
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#define BF_SSP_TIMING_CLOCK_RATE(v) \ |
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(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) |
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#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080) |
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#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) |
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#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) |
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#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) |
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#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) |
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) |
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#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) |
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) |
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#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) |
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#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) |
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#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) |
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) |
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#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) |
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) |
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#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) |
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) |
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#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) |
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#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) |
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#define BM_SSP_CTRL1_PHASE (1 << 10) |
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#define BM_SSP_CTRL1_POLARITY (1 << 9) |
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#define BP_SSP_CTRL1_WORD_LENGTH 4 |
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#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) |
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#define BF_SSP_CTRL1_WORD_LENGTH(v) \ |
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(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) |
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#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 |
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#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 |
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#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF |
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#define BP_SSP_CTRL1_SSP_MODE 0 |
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#define BM_SSP_CTRL1_SSP_MODE 0xf |
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#define BF_SSP_CTRL1_SSP_MODE(v) \ |
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(((v) << 0) & BM_SSP_CTRL1_SSP_MODE) |
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#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 |
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#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 |
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#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 |
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#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 |
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#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090) |
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#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0) |
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#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0) |
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#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0) |
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#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0) |
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#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100) |
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#define BM_SSP_STATUS_CARD_DETECT (1 << 28) |
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#define BM_SSP_STATUS_SDIO_IRQ (1 << 17) |
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#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5) |
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#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) |
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#define SSP_PIO_NUM 3 |
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enum mxs_ssp_id { |
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IMX23_SSP, |
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IMX28_SSP, |
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}; |
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struct mxs_ssp { |
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struct device *dev; |
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void __iomem *base; |
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struct clk *clk; |
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unsigned int clk_rate; |
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enum mxs_ssp_id devid; |
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struct dma_chan *dmach; |
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unsigned int dma_dir; |
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enum dma_transfer_direction slave_dirn; |
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u32 ssp_pio_words[SSP_PIO_NUM]; |
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}; |
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void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate); |
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#endif /* __LINUX_SPI_MXS_SPI_H__ */
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