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1013 lines
30 KiB
1013 lines
30 KiB
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ |
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/* Copyright(c) 2015-17 Intel Corporation. */ |
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#ifndef __SOUNDWIRE_H |
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#define __SOUNDWIRE_H |
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#include <linux/mod_devicetable.h> |
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#include <linux/bitfield.h> |
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struct sdw_bus; |
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struct sdw_slave; |
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/* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ |
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/* SDW Broadcast Device Number */ |
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#define SDW_BROADCAST_DEV_NUM 15 |
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/* SDW Enumeration Device Number */ |
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#define SDW_ENUM_DEV_NUM 0 |
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/* SDW Group Device Numbers */ |
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#define SDW_GROUP12_DEV_NUM 12 |
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#define SDW_GROUP13_DEV_NUM 13 |
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/* SDW Master Device Number, not supported yet */ |
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#define SDW_MASTER_DEV_NUM 14 |
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#define SDW_NUM_DEV_ID_REGISTERS 6 |
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/* frame shape defines */ |
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/* |
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* Note: The maximum row define in SoundWire spec 1.1 is 23. In order to |
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* fill hole with 0, one more dummy entry is added |
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*/ |
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#define SDW_FRAME_ROWS 24 |
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#define SDW_FRAME_COLS 8 |
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#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) |
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#define SDW_FRAME_CTRL_BITS 48 |
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#define SDW_MAX_DEVICES 11 |
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#define SDW_MAX_PORTS 15 |
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#define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1) |
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enum { |
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SDW_PORT_DIRN_SINK = 0, |
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SDW_PORT_DIRN_SOURCE, |
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SDW_PORT_DIRN_MAX, |
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}; |
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/* |
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* constants for flow control, ports and transport |
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* |
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* these are bit masks as devices can have multiple capabilities |
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*/ |
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/* |
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* flow modes for SDW port. These can be isochronous, tx controlled, |
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* rx controlled or async |
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*/ |
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#define SDW_PORT_FLOW_MODE_ISOCH 0 |
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#define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) |
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#define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) |
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#define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) |
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/* sample packaging for block. It can be per port or per channel */ |
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#define SDW_BLOCK_PACKG_PER_PORT BIT(0) |
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#define SDW_BLOCK_PACKG_PER_CH BIT(1) |
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/** |
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* enum sdw_slave_status - Slave status |
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* @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. |
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* @SDW_SLAVE_ATTACHED: Slave is attached with bus. |
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* @SDW_SLAVE_ALERT: Some alert condition on the Slave |
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* @SDW_SLAVE_RESERVED: Reserved for future use |
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*/ |
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enum sdw_slave_status { |
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SDW_SLAVE_UNATTACHED = 0, |
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SDW_SLAVE_ATTACHED = 1, |
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SDW_SLAVE_ALERT = 2, |
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SDW_SLAVE_RESERVED = 3, |
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}; |
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/** |
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* enum sdw_clk_stop_type: clock stop operations |
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* |
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* @SDW_CLK_PRE_PREPARE: pre clock stop prepare |
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* @SDW_CLK_POST_PREPARE: post clock stop prepare |
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* @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare |
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* @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare |
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*/ |
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enum sdw_clk_stop_type { |
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SDW_CLK_PRE_PREPARE = 0, |
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SDW_CLK_POST_PREPARE, |
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SDW_CLK_PRE_DEPREPARE, |
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SDW_CLK_POST_DEPREPARE, |
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}; |
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/** |
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* enum sdw_command_response - Command response as defined by SDW spec |
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* @SDW_CMD_OK: cmd was successful |
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* @SDW_CMD_IGNORED: cmd was ignored |
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* @SDW_CMD_FAIL: cmd was NACKed |
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* @SDW_CMD_TIMEOUT: cmd timedout |
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* @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above |
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* |
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* NOTE: The enum is different than actual Spec as response in the Spec is |
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* combination of ACK/NAK bits |
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* |
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* SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec |
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*/ |
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enum sdw_command_response { |
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SDW_CMD_OK = 0, |
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SDW_CMD_IGNORED = 1, |
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SDW_CMD_FAIL = 2, |
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SDW_CMD_TIMEOUT = 3, |
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SDW_CMD_FAIL_OTHER = 4, |
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}; |
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/* block group count enum */ |
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enum sdw_dpn_grouping { |
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SDW_BLK_GRP_CNT_1 = 0, |
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SDW_BLK_GRP_CNT_2 = 1, |
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SDW_BLK_GRP_CNT_3 = 2, |
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SDW_BLK_GRP_CNT_4 = 3, |
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}; |
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/** |
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* enum sdw_stream_type: data stream type |
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* |
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* @SDW_STREAM_PCM: PCM data stream |
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* @SDW_STREAM_PDM: PDM data stream |
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* |
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* spec doesn't define this, but is used in implementation |
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*/ |
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enum sdw_stream_type { |
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SDW_STREAM_PCM = 0, |
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SDW_STREAM_PDM = 1, |
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}; |
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/** |
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* enum sdw_data_direction: Data direction |
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* |
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* @SDW_DATA_DIR_RX: Data into Port |
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* @SDW_DATA_DIR_TX: Data out of Port |
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*/ |
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enum sdw_data_direction { |
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SDW_DATA_DIR_RX = 0, |
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SDW_DATA_DIR_TX = 1, |
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}; |
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/** |
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* enum sdw_port_data_mode: Data Port mode |
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* |
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* @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received |
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* and transmitted. |
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* @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce |
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* a pseudo random data pattern that is transferred |
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* @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of |
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* logic 0. The encoding will result in no signal transitions |
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* @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of |
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* logic 1. The encoding will result in signal transitions at every bitslot |
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* owned by this Port |
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*/ |
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enum sdw_port_data_mode { |
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SDW_PORT_DATA_MODE_NORMAL = 0, |
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SDW_PORT_DATA_MODE_PRBS = 1, |
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SDW_PORT_DATA_MODE_STATIC_0 = 2, |
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SDW_PORT_DATA_MODE_STATIC_1 = 3, |
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}; |
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/* |
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* SDW properties, defined in MIPI DisCo spec v1.0 |
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*/ |
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enum sdw_clk_stop_reset_behave { |
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SDW_CLK_STOP_KEEP_STATUS = 1, |
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}; |
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/** |
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* enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a |
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* read |
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* @SDW_P15_READ_IGNORED: Read is ignored |
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* @SDW_P15_CMD_OK: Command is ok |
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*/ |
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enum sdw_p15_behave { |
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SDW_P15_READ_IGNORED = 0, |
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SDW_P15_CMD_OK = 1, |
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}; |
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/** |
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* enum sdw_dpn_type - Data port types |
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* @SDW_DPN_FULL: Full Data Port is supported |
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* @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. |
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* DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 |
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* are not implemented. |
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* @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. |
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* DPN_SampleCtrl2, DPN_HCtrl are not implemented. |
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*/ |
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enum sdw_dpn_type { |
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SDW_DPN_FULL = 0, |
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SDW_DPN_SIMPLE = 1, |
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SDW_DPN_REDUCED = 2, |
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}; |
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/** |
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* enum sdw_clk_stop_mode - Clock Stop modes |
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* @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock |
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* restart |
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* @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, |
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* not capable of continuing operation seamlessly when the clock restarts |
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*/ |
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enum sdw_clk_stop_mode { |
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SDW_CLK_STOP_MODE0 = 0, |
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SDW_CLK_STOP_MODE1 = 1, |
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}; |
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/** |
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* struct sdw_dp0_prop - DP0 properties |
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* @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 |
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* (inclusive) |
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* @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 |
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* (inclusive) |
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* @num_words: number of wordlengths supported |
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* @words: wordlengths supported |
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* @BRA_flow_controlled: Slave implementation results in an OK_NotReady |
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* response |
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* @simple_ch_prep_sm: If channel prepare sequence is required |
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* @imp_def_interrupts: If set, each bit corresponds to support for |
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* implementation-defined interrupts |
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* |
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* The wordlengths are specified by Spec as max, min AND number of |
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* discrete values, implementation can define based on the wordlengths they |
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* support |
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*/ |
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struct sdw_dp0_prop { |
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u32 max_word; |
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u32 min_word; |
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u32 num_words; |
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u32 *words; |
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bool BRA_flow_controlled; |
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bool simple_ch_prep_sm; |
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bool imp_def_interrupts; |
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}; |
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/** |
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* struct sdw_dpn_audio_mode - Audio mode properties for DPn |
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* @bus_min_freq: Minimum bus frequency, in Hz |
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* @bus_max_freq: Maximum bus frequency, in Hz |
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* @bus_num_freq: Number of discrete frequencies supported |
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* @bus_freq: Discrete bus frequencies, in Hz |
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* @min_freq: Minimum sampling frequency, in Hz |
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* @max_freq: Maximum sampling bus frequency, in Hz |
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* @num_freq: Number of discrete sampling frequency supported |
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* @freq: Discrete sampling frequencies, in Hz |
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* @prep_ch_behave: Specifies the dependencies between Channel Prepare |
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* sequence and bus clock configuration |
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* If 0, Channel Prepare can happen at any Bus clock rate |
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* If 1, Channel Prepare sequence shall happen only after Bus clock is |
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* changed to a frequency supported by this mode or compatible modes |
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* described by the next field |
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* @glitchless: Bitmap describing possible glitchless transitions from this |
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* Audio Mode to other Audio Modes |
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*/ |
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struct sdw_dpn_audio_mode { |
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u32 bus_min_freq; |
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u32 bus_max_freq; |
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u32 bus_num_freq; |
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u32 *bus_freq; |
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u32 max_freq; |
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u32 min_freq; |
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u32 num_freq; |
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u32 *freq; |
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u32 prep_ch_behave; |
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u32 glitchless; |
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}; |
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/** |
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* struct sdw_dpn_prop - Data Port DPn properties |
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* @num: port number |
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* @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 |
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* (inclusive) |
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* @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 |
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* (inclusive) |
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* @num_words: Number of discrete supported wordlengths |
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* @words: Discrete supported wordlength |
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* @type: Data port type. Full, Simplified or Reduced |
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* @max_grouping: Maximum number of samples that can be grouped together for |
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* a full data port |
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* @simple_ch_prep_sm: If the port supports simplified channel prepare state |
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* machine |
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* @ch_prep_timeout: Port-specific timeout value, in milliseconds |
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* @imp_def_interrupts: If set, each bit corresponds to support for |
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* implementation-defined interrupts |
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* @max_ch: Maximum channels supported |
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* @min_ch: Minimum channels supported |
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* @num_channels: Number of discrete channels supported |
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* @channels: Discrete channels supported |
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* @num_ch_combinations: Number of channel combinations supported |
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* @ch_combinations: Channel combinations supported |
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* @modes: SDW mode supported |
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* @max_async_buffer: Number of samples that this port can buffer in |
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* asynchronous modes |
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* @block_pack_mode: Type of block port mode supported |
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* @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register |
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* @port_encoding: Payload Channel Sample encoding schemes supported |
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* @audio_modes: Audio modes supported |
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*/ |
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struct sdw_dpn_prop { |
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u32 num; |
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u32 max_word; |
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u32 min_word; |
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u32 num_words; |
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u32 *words; |
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enum sdw_dpn_type type; |
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u32 max_grouping; |
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bool simple_ch_prep_sm; |
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u32 ch_prep_timeout; |
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u32 imp_def_interrupts; |
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u32 max_ch; |
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u32 min_ch; |
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u32 num_channels; |
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u32 *channels; |
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u32 num_ch_combinations; |
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u32 *ch_combinations; |
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u32 modes; |
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u32 max_async_buffer; |
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bool block_pack_mode; |
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bool read_only_wordlength; |
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u32 port_encoding; |
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struct sdw_dpn_audio_mode *audio_modes; |
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}; |
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/** |
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* struct sdw_slave_prop - SoundWire Slave properties |
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* @mipi_revision: Spec version of the implementation |
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* @wake_capable: Wake-up events are supported |
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* @test_mode_capable: If test mode is supported |
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* @clk_stop_mode1: Clock-Stop Mode 1 is supported |
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* @simple_clk_stop_capable: Simple clock mode is supported |
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* @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State |
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* Machine transitions, in milliseconds |
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* @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine |
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* transitions, in milliseconds |
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* @reset_behave: Slave keeps the status of the SlaveStopClockPrepare |
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* state machine (P=1 SCSP_SM) after exit from clock-stop mode1 |
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* @high_PHY_capable: Slave is HighPHY capable |
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* @paging_support: Slave implements paging registers SCP_AddrPage1 and |
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* SCP_AddrPage2 |
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* @bank_delay_support: Slave implements bank delay/bridge support registers |
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* SCP_BankDelay and SCP_NextFrame |
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* @p15_behave: Slave behavior when the Master attempts a read to the Port15 |
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* alias |
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* @lane_control_support: Slave supports lane control |
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* @master_count: Number of Masters present on this Slave |
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* @source_ports: Bitmap identifying source ports |
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* @sink_ports: Bitmap identifying sink ports |
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* @dp0_prop: Data Port 0 properties |
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* @src_dpn_prop: Source Data Port N properties |
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* @sink_dpn_prop: Sink Data Port N properties |
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* @scp_int1_mask: SCP_INT1_MASK desired settings |
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* @quirks: bitmask identifying deltas from the MIPI specification |
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* @is_sdca: the Slave supports the SDCA specification |
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*/ |
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struct sdw_slave_prop { |
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u32 mipi_revision; |
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bool wake_capable; |
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bool test_mode_capable; |
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bool clk_stop_mode1; |
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bool simple_clk_stop_capable; |
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u32 clk_stop_timeout; |
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u32 ch_prep_timeout; |
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enum sdw_clk_stop_reset_behave reset_behave; |
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bool high_PHY_capable; |
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bool paging_support; |
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bool bank_delay_support; |
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enum sdw_p15_behave p15_behave; |
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bool lane_control_support; |
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u32 master_count; |
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u32 source_ports; |
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u32 sink_ports; |
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struct sdw_dp0_prop *dp0_prop; |
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struct sdw_dpn_prop *src_dpn_prop; |
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struct sdw_dpn_prop *sink_dpn_prop; |
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u8 scp_int1_mask; |
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u32 quirks; |
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bool is_sdca; |
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}; |
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#define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0) |
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/** |
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* struct sdw_master_prop - Master properties |
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* @revision: MIPI spec version of the implementation |
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* @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported |
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* @max_clk_freq: Maximum Bus clock frequency, in Hz |
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* @num_clk_gears: Number of clock gears supported |
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* @clk_gears: Clock gears supported |
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* @num_clk_freq: Number of clock frequencies supported, in Hz |
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* @clk_freq: Clock frequencies supported, in Hz |
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* @default_frame_rate: Controller default Frame rate, in Hz |
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* @default_row: Number of rows |
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* @default_col: Number of columns |
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* @dynamic_frame: Dynamic frame shape supported |
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* @err_threshold: Number of times that software may retry sending a single |
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* command |
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* @mclk_freq: clock reference passed to SoundWire Master, in Hz. |
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* @hw_disabled: if true, the Master is not functional, typically due to pin-mux |
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*/ |
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struct sdw_master_prop { |
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u32 revision; |
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u32 clk_stop_modes; |
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u32 max_clk_freq; |
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u32 num_clk_gears; |
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u32 *clk_gears; |
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u32 num_clk_freq; |
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u32 *clk_freq; |
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u32 default_frame_rate; |
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u32 default_row; |
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u32 default_col; |
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bool dynamic_frame; |
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u32 err_threshold; |
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u32 mclk_freq; |
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bool hw_disabled; |
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}; |
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int sdw_master_read_prop(struct sdw_bus *bus); |
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int sdw_slave_read_prop(struct sdw_slave *slave); |
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/* |
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* SDW Slave Structures and APIs |
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*/ |
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#define SDW_IGNORED_UNIQUE_ID 0xFF |
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/** |
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* struct sdw_slave_id - Slave ID |
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* @mfg_id: MIPI Manufacturer ID |
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* @part_id: Device Part ID |
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* @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) |
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* @unique_id: Device unique ID |
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* @sdw_version: SDW version implemented |
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* |
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* The order of the IDs here does not follow the DisCo spec definitions |
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*/ |
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struct sdw_slave_id { |
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__u16 mfg_id; |
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__u16 part_id; |
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__u8 class_id; |
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__u8 unique_id; |
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__u8 sdw_version:4; |
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}; |
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/* |
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* Helper macros to extract the MIPI-defined IDs |
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* |
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* Spec definition |
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* Register Bit Contents |
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* DevId_0 [7:4] 47:44 sdw_version |
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* DevId_0 [3:0] 43:40 unique_id |
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* DevId_1 39:32 mfg_id [15:8] |
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* DevId_2 31:24 mfg_id [7:0] |
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* DevId_3 23:16 part_id [15:8] |
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* DevId_4 15:08 part_id [7:0] |
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* DevId_5 07:00 class_id |
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* |
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* The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48 |
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*/ |
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#define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48) |
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#define SDW_VERSION_MASK GENMASK_ULL(47, 44) |
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#define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40) |
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#define SDW_MFG_ID_MASK GENMASK_ULL(39, 24) |
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#define SDW_PART_ID_MASK GENMASK_ULL(23, 8) |
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#define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0) |
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#define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr) |
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#define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr) |
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#define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr) |
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#define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr) |
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#define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr) |
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#define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr) |
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/** |
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* struct sdw_slave_intr_status - Slave interrupt status |
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* @sdca_cascade: set if the Slave device reports an SDCA interrupt |
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* @control_port: control port status |
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* @port: data port status |
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*/ |
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struct sdw_slave_intr_status { |
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bool sdca_cascade; |
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u8 control_port; |
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u8 port[15]; |
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}; |
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/** |
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* sdw_reg_bank - SoundWire register banks |
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* @SDW_BANK0: Soundwire register bank 0 |
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* @SDW_BANK1: Soundwire register bank 1 |
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*/ |
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enum sdw_reg_bank { |
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SDW_BANK0, |
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SDW_BANK1, |
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}; |
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/** |
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* struct sdw_bus_conf: Bus configuration |
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* |
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* @clk_freq: Clock frequency, in Hz |
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* @num_rows: Number of rows in frame |
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* @num_cols: Number of columns in frame |
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* @bank: Next register bank |
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*/ |
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struct sdw_bus_conf { |
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unsigned int clk_freq; |
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unsigned int num_rows; |
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unsigned int num_cols; |
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unsigned int bank; |
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}; |
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|
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/** |
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* struct sdw_prepare_ch: Prepare/De-prepare Data Port channel |
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* |
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* @num: Port number |
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* @ch_mask: Active channel mask |
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* @prepare: Prepare (true) /de-prepare (false) channel |
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* @bank: Register bank, which bank Slave/Master driver should program for |
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* implementation defined registers. This is always updated to next_bank |
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* value read from bus params. |
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* |
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*/ |
|
struct sdw_prepare_ch { |
|
unsigned int num; |
|
unsigned int ch_mask; |
|
bool prepare; |
|
unsigned int bank; |
|
}; |
|
|
|
/** |
|
* enum sdw_port_prep_ops: Prepare operations for Data Port |
|
* |
|
* @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port |
|
* @SDW_OPS_PORT_PREP: Prepare operation for the Port |
|
* @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port |
|
*/ |
|
enum sdw_port_prep_ops { |
|
SDW_OPS_PORT_PRE_PREP = 0, |
|
SDW_OPS_PORT_PREP = 1, |
|
SDW_OPS_PORT_POST_PREP = 2, |
|
}; |
|
|
|
/** |
|
* struct sdw_bus_params: Structure holding bus configuration |
|
* |
|
* @curr_bank: Current bank in use (BANK0/BANK1) |
|
* @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be |
|
* set to !curr_bank |
|
* @max_dr_freq: Maximum double rate clock frequency supported, in Hz |
|
* @curr_dr_freq: Current double rate clock frequency, in Hz |
|
* @bandwidth: Current bandwidth |
|
* @col: Active columns |
|
* @row: Active rows |
|
* @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports |
|
* @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value |
|
* should be the same to detect transmission issues, but can be different to |
|
* test the interrupt reports |
|
*/ |
|
struct sdw_bus_params { |
|
enum sdw_reg_bank curr_bank; |
|
enum sdw_reg_bank next_bank; |
|
unsigned int max_dr_freq; |
|
unsigned int curr_dr_freq; |
|
unsigned int bandwidth; |
|
unsigned int col; |
|
unsigned int row; |
|
int s_data_mode; |
|
int m_data_mode; |
|
}; |
|
|
|
/** |
|
* struct sdw_slave_ops: Slave driver callback ops |
|
* |
|
* @read_prop: Read Slave properties |
|
* @interrupt_callback: Device interrupt notification (invoked in thread |
|
* context) |
|
* @update_status: Update Slave status |
|
* @bus_config: Update the bus config for Slave |
|
* @port_prep: Prepare the port with parameters |
|
*/ |
|
struct sdw_slave_ops { |
|
int (*read_prop)(struct sdw_slave *sdw); |
|
int (*interrupt_callback)(struct sdw_slave *slave, |
|
struct sdw_slave_intr_status *status); |
|
int (*update_status)(struct sdw_slave *slave, |
|
enum sdw_slave_status status); |
|
int (*bus_config)(struct sdw_slave *slave, |
|
struct sdw_bus_params *params); |
|
int (*port_prep)(struct sdw_slave *slave, |
|
struct sdw_prepare_ch *prepare_ch, |
|
enum sdw_port_prep_ops pre_ops); |
|
int (*get_clk_stop_mode)(struct sdw_slave *slave); |
|
int (*clk_stop)(struct sdw_slave *slave, |
|
enum sdw_clk_stop_mode mode, |
|
enum sdw_clk_stop_type type); |
|
|
|
}; |
|
|
|
/** |
|
* struct sdw_slave - SoundWire Slave |
|
* @id: MIPI device ID |
|
* @dev: Linux device |
|
* @status: Status reported by the Slave |
|
* @bus: Bus handle |
|
* @ops: Slave callback ops |
|
* @prop: Slave properties |
|
* @debugfs: Slave debugfs |
|
* @node: node for bus list |
|
* @port_ready: Port ready completion flag for each Slave port |
|
* @dev_num: Current Device Number, values can be 0 or dev_num_sticky |
|
* @dev_num_sticky: one-time static Device Number assigned by Bus |
|
* @probed: boolean tracking driver state |
|
* @probe_complete: completion utility to control potential races |
|
* on startup between driver probe/initialization and SoundWire |
|
* Slave state changes/implementation-defined interrupts |
|
* @enumeration_complete: completion utility to control potential races |
|
* on startup between device enumeration and read/write access to the |
|
* Slave device |
|
* @initialization_complete: completion utility to control potential races |
|
* on startup between device enumeration and settings being restored |
|
* @unattach_request: mask field to keep track why the Slave re-attached and |
|
* was re-initialized. This is useful to deal with potential race conditions |
|
* between the Master suspending and the codec resuming, and make sure that |
|
* when the Master triggered a reset the Slave is properly enumerated and |
|
* initialized |
|
* @first_interrupt_done: status flag tracking if the interrupt handling |
|
* for a Slave happens for the first time after enumeration |
|
*/ |
|
struct sdw_slave { |
|
struct sdw_slave_id id; |
|
struct device dev; |
|
enum sdw_slave_status status; |
|
struct sdw_bus *bus; |
|
const struct sdw_slave_ops *ops; |
|
struct sdw_slave_prop prop; |
|
#ifdef CONFIG_DEBUG_FS |
|
struct dentry *debugfs; |
|
#endif |
|
struct list_head node; |
|
struct completion port_ready[SDW_MAX_PORTS]; |
|
enum sdw_clk_stop_mode curr_clk_stop_mode; |
|
u16 dev_num; |
|
u16 dev_num_sticky; |
|
bool probed; |
|
struct completion probe_complete; |
|
struct completion enumeration_complete; |
|
struct completion initialization_complete; |
|
u32 unattach_request; |
|
bool first_interrupt_done; |
|
}; |
|
|
|
#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) |
|
|
|
/** |
|
* struct sdw_master_device - SoundWire 'Master Device' representation |
|
* @dev: Linux device for this Master |
|
* @bus: Bus handle shortcut |
|
*/ |
|
struct sdw_master_device { |
|
struct device dev; |
|
struct sdw_bus *bus; |
|
}; |
|
|
|
#define dev_to_sdw_master_device(d) \ |
|
container_of(d, struct sdw_master_device, dev) |
|
|
|
struct sdw_driver { |
|
const char *name; |
|
|
|
int (*probe)(struct sdw_slave *sdw, |
|
const struct sdw_device_id *id); |
|
int (*remove)(struct sdw_slave *sdw); |
|
void (*shutdown)(struct sdw_slave *sdw); |
|
|
|
const struct sdw_device_id *id_table; |
|
const struct sdw_slave_ops *ops; |
|
|
|
struct device_driver driver; |
|
}; |
|
|
|
#define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ |
|
{ .mfg_id = (_mfg_id), .part_id = (_part_id), \ |
|
.sdw_version = (_version), .class_id = (_c_id), \ |
|
.driver_data = (unsigned long)(_drv_data) } |
|
|
|
#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ |
|
SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) |
|
|
|
int sdw_handle_slave_status(struct sdw_bus *bus, |
|
enum sdw_slave_status status[]); |
|
|
|
/* |
|
* SDW master structures and APIs |
|
*/ |
|
|
|
/** |
|
* struct sdw_port_params: Data Port parameters |
|
* |
|
* @num: Port number |
|
* @bps: Word length of the Port |
|
* @flow_mode: Port Data flow mode |
|
* @data_mode: Test modes or normal mode |
|
* |
|
* This is used to program the Data Port based on Data Port stream |
|
* parameters. |
|
*/ |
|
struct sdw_port_params { |
|
unsigned int num; |
|
unsigned int bps; |
|
unsigned int flow_mode; |
|
unsigned int data_mode; |
|
}; |
|
|
|
/** |
|
* struct sdw_transport_params: Data Port Transport Parameters |
|
* |
|
* @blk_grp_ctrl_valid: Port implements block group control |
|
* @num: Port number |
|
* @blk_grp_ctrl: Block group control value |
|
* @sample_interval: Sample interval |
|
* @offset1: Blockoffset of the payload data |
|
* @offset2: Blockoffset of the payload data |
|
* @hstart: Horizontal start of the payload data |
|
* @hstop: Horizontal stop of the payload data |
|
* @blk_pkg_mode: Block per channel or block per port |
|
* @lane_ctrl: Data lane Port uses for Data transfer. Currently only single |
|
* data lane is supported in bus |
|
* |
|
* This is used to program the Data Port based on Data Port transport |
|
* parameters. All these parameters are banked and can be modified |
|
* during a bank switch without any artifacts in audio stream. |
|
*/ |
|
struct sdw_transport_params { |
|
bool blk_grp_ctrl_valid; |
|
unsigned int port_num; |
|
unsigned int blk_grp_ctrl; |
|
unsigned int sample_interval; |
|
unsigned int offset1; |
|
unsigned int offset2; |
|
unsigned int hstart; |
|
unsigned int hstop; |
|
unsigned int blk_pkg_mode; |
|
unsigned int lane_ctrl; |
|
}; |
|
|
|
/** |
|
* struct sdw_enable_ch: Enable/disable Data Port channel |
|
* |
|
* @num: Port number |
|
* @ch_mask: Active channel mask |
|
* @enable: Enable (true) /disable (false) channel |
|
*/ |
|
struct sdw_enable_ch { |
|
unsigned int port_num; |
|
unsigned int ch_mask; |
|
bool enable; |
|
}; |
|
|
|
/** |
|
* struct sdw_master_port_ops: Callback functions from bus to Master |
|
* driver to set Master Data ports. |
|
* |
|
* @dpn_set_port_params: Set the Port parameters for the Master Port. |
|
* Mandatory callback |
|
* @dpn_set_port_transport_params: Set transport parameters for the Master |
|
* Port. Mandatory callback |
|
* @dpn_port_prep: Port prepare operations for the Master Data Port. |
|
* @dpn_port_enable_ch: Enable the channels of Master Port. |
|
*/ |
|
struct sdw_master_port_ops { |
|
int (*dpn_set_port_params)(struct sdw_bus *bus, |
|
struct sdw_port_params *port_params, |
|
unsigned int bank); |
|
int (*dpn_set_port_transport_params)(struct sdw_bus *bus, |
|
struct sdw_transport_params *transport_params, |
|
enum sdw_reg_bank bank); |
|
int (*dpn_port_prep)(struct sdw_bus *bus, |
|
struct sdw_prepare_ch *prepare_ch); |
|
int (*dpn_port_enable_ch)(struct sdw_bus *bus, |
|
struct sdw_enable_ch *enable_ch, unsigned int bank); |
|
}; |
|
|
|
struct sdw_msg; |
|
|
|
/** |
|
* struct sdw_defer - SDW deffered message |
|
* @length: message length |
|
* @complete: message completion |
|
* @msg: SDW message |
|
*/ |
|
struct sdw_defer { |
|
int length; |
|
struct completion complete; |
|
struct sdw_msg *msg; |
|
}; |
|
|
|
/** |
|
* struct sdw_master_ops - Master driver ops |
|
* @read_prop: Read Master properties |
|
* @xfer_msg: Transfer message callback |
|
* @xfer_msg_defer: Defer version of transfer message callback |
|
* @reset_page_addr: Reset the SCP page address registers |
|
* @set_bus_conf: Set the bus configuration |
|
* @pre_bank_switch: Callback for pre bank switch |
|
* @post_bank_switch: Callback for post bank switch |
|
*/ |
|
struct sdw_master_ops { |
|
int (*read_prop)(struct sdw_bus *bus); |
|
|
|
enum sdw_command_response (*xfer_msg) |
|
(struct sdw_bus *bus, struct sdw_msg *msg); |
|
enum sdw_command_response (*xfer_msg_defer) |
|
(struct sdw_bus *bus, struct sdw_msg *msg, |
|
struct sdw_defer *defer); |
|
enum sdw_command_response (*reset_page_addr) |
|
(struct sdw_bus *bus, unsigned int dev_num); |
|
int (*set_bus_conf)(struct sdw_bus *bus, |
|
struct sdw_bus_params *params); |
|
int (*pre_bank_switch)(struct sdw_bus *bus); |
|
int (*post_bank_switch)(struct sdw_bus *bus); |
|
|
|
}; |
|
|
|
/** |
|
* struct sdw_bus - SoundWire bus |
|
* @dev: Shortcut to &bus->md->dev to avoid changing the entire code. |
|
* @md: Master device |
|
* @link_id: Link id number, can be 0 to N, unique for each Master |
|
* @id: bus system-wide unique id |
|
* @slaves: list of Slaves on this bus |
|
* @assigned: Bitmap for Slave device numbers. |
|
* Bit set implies used number, bit clear implies unused number. |
|
* @bus_lock: bus lock |
|
* @msg_lock: message lock |
|
* @compute_params: points to Bus resource management implementation |
|
* @ops: Master callback ops |
|
* @port_ops: Master port callback ops |
|
* @params: Current bus parameters |
|
* @prop: Master properties |
|
* @m_rt_list: List of Master instance of all stream(s) running on Bus. This |
|
* is used to compute and program bus bandwidth, clock, frame shape, |
|
* transport and port parameters |
|
* @debugfs: Bus debugfs |
|
* @defer_msg: Defer message |
|
* @clk_stop_timeout: Clock stop timeout computed |
|
* @bank_switch_timeout: Bank switch timeout computed |
|
* @multi_link: Store bus property that indicates if multi links |
|
* are supported. This flag is populated by drivers after reading |
|
* appropriate firmware (ACPI/DT). |
|
* @hw_sync_min_links: Number of links used by a stream above which |
|
* hardware-based synchronization is required. This value is only |
|
* meaningful if multi_link is set. If set to 1, hardware-based |
|
* synchronization will be used even if a stream only uses a single |
|
* SoundWire segment. |
|
*/ |
|
struct sdw_bus { |
|
struct device *dev; |
|
struct sdw_master_device *md; |
|
unsigned int link_id; |
|
int id; |
|
struct list_head slaves; |
|
DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); |
|
struct mutex bus_lock; |
|
struct mutex msg_lock; |
|
int (*compute_params)(struct sdw_bus *bus); |
|
const struct sdw_master_ops *ops; |
|
const struct sdw_master_port_ops *port_ops; |
|
struct sdw_bus_params params; |
|
struct sdw_master_prop prop; |
|
struct list_head m_rt_list; |
|
#ifdef CONFIG_DEBUG_FS |
|
struct dentry *debugfs; |
|
#endif |
|
struct sdw_defer defer_msg; |
|
unsigned int clk_stop_timeout; |
|
u32 bank_switch_timeout; |
|
bool multi_link; |
|
int hw_sync_min_links; |
|
}; |
|
|
|
int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, |
|
struct fwnode_handle *fwnode); |
|
void sdw_bus_master_delete(struct sdw_bus *bus); |
|
|
|
/** |
|
* sdw_port_config: Master or Slave Port configuration |
|
* |
|
* @num: Port number |
|
* @ch_mask: channels mask for port |
|
*/ |
|
struct sdw_port_config { |
|
unsigned int num; |
|
unsigned int ch_mask; |
|
}; |
|
|
|
/** |
|
* sdw_stream_config: Master or Slave stream configuration |
|
* |
|
* @frame_rate: Audio frame rate of the stream, in Hz |
|
* @ch_count: Channel count of the stream |
|
* @bps: Number of bits per audio sample |
|
* @direction: Data direction |
|
* @type: Stream type PCM or PDM |
|
*/ |
|
struct sdw_stream_config { |
|
unsigned int frame_rate; |
|
unsigned int ch_count; |
|
unsigned int bps; |
|
enum sdw_data_direction direction; |
|
enum sdw_stream_type type; |
|
}; |
|
|
|
/** |
|
* sdw_stream_state: Stream states |
|
* |
|
* @SDW_STREAM_ALLOCATED: New stream allocated. |
|
* @SDW_STREAM_CONFIGURED: Stream configured |
|
* @SDW_STREAM_PREPARED: Stream prepared |
|
* @SDW_STREAM_ENABLED: Stream enabled |
|
* @SDW_STREAM_DISABLED: Stream disabled |
|
* @SDW_STREAM_DEPREPARED: Stream de-prepared |
|
* @SDW_STREAM_RELEASED: Stream released |
|
*/ |
|
enum sdw_stream_state { |
|
SDW_STREAM_ALLOCATED = 0, |
|
SDW_STREAM_CONFIGURED = 1, |
|
SDW_STREAM_PREPARED = 2, |
|
SDW_STREAM_ENABLED = 3, |
|
SDW_STREAM_DISABLED = 4, |
|
SDW_STREAM_DEPREPARED = 5, |
|
SDW_STREAM_RELEASED = 6, |
|
}; |
|
|
|
/** |
|
* sdw_stream_params: Stream parameters |
|
* |
|
* @rate: Sampling frequency, in Hz |
|
* @ch_count: Number of channels |
|
* @bps: bits per channel sample |
|
*/ |
|
struct sdw_stream_params { |
|
unsigned int rate; |
|
unsigned int ch_count; |
|
unsigned int bps; |
|
}; |
|
|
|
/** |
|
* sdw_stream_runtime: Runtime stream parameters |
|
* |
|
* @name: SoundWire stream name |
|
* @params: Stream parameters |
|
* @state: Current state of the stream |
|
* @type: Stream type PCM or PDM |
|
* @master_list: List of Master runtime(s) in this stream. |
|
* master_list can contain only one m_rt per Master instance |
|
* for a stream |
|
* @m_rt_count: Count of Master runtime(s) in this stream |
|
*/ |
|
struct sdw_stream_runtime { |
|
const char *name; |
|
struct sdw_stream_params params; |
|
enum sdw_stream_state state; |
|
enum sdw_stream_type type; |
|
struct list_head master_list; |
|
int m_rt_count; |
|
}; |
|
|
|
struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name); |
|
void sdw_release_stream(struct sdw_stream_runtime *stream); |
|
|
|
int sdw_compute_params(struct sdw_bus *bus); |
|
|
|
int sdw_stream_add_master(struct sdw_bus *bus, |
|
struct sdw_stream_config *stream_config, |
|
struct sdw_port_config *port_config, |
|
unsigned int num_ports, |
|
struct sdw_stream_runtime *stream); |
|
int sdw_stream_add_slave(struct sdw_slave *slave, |
|
struct sdw_stream_config *stream_config, |
|
struct sdw_port_config *port_config, |
|
unsigned int num_ports, |
|
struct sdw_stream_runtime *stream); |
|
int sdw_stream_remove_master(struct sdw_bus *bus, |
|
struct sdw_stream_runtime *stream); |
|
int sdw_stream_remove_slave(struct sdw_slave *slave, |
|
struct sdw_stream_runtime *stream); |
|
int sdw_startup_stream(void *sdw_substream); |
|
int sdw_prepare_stream(struct sdw_stream_runtime *stream); |
|
int sdw_enable_stream(struct sdw_stream_runtime *stream); |
|
int sdw_disable_stream(struct sdw_stream_runtime *stream); |
|
int sdw_deprepare_stream(struct sdw_stream_runtime *stream); |
|
void sdw_shutdown_stream(void *sdw_substream); |
|
int sdw_bus_prep_clk_stop(struct sdw_bus *bus); |
|
int sdw_bus_clk_stop(struct sdw_bus *bus); |
|
int sdw_bus_exit_clk_stop(struct sdw_bus *bus); |
|
|
|
/* messaging and data APIs */ |
|
|
|
int sdw_read(struct sdw_slave *slave, u32 addr); |
|
int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); |
|
int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value); |
|
int sdw_read_no_pm(struct sdw_slave *slave, u32 addr); |
|
int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); |
|
int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); |
|
|
|
#endif /* __SOUNDWIRE_H */
|
|
|