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48 lines
1.7 KiB
48 lines
1.7 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Simple Reset Controller ops |
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* |
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* Based on Allwinner SoCs Reset Controller driver |
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* |
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* Copyright 2013 Maxime Ripard |
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* |
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* Maxime Ripard <[email protected]> |
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*/ |
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#ifndef __RESET_SIMPLE_H__ |
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#define __RESET_SIMPLE_H__ |
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#include <linux/io.h> |
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#include <linux/reset-controller.h> |
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#include <linux/spinlock.h> |
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/** |
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* struct reset_simple_data - driver data for simple reset controllers |
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* @lock: spinlock to protect registers during read-modify-write cycles |
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* @membase: memory mapped I/O register range |
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* @rcdev: reset controller device base structure |
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* @active_low: if true, bits are cleared to assert the reset. Otherwise, bits |
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* are set to assert the reset. Note that this says nothing about |
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* the voltage level of the actual reset line. |
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* @status_active_low: if true, bits read back as cleared while the reset is |
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* asserted. Otherwise, bits read back as set while the |
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* reset is asserted. |
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* @reset_us: Minimum delay in microseconds needed that needs to be |
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* waited for between an assert and a deassert to reset the |
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* device. If multiple consumers with different delay |
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* requirements are connected to this controller, it must |
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* be the largest minimum delay. 0 means that such a delay is |
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* unknown and the reset operation is unsupported. |
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*/ |
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struct reset_simple_data { |
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spinlock_t lock; |
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void __iomem *membase; |
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struct reset_controller_dev rcdev; |
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bool active_low; |
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bool status_active_low; |
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unsigned int reset_us; |
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}; |
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extern const struct reset_control_ops reset_simple_ops; |
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#endif /* __RESET_SIMPLE_H__ */
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